Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272085
Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong
In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.
{"title":"Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode","authors":"Shiyang Zhu, H. Yu, S. Whang, J.H. Chen, C. Shen, Chunxiang Zhu, S.J. Lee, M. Li, D. Chan, W. Yoo, A. Du, C. Tung, J. Singh, A. Chin, D. Kwong","doi":"10.1109/ISDRS.2003.1272085","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272085","url":null,"abstract":"In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO/sub 2/ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi/sub 2-x/ (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420/spl deg/C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132758265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272098
Hui Yu, Biao Li, Xin Zhang
Laser processing is widely used since it not only makes manufacturing cheaper, faster, cleaner, and more accurate but also opens up entirely new technologies and manufacturing methods that are simply not available using standard techniques. In this paper, we demonstrate the use of a beam-scanning laser system for direct writing 3-D microstructures in a negative photosensitive polymer (SU-8). Furthermore, with the aid of an auxiliary laser alignment setup, this technology could be readily extended to the flexible fabrication of 3-D multilayer microstructures, which promise to be of great importance for the coming biotechnology revolution.
{"title":"Rapid prototyping of 3D microstructures by direct scanning laser writing","authors":"Hui Yu, Biao Li, Xin Zhang","doi":"10.1109/ISDRS.2003.1272098","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272098","url":null,"abstract":"Laser processing is widely used since it not only makes manufacturing cheaper, faster, cleaner, and more accurate but also opens up entirely new technologies and manufacturing methods that are simply not available using standard techniques. In this paper, we demonstrate the use of a beam-scanning laser system for direct writing 3-D microstructures in a negative photosensitive polymer (SU-8). Furthermore, with the aid of an auxiliary laser alignment setup, this technology could be readily extended to the flexible fabrication of 3-D multilayer microstructures, which promise to be of great importance for the coming biotechnology revolution.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134288310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272185
J. Booske
The microwave power is successfully utilized to rapidly heat a variety of materials, including Si at 150 /spl deg/C/s to 1200 /spl deg/C and SiC at 400 /spl deg/C/s to 2000 /spl deg/C. In this paper with Si microwave RTP, we have demonstrated ultra shallow junctions that exceed lamp-based RTP capabilities and satisfy the 90 nm technology node. The comparative experiment has been conducted between microwave RTP and optical lamp RTP. Comparison sheet resistance-junction depth curve for microwave and lamp-based p-type annealing results and time-temperature profile for a high-power microwave spike annealing are studied by experiments.
{"title":"Microwave heating for advanced semiconductor processing","authors":"J. Booske","doi":"10.1109/ISDRS.2003.1272185","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272185","url":null,"abstract":"The microwave power is successfully utilized to rapidly heat a variety of materials, including Si at 150 /spl deg/C/s to 1200 /spl deg/C and SiC at 400 /spl deg/C/s to 2000 /spl deg/C. In this paper with Si microwave RTP, we have demonstrated ultra shallow junctions that exceed lamp-based RTP capabilities and satisfy the 90 nm technology node. The comparative experiment has been conducted between microwave RTP and optical lamp RTP. Comparison sheet resistance-junction depth curve for microwave and lamp-based p-type annealing results and time-temperature profile for a high-power microwave spike annealing are studied by experiments.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271955
S. Stockman, A. Kim, M. Misra, P. Grillot, L. Cook, S. Watanabe, R. Mann, L. Hudson, W. Gotz, M. Krames, D. Steigerwald, P. S. Martin, F. Wall, F. Steranka
We review the current state-of-the-art in high-power (>1 W) GaN LED technology, and highlight current challenges in MOCVD epitaxy, device design, and high-volume manufacturing. We also describe recent developments in technology for high-power GaN-based LEDs which are operated beyond 5 W/LED with high efficiency (50 lm/W green, >30 lm/W white) and excellent reliability, and preview future challenges in solid state lighting and display applications.
我们回顾了目前高功率(> 1w) GaN LED技术的最新进展，并强调了MOCVD外延，器件设计和大批量制造方面的当前挑战。我们还描述了大功率氮化镓基LED技术的最新发展，其工作效率超过5 W/LED，效率高(50 lm/W绿色，>30 lm/W白色)，可靠性高，并预览了固态照明和显示应用的未来挑战。
{"title":"High-power GaN-based LEDs for lighting and display applications","authors":"S. Stockman, A. Kim, M. Misra, P. Grillot, L. Cook, S. Watanabe, R. Mann, L. Hudson, W. Gotz, M. Krames, D. Steigerwald, P. S. Martin, F. Wall, F. Steranka","doi":"10.1109/ISDRS.2003.1271955","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271955","url":null,"abstract":"We review the current state-of-the-art in high-power (>1 W) GaN LED technology, and highlight current challenges in MOCVD epitaxy, device design, and high-volume manufacturing. We also describe recent developments in technology for high-power GaN-based LEDs which are operated beyond 5 W/LED with high efficiency (50 lm/W green, >30 lm/W white) and excellent reliability, and preview future challenges in solid state lighting and display applications.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"43 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272162
M. Thomason, J. Prasad, J. De Greve
Reverse Short Channel Effect (RSCE) is caused by the increased channel concentration with decreasing gate length in submicron devices. It has been reported that the source for this concentration increase is the point defect enhanced localize diffusion near the gate edge that causes boron to pile-up near oxide/silicon interface. In this work we have performed experimental studies to identify the process steps that decrease the extent of the RCSE not only in the NMOS devices but in PMOS devices as well. Various experiments were performed to understand the effects of different implant conditions and process steps variations on RCSE.
{"title":"Suppression of the reverse short channel effect in sub-micron CMOS devices","authors":"M. Thomason, J. Prasad, J. De Greve","doi":"10.1109/ISDRS.2003.1272162","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272162","url":null,"abstract":"Reverse Short Channel Effect (RSCE) is caused by the increased channel concentration with decreasing gate length in submicron devices. It has been reported that the source for this concentration increase is the point defect enhanced localize diffusion near the gate edge that causes boron to pile-up near oxide/silicon interface. In this work we have performed experimental studies to identify the process steps that decrease the extent of the RCSE not only in the NMOS devices but in PMOS devices as well. Various experiments were performed to understand the effects of different implant conditions and process steps variations on RCSE.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272195
C. Shih, C. Lien
In this paper the analytical channel potential solution and short-channel effect model are derived for sub-100 nm MOSFET with graded junction and halo doped channel. The dependence of the counter-doping due to graded source/drain junction is presented for the first time. Scale-length approach for solving 2D poisson's equation is extended to find the channel potential successfully. By this model, the lateral non-uniform channel devices can be reduced into uniform devices with shorter lengths. The effects of the halo and graded junction on short-channel MOSFET can be illustrated from the viewpoints of the distributed effective-doping concentration and the exponential roll-off behavior.
{"title":"An analytical model of short-channel effect for sub-100 nm MOSFET with graded junction and halo doped channel","authors":"C. Shih, C. Lien","doi":"10.1109/ISDRS.2003.1272195","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272195","url":null,"abstract":"In this paper the analytical channel potential solution and short-channel effect model are derived for sub-100 nm MOSFET with graded junction and halo doped channel. The dependence of the counter-doping due to graded source/drain junction is presented for the first time. Scale-length approach for solving 2D poisson's equation is extended to find the channel potential successfully. By this model, the lateral non-uniform channel devices can be reduced into uniform devices with shorter lengths. The effects of the halo and graded junction on short-channel MOSFET can be illustrated from the viewpoints of the distributed effective-doping concentration and the exponential roll-off behavior.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122277204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271958
J. M. Shah, Y.-L. Li, T. Gessmann, E. Schubert
In this paper, we described the fabrication of GaN based diodes from two different structures , a bulk GaN p-n junction structure and a p-n junction structure incorporating a p-type AlGaN/GaN superlattice. This superlattice structure is included to facilitate ohmic contact formation. We measure the I-V characteristics of the p-n junctions at room temperature. The lower ideality factor to the improved transport characteristics of p-type AlGaN/GaN superlattices are attributed. The temperature dependence of ideality factor is obtained by measuring the I-V characteristics of the GaN p-n juction with the superlattice structure at three different temperatures. In addition, contact become less rectifying at higher temperatures and hence result in more ohmic behavior. This decreases the ideality factor of the metal-semiconductor juction, which in turn reduces the overall ideality factor. This interpretation is in excellent agreement with the theoretical model and the experimental results.
{"title":"Experimental analysis and a new model for the high ideality factors in GaN-based diodes","authors":"J. M. Shah, Y.-L. Li, T. Gessmann, E. Schubert","doi":"10.1109/ISDRS.2003.1271958","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271958","url":null,"abstract":"In this paper, we described the fabrication of GaN based diodes from two different structures , a bulk GaN p-n junction structure and a p-n junction structure incorporating a p-type AlGaN/GaN superlattice. This superlattice structure is included to facilitate ohmic contact formation. We measure the I-V characteristics of the p-n junctions at room temperature. The lower ideality factor to the improved transport characteristics of p-type AlGaN/GaN superlattices are attributed. The temperature dependence of ideality factor is obtained by measuring the I-V characteristics of the GaN p-n juction with the superlattice structure at three different temperatures. In addition, contact become less rectifying at higher temperatures and hence result in more ohmic behavior. This decreases the ideality factor of the metal-semiconductor juction, which in turn reduces the overall ideality factor. This interpretation is in excellent agreement with the theoretical model and the experimental results.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122370671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272060
V. Ryzhii, M. Shur
In deep submicron field effect transistors, the velocity of the surface plasma waves is more than an order of magnitude higher that the electron drift velocity and, therefore, excitation, propagation and generation of these waves should allow for operation at terahertz frequencies. In the plasma wave excitation regime, deep submicron transistors with high electron mobility could be used as tunable resonant detectors of terahertz radiation.
{"title":"Plasma wave electronics devices","authors":"V. Ryzhii, M. Shur","doi":"10.1109/ISDRS.2003.1272060","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272060","url":null,"abstract":"In deep submicron field effect transistors, the velocity of the surface plasma waves is more than an order of magnitude higher that the electron drift velocity and, therefore, excitation, propagation and generation of these waves should allow for operation at terahertz frequencies. In the plasma wave excitation regime, deep submicron transistors with high electron mobility could be used as tunable resonant detectors of terahertz radiation.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271956
D. S. Lee, A. Steckl, U. Hommerich, E. Nyein, P. Rack, James M. Fitz-Gerald, J. Zavada
In this paper, we report on the growth of in-situ Tm-doped Al/sub x/Ga/sub 1-x/N films and the corresponding effect of Al composition on the EL emission. PL and CL show almost same trend as EL with various Al compositions. The 465-nm emission is barely present at x=0.16, it becomes very clear for x/spl ges/0.39, and it dominates for x/spl ges/0.81. The EL emission at 802 nm experienced the opposite trend, decreasing with Al composition. We have confirmed that blue EL emission becomes dominant over IR emission with increasing Al composition in the Al/sub x/Ga/sub 1-x/N host.
{"title":"Enhanced blue emission from Tm-doped Al/sub x/Ga/sub 1-x/N electroluminescent thin films","authors":"D. S. Lee, A. Steckl, U. Hommerich, E. Nyein, P. Rack, James M. Fitz-Gerald, J. Zavada","doi":"10.1109/ISDRS.2003.1271956","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271956","url":null,"abstract":"In this paper, we report on the growth of in-situ Tm-doped Al/sub x/Ga/sub 1-x/N films and the corresponding effect of Al composition on the EL emission. PL and CL show almost same trend as EL with various Al compositions. The 465-nm emission is barely present at x=0.16, it becomes very clear for x/spl ges/0.39, and it dominates for x/spl ges/0.81. The EL emission at 802 nm experienced the opposite trend, decreasing with Al composition. We have confirmed that blue EL emission becomes dominant over IR emission with increasing Al composition in the Al/sub x/Ga/sub 1-x/N host.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130417278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272173
A. Conway, J. Li, P. Asbeck
This paper reports pulsed I-V characteristics of AlGaN/GaN HFETs fabricated with gate regions recessed into the AlGaN barrier layer with different recess geometries. Pulsed I-V characteristics are known to correlate with rf ouput power measurements vs bias, and are an important estimator of "knee voltage walkout" and "current slump" effects in the nitride HFETs. Our measurements indicate that the knee voltage walkout is strongly dependent on the depth of the recessed region, and that the walkout is minimized in devices with shallower recess depth. The results strongly support the model that current slump is due to surface traps. An effective trap time constant of 10 /spl mu/sec is extracted for these devices.
{"title":"Effects of gate recess depth on pulsed I-V characteristics of AlGaN/GaN HFETs","authors":"A. Conway, J. Li, P. Asbeck","doi":"10.1109/ISDRS.2003.1272173","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272173","url":null,"abstract":"This paper reports pulsed I-V characteristics of AlGaN/GaN HFETs fabricated with gate regions recessed into the AlGaN barrier layer with different recess geometries. Pulsed I-V characteristics are known to correlate with rf ouput power measurements vs bias, and are an important estimator of \"knee voltage walkout\" and \"current slump\" effects in the nitride HFETs. Our measurements indicate that the knee voltage walkout is strongly dependent on the depth of the recessed region, and that the walkout is minimized in devices with shallower recess depth. The results strongly support the model that current slump is due to surface traps. An effective trap time constant of 10 /spl mu/sec is extracted for these devices.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127185815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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