Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272097
M. Datta, M. Pruessner, D. Kelly, R. Ghodssi
Theoretical analysis of an optical waveguide based horizontal resonant microcavity filter in InP, which is tunable within a broad wavelength range of 350 nm by MEMS electrostatic actuation is presented in this paper. The microcavity is formed between the input and output waveguides by fabricating monolithically integrated horizontal distributed Bragg reflector (DBR) mirrors. The length of the microcavity is varied by a total of 200 nm in steps of 10 nm to meet the Fabry-Perot resonant condition. Spectral response of the proposed resonant filter is numerically simulated using typical values for monolithic input beam size (3 /spl mu/m/spl times/1.5 /spl mu/m) and first-order mirror reflectivities.
{"title":"MEMS-tunable novel monolithic optical filters in InP with horizontal Bragg mirrors","authors":"M. Datta, M. Pruessner, D. Kelly, R. Ghodssi","doi":"10.1109/ISDRS.2003.1272097","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272097","url":null,"abstract":"Theoretical analysis of an optical waveguide based horizontal resonant microcavity filter in InP, which is tunable within a broad wavelength range of 350 nm by MEMS electrostatic actuation is presented in this paper. The microcavity is formed between the input and output waveguides by fabricating monolithically integrated horizontal distributed Bragg reflector (DBR) mirrors. The length of the microcavity is varied by a total of 200 nm in steps of 10 nm to meet the Fabry-Perot resonant condition. Spectral response of the proposed resonant filter is numerically simulated using typical values for monolithic input beam size (3 /spl mu/m/spl times/1.5 /spl mu/m) and first-order mirror reflectivities.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271998
G. Lucovsky, J. C. Phillips
The purpose of this paper is to develop a physical model for the formation of self-organized, interfacial transition regions between Si and compound semiconductor substrates such as GaN, and SiO/sub 2/ and alternative high-k gate dielectrics. One objective is to identify i) why densities of interfacial Si dangling bonds prior to H-termination are larger by factors of 4-6 at Si-Al/sub 2/O/sub 3/ and Si-ZrO/sub 2/ interfaces compared to Si-SiO/sub 2/ and ii) why interfacial traps, D/sub it/, and C-V hysteresis are up to ten times larger. A second is to show that these interface traps are located in strained Si and GaN regions at their respective dielectric interfaces. The SHG phase angle versus change in film thickness plot for Si-SiO/sub 2/ structures is processed.
{"title":"A new approach to gate stack integrity based on mechanical and electrostatic strain relief in self-organized interfacial suboxide transition regions","authors":"G. Lucovsky, J. C. Phillips","doi":"10.1109/ISDRS.2003.1271998","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271998","url":null,"abstract":"The purpose of this paper is to develop a physical model for the formation of self-organized, interfacial transition regions between Si and compound semiconductor substrates such as GaN, and SiO/sub 2/ and alternative high-k gate dielectrics. One objective is to identify i) why densities of interfacial Si dangling bonds prior to H-termination are larger by factors of 4-6 at Si-Al/sub 2/O/sub 3/ and Si-ZrO/sub 2/ interfaces compared to Si-SiO/sub 2/ and ii) why interfacial traps, D/sub it/, and C-V hysteresis are up to ten times larger. A second is to show that these interface traps are located in strained Si and GaN regions at their respective dielectric interfaces. The SHG phase angle versus change in film thickness plot for Si-SiO/sub 2/ structures is processed.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116507662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272142
D. Woolard, Weidong Zhang, B. Gelmont
A novel type of interband-RTD (I-RTD) based upon staggered-bandgap heterostructures was investigated. A detailed theoretical analysis of the time-dependent characteristics of an I-RTD based upon a type-II resonant tunneling heterostructure is presented. Specifically, an AlGaSb/InAs/AlGaSb double-barrier structure was considered to determine the influence of multi-band transport effects on the static and dynamic behavior of the I-RTD device.
{"title":"A novel interband-resonant-tunneling-diode(I-RTD) based high-frequency oscillator","authors":"D. Woolard, Weidong Zhang, B. Gelmont","doi":"10.1109/ISDRS.2003.1272142","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272142","url":null,"abstract":"A novel type of interband-RTD (I-RTD) based upon staggered-bandgap heterostructures was investigated. A detailed theoretical analysis of the time-dependent characteristics of an I-RTD based upon a type-II resonant tunneling heterostructure is presented. Specifically, an AlGaSb/InAs/AlGaSb double-barrier structure was considered to determine the influence of multi-band transport effects on the static and dynamic behavior of the I-RTD device.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116909378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272117
J. Prasad, M. Anser, M. Thomason
Electrical characterization of the MIM (metal-insulator-metal) capacitor for RF circuits used in mixed signal devices is presented in this paper. Characterization and evaluation of Nitride, Oxide or Oxynitride as the dielectric materials is also presented. MIM module structure is a six-mask process with three levels of metallization. Capacitance as a function of dielectric film thickness for various dielectric materials and alloying effects on the silicon nitride MIM capacitor linearity are presented. Hysteresis characterization and modeling is used to improve analog circuit performance.
{"title":"Electrical characterization of dielectrics (oxide, nitride, oxy-nitride) for use in MIM capacitors for mixed signal applications","authors":"J. Prasad, M. Anser, M. Thomason","doi":"10.1109/ISDRS.2003.1272117","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272117","url":null,"abstract":"Electrical characterization of the MIM (metal-insulator-metal) capacitor for RF circuits used in mixed signal devices is presented in this paper. Characterization and evaluation of Nitride, Oxide or Oxynitride as the dielectric materials is also presented. MIM module structure is a six-mask process with three levels of metallization. Capacitance as a function of dielectric film thickness for various dielectric materials and alloying effects on the silicon nitride MIM capacitor linearity are presented. Hysteresis characterization and modeling is used to improve analog circuit performance.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121254585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272102
Y. Bai, Z. Dilli, N. Goldsman, G. Metze
The numerical modeling of on-chip inductor structures, applied to the comparison of inductor geometries was studied. The frequency-dependence of inductor characteristics depends on skin effect in the conductors and induced currents in the semiconductor substrates.
{"title":"Frequency-dependent modeling of on-chip inductors on lossy substrates","authors":"Y. Bai, Z. Dilli, N. Goldsman, G. Metze","doi":"10.1109/ISDRS.2003.1272102","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272102","url":null,"abstract":"The numerical modeling of on-chip inductor structures, applied to the comparison of inductor geometries was studied. The frequency-dependence of inductor characteristics depends on skin effect in the conductors and induced currents in the semiconductor substrates.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271982
J. Ackaert, T. Vermeulen, A. Lowe, S. Boonen, T. Yao, J. Prasad, M. Thomason, J. van Houdt, R. Degraeve, L. Haspeslagh, P. Hendrickx
The purpose of this paper is to characterize, to compare different types of tunnel oxides and to determine the impact on the MB (Moving Bit measurement) issues. The measurements and comparison carried out for the following tunnel oxide thickness in the range of 8 to 10 nm is used. They are: (1) Dry oxidation at 900 C which gives acceptable oxide quality in the thickness range of 100 /spl Aring/ (2) 5% O/sub 2/ diluted oxidation at 900 C, (3) 5% O/sub 2/ diluted oxidation at 960 C and (4) Wet oxidation at 750 C which gives superior results even for a minimal oxide thickness of 88.9 /spl Aring/.
{"title":"Characterization of tunnel oxides for non-volatile memory (NVM) applications","authors":"J. Ackaert, T. Vermeulen, A. Lowe, S. Boonen, T. Yao, J. Prasad, M. Thomason, J. van Houdt, R. Degraeve, L. Haspeslagh, P. Hendrickx","doi":"10.1109/ISDRS.2003.1271982","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271982","url":null,"abstract":"The purpose of this paper is to characterize, to compare different types of tunnel oxides and to determine the impact on the MB (Moving Bit measurement) issues. The measurements and comparison carried out for the following tunnel oxide thickness in the range of 8 to 10 nm is used. They are: (1) Dry oxidation at 900 C which gives acceptable oxide quality in the thickness range of 100 /spl Aring/ (2) 5% O/sub 2/ diluted oxidation at 900 C, (3) 5% O/sub 2/ diluted oxidation at 960 C and (4) Wet oxidation at 750 C which gives superior results even for a minimal oxide thickness of 88.9 /spl Aring/.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130904142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272372
T. Suligoj, Haitao Liu, J. Sin, K. Tsui, K.J. Chen, P. Biljanovic, K. Wang
In this paper, we present a scaled transistor processed with the improved technology, resulting in the enhancement of its electrical performance. The electrical characteristics such as collector-emitter breakdown, charge sharing of the processed transistor is presented. The electrical properties of HCBTs are compared with the existing LBTs (Lateral Bipolar Transistors). This HCBT technology was applied in the BiCMOS integration with FinFETs.
{"title":"A low-cost Horizontal Current Bipolar Transistor (HCBT) technology for the BiCMOS integration with FinFETs","authors":"T. Suligoj, Haitao Liu, J. Sin, K. Tsui, K.J. Chen, P. Biljanovic, K. Wang","doi":"10.1109/ISDRS.2003.1272372","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272372","url":null,"abstract":"In this paper, we present a scaled transistor processed with the improved technology, resulting in the enhancement of its electrical performance. The electrical characteristics such as collector-emitter breakdown, charge sharing of the processed transistor is presented. The electrical properties of HCBTs are compared with the existing LBTs (Lateral Bipolar Transistors). This HCBT technology was applied in the BiCMOS integration with FinFETs.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128330503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272148
T. Hiramoto, T. Nagumo, T. Ohtou
A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.
{"title":"Low-power device design of fully-depleted SOI MOSFETs","authors":"T. Hiramoto, T. Nagumo, T. Ohtou","doi":"10.1109/ISDRS.2003.1272148","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272148","url":null,"abstract":"A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272150
F. Yu, M. Cheng
An analytical heat flow model, accounting for heat exchanges among devices via interconnect/poly lines and heat loss to oxide is developed and applied to study heat flow in SOI current mirror structures. An SOI nMOS current mirror illustrates the thermal coupling and heat flow through the interconnect. The interconnect provides an efficient heat loss medium for the SOI circuit.
{"title":"Heat flow in SOI current mirrors","authors":"F. Yu, M. Cheng","doi":"10.1109/ISDRS.2003.1272150","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272150","url":null,"abstract":"An analytical heat flow model, accounting for heat exchanges among devices via interconnect/poly lines and heat loss to oxide is developed and applied to study heat flow in SOI current mirror structures. An SOI nMOS current mirror illustrates the thermal coupling and heat flow through the interconnect. The interconnect provides an efficient heat loss medium for the SOI circuit.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126916702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Magno, J. B. Boos, P. Campbell, B. R. Bennett, E. Glaser, B. Tinkham, M. Ancona, K. Hobart, Doe Park, N. Papanicolaou
In this paper we report on the development of an npn double bipolar transistor with an InGaSb base and InAlAsSb alloys for the emitter and collector. The combination of alloys with a lattice constant of 6.2 a is illustrated. Silvaco simulation indicate that large collector currents, I/sub c/, are possible with this system at smaller base emitter voltages, V/sub BE/, than are measured in the InP based HBT. An important advantage of this system is that the conduction band offset between the InGaSb base and the InAlAsSb may be tuned over a large range while maintaining large valence band offsets that are useful for minimizing parasitic base currents.
{"title":"InAlAsSb/InGaSb double heterojunction bipolar transistor","authors":"R. Magno, J. B. Boos, P. Campbell, B. R. Bennett, E. Glaser, B. Tinkham, M. Ancona, K. Hobart, Doe Park, N. Papanicolaou","doi":"10.1049/EL:20058107","DOIUrl":"https://doi.org/10.1049/EL:20058107","url":null,"abstract":"In this paper we report on the development of an npn double bipolar transistor with an InGaSb base and InAlAsSb alloys for the emitter and collector. The combination of alloys with a lattice constant of 6.2 a is illustrated. Silvaco simulation indicate that large collector currents, I/sub c/, are possible with this system at smaller base emitter voltages, V/sub BE/, than are measured in the InP based HBT. An important advantage of this system is that the conduction band offset between the InGaSb base and the InAlAsSb may be tuned over a large range while maintaining large valence band offsets that are useful for minimizing parasitic base currents.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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