Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272057
W. Kruppa, J. B. Boos, B. R. Bennett, B. Tinkham
Measurements of the low-frequency noise characteristics of AlSb/InAsSb HEMTs as a function of temperature and illumination are reported in this paper. The primary focus in this paper is on devices in which a digital alloy superlattice of InAs/InSb was used to form an InAsSb channel. This appears to be related to the lower stress in this channel, which is matched to AlSb.
{"title":"Low-frequency noise characteristics of AlSb/InAsSb HEMTs as a function of temperature and illumination","authors":"W. Kruppa, J. B. Boos, B. R. Bennett, B. Tinkham","doi":"10.1109/ISDRS.2003.1272057","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272057","url":null,"abstract":"Measurements of the low-frequency noise characteristics of AlSb/InAsSb HEMTs as a function of temperature and illumination are reported in this paper. The primary focus in this paper is on devices in which a digital alloy superlattice of InAs/InSb was used to form an InAsSb channel. This appears to be related to the lower stress in this channel, which is matched to AlSb.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131507280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272097
M. Datta, M. Pruessner, D. Kelly, R. Ghodssi
Theoretical analysis of an optical waveguide based horizontal resonant microcavity filter in InP, which is tunable within a broad wavelength range of 350 nm by MEMS electrostatic actuation is presented in this paper. The microcavity is formed between the input and output waveguides by fabricating monolithically integrated horizontal distributed Bragg reflector (DBR) mirrors. The length of the microcavity is varied by a total of 200 nm in steps of 10 nm to meet the Fabry-Perot resonant condition. Spectral response of the proposed resonant filter is numerically simulated using typical values for monolithic input beam size (3 /spl mu/m/spl times/1.5 /spl mu/m) and first-order mirror reflectivities.
{"title":"MEMS-tunable novel monolithic optical filters in InP with horizontal Bragg mirrors","authors":"M. Datta, M. Pruessner, D. Kelly, R. Ghodssi","doi":"10.1109/ISDRS.2003.1272097","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272097","url":null,"abstract":"Theoretical analysis of an optical waveguide based horizontal resonant microcavity filter in InP, which is tunable within a broad wavelength range of 350 nm by MEMS electrostatic actuation is presented in this paper. The microcavity is formed between the input and output waveguides by fabricating monolithically integrated horizontal distributed Bragg reflector (DBR) mirrors. The length of the microcavity is varied by a total of 200 nm in steps of 10 nm to meet the Fabry-Perot resonant condition. Spectral response of the proposed resonant filter is numerically simulated using typical values for monolithic input beam size (3 /spl mu/m/spl times/1.5 /spl mu/m) and first-order mirror reflectivities.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272117
J. Prasad, M. Anser, M. Thomason
Electrical characterization of the MIM (metal-insulator-metal) capacitor for RF circuits used in mixed signal devices is presented in this paper. Characterization and evaluation of Nitride, Oxide or Oxynitride as the dielectric materials is also presented. MIM module structure is a six-mask process with three levels of metallization. Capacitance as a function of dielectric film thickness for various dielectric materials and alloying effects on the silicon nitride MIM capacitor linearity are presented. Hysteresis characterization and modeling is used to improve analog circuit performance.
{"title":"Electrical characterization of dielectrics (oxide, nitride, oxy-nitride) for use in MIM capacitors for mixed signal applications","authors":"J. Prasad, M. Anser, M. Thomason","doi":"10.1109/ISDRS.2003.1272117","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272117","url":null,"abstract":"Electrical characterization of the MIM (metal-insulator-metal) capacitor for RF circuits used in mixed signal devices is presented in this paper. Characterization and evaluation of Nitride, Oxide or Oxynitride as the dielectric materials is also presented. MIM module structure is a six-mask process with three levels of metallization. Capacitance as a function of dielectric film thickness for various dielectric materials and alloying effects on the silicon nitride MIM capacitor linearity are presented. Hysteresis characterization and modeling is used to improve analog circuit performance.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121254585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271983
E. Sargent
We review light production from quantum dot nanocrystals embedded in a semiconducting polymer. Integrable optoelectronics is facilitated in this processible material system - one which may conveniently be combined with silicon electronics, passive optics, and RF platforms. Synthetic conditions determine nanocrystal diameter and thereby tune, through the quantum size effect, the spectrum of optical emissions from the quantum dots. We show that it is possible to span across and beyond the 1.3-1.6 /spl mu/m spectrum of optical communications. Nonradiative recombination from the nanocrystals' surface is addressed by choosing stabilizing, passivating organic ligands which nevertheless permit energy transfer from polymer to nanocrystals.
{"title":"Telecom-wavelength electroluminescence from processible quantum dot nanocrystals","authors":"E. Sargent","doi":"10.1109/ISDRS.2003.1271983","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271983","url":null,"abstract":"We review light production from quantum dot nanocrystals embedded in a semiconducting polymer. Integrable optoelectronics is facilitated in this processible material system - one which may conveniently be combined with silicon electronics, passive optics, and RF platforms. Synthetic conditions determine nanocrystal diameter and thereby tune, through the quantum size effect, the spectrum of optical emissions from the quantum dots. We show that it is possible to span across and beyond the 1.3-1.6 /spl mu/m spectrum of optical communications. Nonradiative recombination from the nanocrystals' surface is addressed by choosing stabilizing, passivating organic ligands which nevertheless permit energy transfer from polymer to nanocrystals.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121276667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272127
Yingda Dong, Yun Wei, Z. Griffith, M. Urteaga, M. Dahlstrom, M. Rodwell
In a mesa structured HBT, a large portion of C/sub bc/originates from the extrinsic base-collector region under the base contact. To reduce extrinsic C/sub bc/, an HBT structure with a selectively implanted collector pedestal and MBE growth, under the HBT intrinsic region is reported. The fabrication steps of the device are implant window and Si ion implant, implant mask removal and HT annealing, HBT structure regrowth and triple-mesa HBT fabrication. The results exhibit low I/sub cbo/ and hence high junction quality can be obtained in a collector pedestal process incorporating regrowth.
{"title":"InP heterojunction bipolar transistor with a selectively implanted collector pedestal","authors":"Yingda Dong, Yun Wei, Z. Griffith, M. Urteaga, M. Dahlstrom, M. Rodwell","doi":"10.1109/ISDRS.2003.1272127","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272127","url":null,"abstract":"In a mesa structured HBT, a large portion of C/sub bc/originates from the extrinsic base-collector region under the base contact. To reduce extrinsic C/sub bc/, an HBT structure with a selectively implanted collector pedestal and MBE growth, under the HBT intrinsic region is reported. The fabrication steps of the device are implant window and Si ion implant, implant mask removal and HT annealing, HBT structure regrowth and triple-mesa HBT fabrication. The results exhibit low I/sub cbo/ and hence high junction quality can be obtained in a collector pedestal process incorporating regrowth.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122300163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1271998
G. Lucovsky, J. C. Phillips
The purpose of this paper is to develop a physical model for the formation of self-organized, interfacial transition regions between Si and compound semiconductor substrates such as GaN, and SiO/sub 2/ and alternative high-k gate dielectrics. One objective is to identify i) why densities of interfacial Si dangling bonds prior to H-termination are larger by factors of 4-6 at Si-Al/sub 2/O/sub 3/ and Si-ZrO/sub 2/ interfaces compared to Si-SiO/sub 2/ and ii) why interfacial traps, D/sub it/, and C-V hysteresis are up to ten times larger. A second is to show that these interface traps are located in strained Si and GaN regions at their respective dielectric interfaces. The SHG phase angle versus change in film thickness plot for Si-SiO/sub 2/ structures is processed.
{"title":"A new approach to gate stack integrity based on mechanical and electrostatic strain relief in self-organized interfacial suboxide transition regions","authors":"G. Lucovsky, J. C. Phillips","doi":"10.1109/ISDRS.2003.1271998","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271998","url":null,"abstract":"The purpose of this paper is to develop a physical model for the formation of self-organized, interfacial transition regions between Si and compound semiconductor substrates such as GaN, and SiO/sub 2/ and alternative high-k gate dielectrics. One objective is to identify i) why densities of interfacial Si dangling bonds prior to H-termination are larger by factors of 4-6 at Si-Al/sub 2/O/sub 3/ and Si-ZrO/sub 2/ interfaces compared to Si-SiO/sub 2/ and ii) why interfacial traps, D/sub it/, and C-V hysteresis are up to ten times larger. A second is to show that these interface traps are located in strained Si and GaN regions at their respective dielectric interfaces. The SHG phase angle versus change in film thickness plot for Si-SiO/sub 2/ structures is processed.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116507662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272160
J. Seminario, Roy A. Araujo, Liuming Yan, Yu Ma
Negative differential resistance (NDR) is a characteristics typical of atomistic systems most likely observed in small organic molecules having electronegative groups, which allow trapping electrons and thus changing the electrical characteristics of the molecule. Here we report high level calculations on small wires of gold atoms that shows the existence of NDR. The analysis of molecular electronic devices using ab initio based methods is presented.
{"title":"The analysis, design, and simulation of molecular electronic devices using ab initio based methods: the negative differential resistance","authors":"J. Seminario, Roy A. Araujo, Liuming Yan, Yu Ma","doi":"10.1109/ISDRS.2003.1272160","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272160","url":null,"abstract":"Negative differential resistance (NDR) is a characteristics typical of atomistic systems most likely observed in small organic molecules having electronegative groups, which allow trapping electrons and thus changing the electrical characteristics of the molecule. Here we report high level calculations on small wires of gold atoms that shows the existence of NDR. The analysis of molecular electronic devices using ab initio based methods is presented.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116407585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272150
F. Yu, M. Cheng
An analytical heat flow model, accounting for heat exchanges among devices via interconnect/poly lines and heat loss to oxide is developed and applied to study heat flow in SOI current mirror structures. An SOI nMOS current mirror illustrates the thermal coupling and heat flow through the interconnect. The interconnect provides an efficient heat loss medium for the SOI circuit.
{"title":"Heat flow in SOI current mirrors","authors":"F. Yu, M. Cheng","doi":"10.1109/ISDRS.2003.1272150","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272150","url":null,"abstract":"An analytical heat flow model, accounting for heat exchanges among devices via interconnect/poly lines and heat loss to oxide is developed and applied to study heat flow in SOI current mirror structures. An SOI nMOS current mirror illustrates the thermal coupling and heat flow through the interconnect. The interconnect provides an efficient heat loss medium for the SOI circuit.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126916702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Magno, J. B. Boos, P. Campbell, B. R. Bennett, E. Glaser, B. Tinkham, M. Ancona, K. Hobart, Doe Park, N. Papanicolaou
In this paper we report on the development of an npn double bipolar transistor with an InGaSb base and InAlAsSb alloys for the emitter and collector. The combination of alloys with a lattice constant of 6.2 a is illustrated. Silvaco simulation indicate that large collector currents, I/sub c/, are possible with this system at smaller base emitter voltages, V/sub BE/, than are measured in the InP based HBT. An important advantage of this system is that the conduction band offset between the InGaSb base and the InAlAsSb may be tuned over a large range while maintaining large valence band offsets that are useful for minimizing parasitic base currents.
{"title":"InAlAsSb/InGaSb double heterojunction bipolar transistor","authors":"R. Magno, J. B. Boos, P. Campbell, B. R. Bennett, E. Glaser, B. Tinkham, M. Ancona, K. Hobart, Doe Park, N. Papanicolaou","doi":"10.1049/EL:20058107","DOIUrl":"https://doi.org/10.1049/EL:20058107","url":null,"abstract":"In this paper we report on the development of an npn double bipolar transistor with an InGaSb base and InAlAsSb alloys for the emitter and collector. The combination of alloys with a lattice constant of 6.2 a is illustrated. Silvaco simulation indicate that large collector currents, I/sub c/, are possible with this system at smaller base emitter voltages, V/sub BE/, than are measured in the InP based HBT. An important advantage of this system is that the conduction band offset between the InGaSb base and the InAlAsSb may be tuned over a large range while maintaining large valence band offsets that are useful for minimizing parasitic base currents.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272148
T. Hiramoto, T. Nagumo, T. Ohtou
A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.
{"title":"Low-power device design of fully-depleted SOI MOSFETs","authors":"T. Hiramoto, T. Nagumo, T. Ohtou","doi":"10.1109/ISDRS.2003.1272148","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272148","url":null,"abstract":"A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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