Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550147
R. Hahn, S. Wagner, S. Krumbholz, H. Reichl
A PEM micro fuel cell system is described which is based on self-breathing PEM micro fuel cells in the power range between 1 mW and 1 W. Micro patterned substrates were used as micro flow fields and replacement of gas diffusion layers (GDL). An analytical model was developed to estimate the losses in such structures and optimize channel design and current collector metallization. A detailed comparison was made between two different designs: pin structures and channel structures. A variety of micro fuel cells with variations of design parameters were tested to verify the model. As a result, micro fuel cell fabrication can be optimized in terms of cell performance and production costs. A maximum power density of 160 mW/cm2 has been achieved with the GDL-less design and a current collector pitch of 400 mum with commercial membrane electrode assemblies.
{"title":"Development of micro fuel cells with organic substrates and electronics manufacturing technologies","authors":"R. Hahn, S. Wagner, S. Krumbholz, H. Reichl","doi":"10.1109/ECTC.2008.4550147","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550147","url":null,"abstract":"A PEM micro fuel cell system is described which is based on self-breathing PEM micro fuel cells in the power range between 1 mW and 1 W. Micro patterned substrates were used as micro flow fields and replacement of gas diffusion layers (GDL). An analytical model was developed to estimate the losses in such structures and optimize channel design and current collector metallization. A detailed comparison was made between two different designs: pin structures and channel structures. A variety of micro fuel cells with variations of design parameters were tested to verify the model. As a result, micro fuel cell fabrication can be optimized in terms of cell performance and production costs. A maximum power density of 160 mW/cm2 has been achieved with the GDL-less design and a current collector pitch of 400 mum with commercial membrane electrode assemblies.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"75 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550229
E. Mintarno, S. Ji
First, this paper discusses a robust and efficient de- embedding technique that can be used for TDR-PNA- simulation correlation in time or frequency domain. Employing the de-embedding technique, TDR-PNA was shown to correlate very well with 2 mV resolution in time- domain, when TDR repeatability is 2 mV. Next, a systematic analysis of memory channel TDR-simulation correlation was detailed. Time domain correlation served as an efficient and straightforward way of capturing impedance discontinuities and crosstalk level. Finally, some design, modeling, and measurement guidelines for platform memory interconnect development were recommended.
{"title":"Time and frequency domain memory channel characterization and correlation methodology","authors":"E. Mintarno, S. Ji","doi":"10.1109/ECTC.2008.4550229","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550229","url":null,"abstract":"First, this paper discusses a robust and efficient de- embedding technique that can be used for TDR-PNA- simulation correlation in time or frequency domain. Employing the de-embedding technique, TDR-PNA was shown to correlate very well with 2 mV resolution in time- domain, when TDR repeatability is 2 mV. Next, a systematic analysis of memory channel TDR-simulation correlation was detailed. Time domain correlation served as an efficient and straightforward way of capturing impedance discontinuities and crosstalk level. Finally, some design, modeling, and measurement guidelines for platform memory interconnect development were recommended.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550132
Y. Mekonnen, J. Schutt-Ainé
The vector-fitting algorithm has been used as the main macromodeling tool for approximating frequency domain responses of complex interconnects and electrical packages (Gustavsen, 1999). In this paper, a new methodology is proposed to fit transfer functions of frequency response data obtained from numerical electromagnetic simulation or measured frequency-domain or time-domain response data. This new method, z-domain vector-fitting (ZDVF), is a formulation of vector- fitting method in the z domain; it has an advantage of faster convergence and better numerical stability compared to the s-domain vector-fitting method(VF). The fast convergence of the method reduces the overall macromodel generation time. The accuracy, numerical stability and convergence speed of VF and ZDVF are compared. Examples are provided to demonstrate the advantage of the ZDVF.
{"title":"Fast broadband macromodeling technique of sampled time/frequency data using z-domain vector-fitting method","authors":"Y. Mekonnen, J. Schutt-Ainé","doi":"10.1109/ECTC.2008.4550132","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550132","url":null,"abstract":"The vector-fitting algorithm has been used as the main macromodeling tool for approximating frequency domain responses of complex interconnects and electrical packages (Gustavsen, 1999). In this paper, a new methodology is proposed to fit transfer functions of frequency response data obtained from numerical electromagnetic simulation or measured frequency-domain or time-domain response data. This new method, z-domain vector-fitting (ZDVF), is a formulation of vector- fitting method in the z domain; it has an advantage of faster convergence and better numerical stability compared to the s-domain vector-fitting method(VF). The fast convergence of the method reduces the overall macromodel generation time. The accuracy, numerical stability and convergence speed of VF and ZDVF are compared. Examples are provided to demonstrate the advantage of the ZDVF.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550196
J. de Vreugd, K. Jansen, A. Xiao, L. Ernst, C. Bohm, A. Kessler, H. Preu, M. Stecher
Warpage is a critical issue for a QFN panel molding process. Much work is done in the past to predict the warpage of a package during cooling down from molding temperature. However, until now, warpage could not always be predicted well, even if the viscoelastic behavior of the molding compound is taken into account. It was for example observed that the cooling velocity affected the warpage after cooling down. Because of this reason, the mechanical behavior of the molding compound was investigated in more detail. In this research, the mechanical properties of the molding compound are determined. It turned out that the properties are highly dependent on time and temperature. A complete viscoelastic model of the model compound is achieved by combining DMA and dilatometric test results. The model is implemented in the finite element software ABAQUS. In this study, our advanced model is compared with elastic calculations which are normally done. A validation experiment is performed in which simulation results are compared with experimental warpage data of a double layered beam, consisting out of a layer of molding compound and a layer of silicon. This beam is cooled down from a temperature above Tg to room temperature with different cooling rates. In the meantime warpage is measured and compared to simulation results. Finally, the advanced material model is used for calculations on a QFN-panel.
{"title":"Advanced viscoelastic material model for predicting warpage of a QFN panel","authors":"J. de Vreugd, K. Jansen, A. Xiao, L. Ernst, C. Bohm, A. Kessler, H. Preu, M. Stecher","doi":"10.1109/ECTC.2008.4550196","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550196","url":null,"abstract":"Warpage is a critical issue for a QFN panel molding process. Much work is done in the past to predict the warpage of a package during cooling down from molding temperature. However, until now, warpage could not always be predicted well, even if the viscoelastic behavior of the molding compound is taken into account. It was for example observed that the cooling velocity affected the warpage after cooling down. Because of this reason, the mechanical behavior of the molding compound was investigated in more detail. In this research, the mechanical properties of the molding compound are determined. It turned out that the properties are highly dependent on time and temperature. A complete viscoelastic model of the model compound is achieved by combining DMA and dilatometric test results. The model is implemented in the finite element software ABAQUS. In this study, our advanced model is compared with elastic calculations which are normally done. A validation experiment is performed in which simulation results are compared with experimental warpage data of a double layered beam, consisting out of a layer of molding compound and a layer of silicon. This beam is cooled down from a temperature above Tg to room temperature with different cooling rates. In the meantime warpage is measured and compared to simulation results. Finally, the advanced material model is used for calculations on a QFN-panel.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132722037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550090
K. Maekawa, M. Mita, K. Yamasaki, T. Niizeki, Y. Matsuba, N. Terada, H. Saito
In order to establish technology of packaging electronic modules, we investigated conditions for laser sintering of Ag nanoparticles, and evaluated characteristics of the sintered film. First, we plotted minute patterns on a copper substrate by ink-jet printing, and then employed an NdYAG laser to metalize the nanopaste in a short time. The Ag nanoparticles (5 nm in average diameter) dispersed in organic solvents were solidified to form coarse agglomerates of about 0.05-0.5 mum with a pulsed laser, or about 0.05 mum by CW mode. We carried out a bend-peel test to find that no separation occurred at the interface between the sintered Ag film and the substrate. Adhesive strength of the laser-sintered pattern on the Cu substrate is higher or equal to than that obtained by furnace sintering. An SIM observation of FIBed cross-sections revealed that the laser-sintered film is as thin as less than 0.5 mum, and has a porous structure. As for wiring a polyimide substrate, the use of water-repellant is indispensable for ink-jet printing. Three-step laser sintering enables us to make Ag wires on the polyimide film at a low laser power, which leads to less thermal damage to the substrate.
{"title":"Packaging of electronic modules through completely dry process","authors":"K. Maekawa, M. Mita, K. Yamasaki, T. Niizeki, Y. Matsuba, N. Terada, H. Saito","doi":"10.1109/ECTC.2008.4550090","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550090","url":null,"abstract":"In order to establish technology of packaging electronic modules, we investigated conditions for laser sintering of Ag nanoparticles, and evaluated characteristics of the sintered film. First, we plotted minute patterns on a copper substrate by ink-jet printing, and then employed an NdYAG laser to metalize the nanopaste in a short time. The Ag nanoparticles (5 nm in average diameter) dispersed in organic solvents were solidified to form coarse agglomerates of about 0.05-0.5 mum with a pulsed laser, or about 0.05 mum by CW mode. We carried out a bend-peel test to find that no separation occurred at the interface between the sintered Ag film and the substrate. Adhesive strength of the laser-sintered pattern on the Cu substrate is higher or equal to than that obtained by furnace sintering. An SIM observation of FIBed cross-sections revealed that the laser-sintered film is as thin as less than 0.5 mum, and has a porous structure. As for wiring a polyimide substrate, the use of water-repellant is indispensable for ink-jet printing. Three-step laser sintering enables us to make Ag wires on the polyimide film at a low laser power, which leads to less thermal damage to the substrate.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550031
R. Beica, C. Sharbono, T. Ritzdorf
Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.
{"title":"Through silicon via copper electrodeposition for 3D integration","authors":"R. Beica, C. Sharbono, T. Ritzdorf","doi":"10.1109/ECTC.2008.4550031","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550031","url":null,"abstract":"Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133158540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550258
J. Szwarc, R. Golombick, Y. Hernik
The reliable functioning of electronic devices which incorporate high precision resistors requires maintaining the specified precision over the full life of the device. As the precision and stability of foil resistors is expressed in parts per million, a precise prediction method of resistor's behavior under different loads and time periods is required. Based on test data gathered over 4 decades of production and testing, an equation based on Arrhenius Rate Law is derived for calculation of the standard deviation of the Gaussian distribution of resistance drifts. The Mean value of the drifts' distribution is evaluated and allows the calculation of the maximum drift for any requested confidence level.
{"title":"Prediction of drift in foil resistors","authors":"J. Szwarc, R. Golombick, Y. Hernik","doi":"10.1109/ECTC.2008.4550258","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550258","url":null,"abstract":"The reliable functioning of electronic devices which incorporate high precision resistors requires maintaining the specified precision over the full life of the device. As the precision and stability of foil resistors is expressed in parts per million, a precise prediction method of resistor's behavior under different loads and time periods is required. Based on test data gathered over 4 decades of production and testing, an equation based on Arrhenius Rate Law is derived for calculation of the standard deviation of the Gaussian distribution of resistance drifts. The Mean value of the drifts' distribution is evaluated and allows the calculation of the maximum drift for any requested confidence level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134534540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550094
Li Li, M. Nagar, J. Xue
Power and power density increase in microelectronics is a major challenge for packaging high performance ASIC and microprocessor devices. The thermal interface material (TIM) used between the chip and the heat spreader of the Flip Chip Plastic Ball Grid Array (FC-PBGA) package plays a very important role in the package thermal performance. Not only does it affect package thermal performance, it can also affect assembly yield and package reliability during manufacturing and normal operation. In this study attention has been focused on improving thermal performance, manufacturing yield and reliability of the flip-chip PBGA single chip packages and the System in Package (SiP) modules. Computational Fluid Dynamics (CFD) software was used to investigate the effect of TIM on FC-PBGA thermal performance. The effect of thermal interface material was then studied for controlling the interaction between the heat spreader and the FC-PBGA SiP module to reduce module warpage and to improve module assembly yield. Qualification of TIM for FC-PBGA at both the component level and the system level was discussed. Component level testing data showed that the thermal characteristics and mechanical integrity of the TIM selected can be evaluated by using the same stress conditions used in package reliability qualification. Finally, system level non- operational humidity test results showed that good mechanical reliability at the thermal interface of the FC-PBGA can be achieved by optimizing the heat spreader attaching process.
{"title":"Effect of thermal interface materials on manufacturing and reliability of Flip Chip PBGA and SiP packages","authors":"Li Li, M. Nagar, J. Xue","doi":"10.1109/ECTC.2008.4550094","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550094","url":null,"abstract":"Power and power density increase in microelectronics is a major challenge for packaging high performance ASIC and microprocessor devices. The thermal interface material (TIM) used between the chip and the heat spreader of the Flip Chip Plastic Ball Grid Array (FC-PBGA) package plays a very important role in the package thermal performance. Not only does it affect package thermal performance, it can also affect assembly yield and package reliability during manufacturing and normal operation. In this study attention has been focused on improving thermal performance, manufacturing yield and reliability of the flip-chip PBGA single chip packages and the System in Package (SiP) modules. Computational Fluid Dynamics (CFD) software was used to investigate the effect of TIM on FC-PBGA thermal performance. The effect of thermal interface material was then studied for controlling the interaction between the heat spreader and the FC-PBGA SiP module to reduce module warpage and to improve module assembly yield. Qualification of TIM for FC-PBGA at both the component level and the system level was discussed. Component level testing data showed that the thermal characteristics and mechanical integrity of the TIM selected can be evaluated by using the same stress conditions used in package reliability qualification. Finally, system level non- operational humidity test results showed that good mechanical reliability at the thermal interface of the FC-PBGA can be achieved by optimizing the heat spreader attaching process.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124226781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550260
Yuquan Li, R.W. Johnson, P. Thompson, T. Hooghan, J. Libres
Copper heat spreaders are often used in flip chip in package construction. While providing high thermal conductivity, Cu has a significantly higher coefficient of thermal expansion than Si. In this work, two heat spreader attachment materials, indium for high power and polymeric adhesive for medium power applications, have been investigated. For In solder based attach, the Cu heat spreader was metallized with Ni/Au. Two thin film metallizations, Ti/Ni/Au and Ti/Au, have been studied for the Si backside. A nearly void free heat spreader attach has been achieved with vacuum soldering. For Ti/Ni/Au backside metallized Si die, there was no significant shear strength change after 1000 hours aging at 120degC and there was no significant shear or pull strength variation after five lead free re flow cycles. The shear and pull failure mode was within the indium layer. For Ti/Au die backside metallization, the initial die pull strength and failure mode were a function of Au thickness. With 3000 A of Au, there is no significant variation for shear and pull strength after 600 hours aging at 120degC or after five lead free solder reflow cycles. Failure was in the indium layer. For both types of die metallization, 24 mm times 24 mm Cu heat spreaders assembled on 22 mm times 22 mm Si die, exhibited no delamination after two lead free solder reflow cycles followed by 500 air to air thermal shock cycles (-40degC to 85degC). At 1000 cycles, slight delamination was found at the edges of the assembly for both die metallurgies. For adhesive based flat heat spreader attachment, a thermally conductive adhesive was used as the thermal interface and a non-thermally conductive adhesive was applied at the substrate corners to provide mechanical reinforcement of the heat spreader. After pre-conditioning then aging at 100degC for 500 hours followed by 500 air-to-air thermal shock cycles (0degC to 100degC), no delamination was observed and there was no significant degradation in pull strength.
{"title":"Reliability of flip chip packages with high thermal conductivity heat spreader attach","authors":"Yuquan Li, R.W. Johnson, P. Thompson, T. Hooghan, J. Libres","doi":"10.1109/ECTC.2008.4550260","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550260","url":null,"abstract":"Copper heat spreaders are often used in flip chip in package construction. While providing high thermal conductivity, Cu has a significantly higher coefficient of thermal expansion than Si. In this work, two heat spreader attachment materials, indium for high power and polymeric adhesive for medium power applications, have been investigated. For In solder based attach, the Cu heat spreader was metallized with Ni/Au. Two thin film metallizations, Ti/Ni/Au and Ti/Au, have been studied for the Si backside. A nearly void free heat spreader attach has been achieved with vacuum soldering. For Ti/Ni/Au backside metallized Si die, there was no significant shear strength change after 1000 hours aging at 120degC and there was no significant shear or pull strength variation after five lead free re flow cycles. The shear and pull failure mode was within the indium layer. For Ti/Au die backside metallization, the initial die pull strength and failure mode were a function of Au thickness. With 3000 A of Au, there is no significant variation for shear and pull strength after 600 hours aging at 120degC or after five lead free solder reflow cycles. Failure was in the indium layer. For both types of die metallization, 24 mm times 24 mm Cu heat spreaders assembled on 22 mm times 22 mm Si die, exhibited no delamination after two lead free solder reflow cycles followed by 500 air to air thermal shock cycles (-40degC to 85degC). At 1000 cycles, slight delamination was found at the edges of the assembly for both die metallurgies. For adhesive based flat heat spreader attachment, a thermally conductive adhesive was used as the thermal interface and a non-thermally conductive adhesive was applied at the substrate corners to provide mechanical reinforcement of the heat spreader. After pre-conditioning then aging at 100degC for 500 hours followed by 500 air-to-air thermal shock cycles (0degC to 100degC), no delamination was observed and there was no significant degradation in pull strength.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550211
Y. Liu, S. Irving, T. Luk, M. Rioux, Qiuxiao Qian
In this paper, the impact from both mechanical and thermal effects, with different parameters on BPSG of a power package is studied. The impact parameters include wedge wire bonding force, clamping force from the spring clip, wave soldering process and power dissipation from the die. An advanced 3D FEA model framework with a global model and local sub-model is developed. Major modeling work includes two areas: One is to evaluate the impact of the wire bonding force during the wedge bonding assembly process and the clamping force from the spring clip. Another area is to study the thermal stress due to thermal expansion mismatch which includes the wave soldering process and power dissipation. Both the global and sub-model simulation results have shown that the stress distribution in BPSG due to the wire bonding process, spring clip clamping force, wave soldering and power dissipation. The modeling has disclosed that the impact of thermal stress is greater than that of wedge wire bonding process and spring clip clamping force.
{"title":"Impact of wedge wire bonding and thermal mechanical stress on reliability of BPSG/poly layer of a silicon die","authors":"Y. Liu, S. Irving, T. Luk, M. Rioux, Qiuxiao Qian","doi":"10.1109/ECTC.2008.4550211","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550211","url":null,"abstract":"In this paper, the impact from both mechanical and thermal effects, with different parameters on BPSG of a power package is studied. The impact parameters include wedge wire bonding force, clamping force from the spring clip, wave soldering process and power dissipation from the die. An advanced 3D FEA model framework with a global model and local sub-model is developed. Major modeling work includes two areas: One is to evaluate the impact of the wire bonding force during the wedge bonding assembly process and the clamping force from the spring clip. Another area is to study the thermal stress due to thermal expansion mismatch which includes the wave soldering process and power dissipation. Both the global and sub-model simulation results have shown that the stress distribution in BPSG due to the wire bonding process, spring clip clamping force, wave soldering and power dissipation. The modeling has disclosed that the impact of thermal stress is greater than that of wedge wire bonding process and spring clip clamping force.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124488706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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