Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550147
R. Hahn, S. Wagner, S. Krumbholz, H. Reichl
A PEM micro fuel cell system is described which is based on self-breathing PEM micro fuel cells in the power range between 1 mW and 1 W. Micro patterned substrates were used as micro flow fields and replacement of gas diffusion layers (GDL). An analytical model was developed to estimate the losses in such structures and optimize channel design and current collector metallization. A detailed comparison was made between two different designs: pin structures and channel structures. A variety of micro fuel cells with variations of design parameters were tested to verify the model. As a result, micro fuel cell fabrication can be optimized in terms of cell performance and production costs. A maximum power density of 160 mW/cm2 has been achieved with the GDL-less design and a current collector pitch of 400 mum with commercial membrane electrode assemblies.
{"title":"Development of micro fuel cells with organic substrates and electronics manufacturing technologies","authors":"R. Hahn, S. Wagner, S. Krumbholz, H. Reichl","doi":"10.1109/ECTC.2008.4550147","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550147","url":null,"abstract":"A PEM micro fuel cell system is described which is based on self-breathing PEM micro fuel cells in the power range between 1 mW and 1 W. Micro patterned substrates were used as micro flow fields and replacement of gas diffusion layers (GDL). An analytical model was developed to estimate the losses in such structures and optimize channel design and current collector metallization. A detailed comparison was made between two different designs: pin structures and channel structures. A variety of micro fuel cells with variations of design parameters were tested to verify the model. As a result, micro fuel cell fabrication can be optimized in terms of cell performance and production costs. A maximum power density of 160 mW/cm2 has been achieved with the GDL-less design and a current collector pitch of 400 mum with commercial membrane electrode assemblies.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"75 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550229
E. Mintarno, S. Ji
First, this paper discusses a robust and efficient de- embedding technique that can be used for TDR-PNA- simulation correlation in time or frequency domain. Employing the de-embedding technique, TDR-PNA was shown to correlate very well with 2 mV resolution in time- domain, when TDR repeatability is 2 mV. Next, a systematic analysis of memory channel TDR-simulation correlation was detailed. Time domain correlation served as an efficient and straightforward way of capturing impedance discontinuities and crosstalk level. Finally, some design, modeling, and measurement guidelines for platform memory interconnect development were recommended.
{"title":"Time and frequency domain memory channel characterization and correlation methodology","authors":"E. Mintarno, S. Ji","doi":"10.1109/ECTC.2008.4550229","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550229","url":null,"abstract":"First, this paper discusses a robust and efficient de- embedding technique that can be used for TDR-PNA- simulation correlation in time or frequency domain. Employing the de-embedding technique, TDR-PNA was shown to correlate very well with 2 mV resolution in time- domain, when TDR repeatability is 2 mV. Next, a systematic analysis of memory channel TDR-simulation correlation was detailed. Time domain correlation served as an efficient and straightforward way of capturing impedance discontinuities and crosstalk level. Finally, some design, modeling, and measurement guidelines for platform memory interconnect development were recommended.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550132
Y. Mekonnen, J. Schutt-Ainé
The vector-fitting algorithm has been used as the main macromodeling tool for approximating frequency domain responses of complex interconnects and electrical packages (Gustavsen, 1999). In this paper, a new methodology is proposed to fit transfer functions of frequency response data obtained from numerical electromagnetic simulation or measured frequency-domain or time-domain response data. This new method, z-domain vector-fitting (ZDVF), is a formulation of vector- fitting method in the z domain; it has an advantage of faster convergence and better numerical stability compared to the s-domain vector-fitting method(VF). The fast convergence of the method reduces the overall macromodel generation time. The accuracy, numerical stability and convergence speed of VF and ZDVF are compared. Examples are provided to demonstrate the advantage of the ZDVF.
{"title":"Fast broadband macromodeling technique of sampled time/frequency data using z-domain vector-fitting method","authors":"Y. Mekonnen, J. Schutt-Ainé","doi":"10.1109/ECTC.2008.4550132","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550132","url":null,"abstract":"The vector-fitting algorithm has been used as the main macromodeling tool for approximating frequency domain responses of complex interconnects and electrical packages (Gustavsen, 1999). In this paper, a new methodology is proposed to fit transfer functions of frequency response data obtained from numerical electromagnetic simulation or measured frequency-domain or time-domain response data. This new method, z-domain vector-fitting (ZDVF), is a formulation of vector- fitting method in the z domain; it has an advantage of faster convergence and better numerical stability compared to the s-domain vector-fitting method(VF). The fast convergence of the method reduces the overall macromodel generation time. The accuracy, numerical stability and convergence speed of VF and ZDVF are compared. Examples are provided to demonstrate the advantage of the ZDVF.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550196
J. de Vreugd, K. Jansen, A. Xiao, L. Ernst, C. Bohm, A. Kessler, H. Preu, M. Stecher
Warpage is a critical issue for a QFN panel molding process. Much work is done in the past to predict the warpage of a package during cooling down from molding temperature. However, until now, warpage could not always be predicted well, even if the viscoelastic behavior of the molding compound is taken into account. It was for example observed that the cooling velocity affected the warpage after cooling down. Because of this reason, the mechanical behavior of the molding compound was investigated in more detail. In this research, the mechanical properties of the molding compound are determined. It turned out that the properties are highly dependent on time and temperature. A complete viscoelastic model of the model compound is achieved by combining DMA and dilatometric test results. The model is implemented in the finite element software ABAQUS. In this study, our advanced model is compared with elastic calculations which are normally done. A validation experiment is performed in which simulation results are compared with experimental warpage data of a double layered beam, consisting out of a layer of molding compound and a layer of silicon. This beam is cooled down from a temperature above Tg to room temperature with different cooling rates. In the meantime warpage is measured and compared to simulation results. Finally, the advanced material model is used for calculations on a QFN-panel.
{"title":"Advanced viscoelastic material model for predicting warpage of a QFN panel","authors":"J. de Vreugd, K. Jansen, A. Xiao, L. Ernst, C. Bohm, A. Kessler, H. Preu, M. Stecher","doi":"10.1109/ECTC.2008.4550196","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550196","url":null,"abstract":"Warpage is a critical issue for a QFN panel molding process. Much work is done in the past to predict the warpage of a package during cooling down from molding temperature. However, until now, warpage could not always be predicted well, even if the viscoelastic behavior of the molding compound is taken into account. It was for example observed that the cooling velocity affected the warpage after cooling down. Because of this reason, the mechanical behavior of the molding compound was investigated in more detail. In this research, the mechanical properties of the molding compound are determined. It turned out that the properties are highly dependent on time and temperature. A complete viscoelastic model of the model compound is achieved by combining DMA and dilatometric test results. The model is implemented in the finite element software ABAQUS. In this study, our advanced model is compared with elastic calculations which are normally done. A validation experiment is performed in which simulation results are compared with experimental warpage data of a double layered beam, consisting out of a layer of molding compound and a layer of silicon. This beam is cooled down from a temperature above Tg to room temperature with different cooling rates. In the meantime warpage is measured and compared to simulation results. Finally, the advanced material model is used for calculations on a QFN-panel.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132722037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550090
K. Maekawa, M. Mita, K. Yamasaki, T. Niizeki, Y. Matsuba, N. Terada, H. Saito
In order to establish technology of packaging electronic modules, we investigated conditions for laser sintering of Ag nanoparticles, and evaluated characteristics of the sintered film. First, we plotted minute patterns on a copper substrate by ink-jet printing, and then employed an NdYAG laser to metalize the nanopaste in a short time. The Ag nanoparticles (5 nm in average diameter) dispersed in organic solvents were solidified to form coarse agglomerates of about 0.05-0.5 mum with a pulsed laser, or about 0.05 mum by CW mode. We carried out a bend-peel test to find that no separation occurred at the interface between the sintered Ag film and the substrate. Adhesive strength of the laser-sintered pattern on the Cu substrate is higher or equal to than that obtained by furnace sintering. An SIM observation of FIBed cross-sections revealed that the laser-sintered film is as thin as less than 0.5 mum, and has a porous structure. As for wiring a polyimide substrate, the use of water-repellant is indispensable for ink-jet printing. Three-step laser sintering enables us to make Ag wires on the polyimide film at a low laser power, which leads to less thermal damage to the substrate.
{"title":"Packaging of electronic modules through completely dry process","authors":"K. Maekawa, M. Mita, K. Yamasaki, T. Niizeki, Y. Matsuba, N. Terada, H. Saito","doi":"10.1109/ECTC.2008.4550090","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550090","url":null,"abstract":"In order to establish technology of packaging electronic modules, we investigated conditions for laser sintering of Ag nanoparticles, and evaluated characteristics of the sintered film. First, we plotted minute patterns on a copper substrate by ink-jet printing, and then employed an NdYAG laser to metalize the nanopaste in a short time. The Ag nanoparticles (5 nm in average diameter) dispersed in organic solvents were solidified to form coarse agglomerates of about 0.05-0.5 mum with a pulsed laser, or about 0.05 mum by CW mode. We carried out a bend-peel test to find that no separation occurred at the interface between the sintered Ag film and the substrate. Adhesive strength of the laser-sintered pattern on the Cu substrate is higher or equal to than that obtained by furnace sintering. An SIM observation of FIBed cross-sections revealed that the laser-sintered film is as thin as less than 0.5 mum, and has a porous structure. As for wiring a polyimide substrate, the use of water-repellant is indispensable for ink-jet printing. Three-step laser sintering enables us to make Ag wires on the polyimide film at a low laser power, which leads to less thermal damage to the substrate.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550031
R. Beica, C. Sharbono, T. Ritzdorf
Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.
{"title":"Through silicon via copper electrodeposition for 3D integration","authors":"R. Beica, C. Sharbono, T. Ritzdorf","doi":"10.1109/ECTC.2008.4550031","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550031","url":null,"abstract":"Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133158540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550258
J. Szwarc, R. Golombick, Y. Hernik
The reliable functioning of electronic devices which incorporate high precision resistors requires maintaining the specified precision over the full life of the device. As the precision and stability of foil resistors is expressed in parts per million, a precise prediction method of resistor's behavior under different loads and time periods is required. Based on test data gathered over 4 decades of production and testing, an equation based on Arrhenius Rate Law is derived for calculation of the standard deviation of the Gaussian distribution of resistance drifts. The Mean value of the drifts' distribution is evaluated and allows the calculation of the maximum drift for any requested confidence level.
{"title":"Prediction of drift in foil resistors","authors":"J. Szwarc, R. Golombick, Y. Hernik","doi":"10.1109/ECTC.2008.4550258","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550258","url":null,"abstract":"The reliable functioning of electronic devices which incorporate high precision resistors requires maintaining the specified precision over the full life of the device. As the precision and stability of foil resistors is expressed in parts per million, a precise prediction method of resistor's behavior under different loads and time periods is required. Based on test data gathered over 4 decades of production and testing, an equation based on Arrhenius Rate Law is derived for calculation of the standard deviation of the Gaussian distribution of resistance drifts. The Mean value of the drifts' distribution is evaluated and allows the calculation of the maximum drift for any requested confidence level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134534540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550054
R. Das, S. Rosser, K. Papathomas, M. Poliks, J. Lauffer, V. Markovich
This paper discusses thin film technology based on resin coated copper capacitive (RC3) nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives, their integration in printed wiring boards (PWB), system in package (SiP) and chip package substrates and the reliability of the embedded capacitors. A variety of RC3 nanocomposite thin films ranging from 2 microns to 50 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. Nanocomposites resulted in high capacitance density (7-500 nF/inch2) at 1 MHz. The manufacturability of these films and their reliability has been tested using large area (13 inch times 18 inch or 19.5 inch times24 inch) test vehicles. Reliability of the RC3 nanocomposite was ascertained by IR-reflow, PCT (pressure cooker test) and solder shock. As a case study, an example of RC3 based multilayer embedded capacitor construction for a flip-chip plastic ball grid array package with a 300 mum core via pitch is given. This effort is an integrated approach centering on three interrelated fronts: (1) materials development and characterization; (2) fabrication, and (3) integration at the device level.
{"title":"Resin coated copper capacitive (RC3) nanocomposites for multilayer embedded capacitors","authors":"R. Das, S. Rosser, K. Papathomas, M. Poliks, J. Lauffer, V. Markovich","doi":"10.1109/ECTC.2008.4550054","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550054","url":null,"abstract":"This paper discusses thin film technology based on resin coated copper capacitive (RC3) nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives, their integration in printed wiring boards (PWB), system in package (SiP) and chip package substrates and the reliability of the embedded capacitors. A variety of RC3 nanocomposite thin films ranging from 2 microns to 50 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. Nanocomposites resulted in high capacitance density (7-500 nF/inch2) at 1 MHz. The manufacturability of these films and their reliability has been tested using large area (13 inch times 18 inch or 19.5 inch times24 inch) test vehicles. Reliability of the RC3 nanocomposite was ascertained by IR-reflow, PCT (pressure cooker test) and solder shock. As a case study, an example of RC3 based multilayer embedded capacitor construction for a flip-chip plastic ball grid array package with a 300 mum core via pitch is given. This effort is an integrated approach centering on three interrelated fronts: (1) materials development and characterization; (2) fabrication, and (3) integration at the device level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550189
O. van der Sluis, P. Timmermans, R. van Silfhout, W. V. van Driel, G.Q. Zhang
Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. Numerical modeling can provide more fundamental understanding of these failure phenomena. As a results, predicting, and ultimately, preventing these phenomena will result in an increased reliability of current and future electronic products. In this paper, delamination phenomena occurring in Cu/low-k back-end structures, buckling-driven delamination in flexible electronics and peeling tests on stretchable electronics will be modeled and validated by experimental results. For the Cu/low-k back-end structures, failure sensitivity analysis is performed by the recently developed area release energy (ARE) method while transient delamination processes are described by cohesive zone elements in the critical regions. For the latter, a dedicated solver is applied that is able to deal with brittle interfaces. For the flexible and stretchable electronics applications, cohesive zones are used to characterize the interface properties by combining numerical results with experimental measurements.
{"title":"Delamination modeling of three-dimensional microelectronic systems","authors":"O. van der Sluis, P. Timmermans, R. van Silfhout, W. V. van Driel, G.Q. Zhang","doi":"10.1109/ECTC.2008.4550189","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550189","url":null,"abstract":"Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. Numerical modeling can provide more fundamental understanding of these failure phenomena. As a results, predicting, and ultimately, preventing these phenomena will result in an increased reliability of current and future electronic products. In this paper, delamination phenomena occurring in Cu/low-k back-end structures, buckling-driven delamination in flexible electronics and peeling tests on stretchable electronics will be modeled and validated by experimental results. For the Cu/low-k back-end structures, failure sensitivity analysis is performed by the recently developed area release energy (ARE) method while transient delamination processes are described by cohesive zone elements in the critical regions. For the latter, a dedicated solver is applied that is able to deal with brittle interfaces. For the flexible and stretchable electronics applications, cohesive zones are used to characterize the interface properties by combining numerical results with experimental measurements.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115678052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550215
S. Anson, J.G. Slezak, K. Srihari
Enhanced or equivalent solder paste wetting on organic solderability preservative (OSP) circuit boards in 63Sn/37Pb and 96.5Sn/3.0Ag/0.5Cu at lower peak temperature and time above liquidus (TAL) has been published previously. These results are contrary to common belief and practice in microelectronics soldering. Microelectronics and general metal wetting literature will be reviewed to generate hypotheses about the cause of the enhanced or equivalent solder wetting. The former wetted area experiments were conducted using design of experiments (DOE) techniques and now analysis outside of the DOE will be conducted to test the new hypotheses and advance the knowledge of solder wetting. Industry relevant manufacturing equipment, materials and processes were used. After detailed analysis, the enhanced or equivalent wetting appears to be unique to the proprietary flux chemistry.
{"title":"Investigation of enhanced solder wetting in 63Sn/37Pb and Sn-Ag-Cu lead free alloy","authors":"S. Anson, J.G. Slezak, K. Srihari","doi":"10.1109/ECTC.2008.4550215","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550215","url":null,"abstract":"Enhanced or equivalent solder paste wetting on organic solderability preservative (OSP) circuit boards in 63Sn/37Pb and 96.5Sn/3.0Ag/0.5Cu at lower peak temperature and time above liquidus (TAL) has been published previously. These results are contrary to common belief and practice in microelectronics soldering. Microelectronics and general metal wetting literature will be reviewed to generate hypotheses about the cause of the enhanced or equivalent solder wetting. The former wetted area experiments were conducted using design of experiments (DOE) techniques and now analysis outside of the DOE will be conducted to test the new hypotheses and advance the knowledge of solder wetting. Industry relevant manufacturing equipment, materials and processes were used. After detailed analysis, the enhanced or equivalent wetting appears to be unique to the proprietary flux chemistry.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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