Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550194
S. Koh, R. Tummala, A. Saxena, P. Selvam
The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.
{"title":"A numerical analysis of crack growth and morphology evolution in chip-to-packages nano-interconnections","authors":"S. Koh, R. Tummala, A. Saxena, P. Selvam","doi":"10.1109/ECTC.2008.4550194","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550194","url":null,"abstract":"The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550252
P. Nummila, M. Johansson, S. Puro
WLCSP, real wafer size package, usage has grown heavily during last years and volume is expected still to grow a lot. Main drivers for WLCSP usage are size and thickness reduction in portable devices and in some applications also price reduction by simplifying packaging structure. The main factor affecting these is reduction of component IO pitch. Growing usage volume has also increased the amount of WLCSP manufacturers, giving large variation of different package structures to the markets. As a consequence field of reliability is large, since different structures are behaving very differently especially under mechanical shock, which is considered to be most critical behavior of WLCSP packages in portable devices. However thermo-mechanical reliability should not be compromised either. Today there are many studies showing comparison of reliability test results between some factors, like dimensions. However from WLCSP end-user point of view whole system is more complex; there are several factors effecting to the overall mechanical and thermo-mechanical robustness of WLCSP packages, especially metallurgical factors play very remarkable role, including different underbump material and solder ball combinations. From WLCSP user point of view it is important to understand the variety of structures in the field and the complexity of factors effecting reliability in the area. Aim of the study is to increase knowledge of complexity of this area and factors effecting reliability of various WLCSP structures. As an introduction, data from last years WLCSP volumes in Nokia portable devices will be shown, together with an estimate of further usage volume. Overview of most common WLCSP structures will be presented, to give an overview of variety of different structures in the field. Reliability test results of mechanical shock will be presented and different package types and bump pitches will be compared. Also "weak links" between different package types will be compared, in terms of failure analysis results. As a conclusion there will be discussion of pros and cons of different package types, there is also not only one correct type to be used but several possibly good ones, defined also by electrical design.
{"title":"Mechanical shock robustness of different WLCSP types","authors":"P. Nummila, M. Johansson, S. Puro","doi":"10.1109/ECTC.2008.4550252","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550252","url":null,"abstract":"WLCSP, real wafer size package, usage has grown heavily during last years and volume is expected still to grow a lot. Main drivers for WLCSP usage are size and thickness reduction in portable devices and in some applications also price reduction by simplifying packaging structure. The main factor affecting these is reduction of component IO pitch. Growing usage volume has also increased the amount of WLCSP manufacturers, giving large variation of different package structures to the markets. As a consequence field of reliability is large, since different structures are behaving very differently especially under mechanical shock, which is considered to be most critical behavior of WLCSP packages in portable devices. However thermo-mechanical reliability should not be compromised either. Today there are many studies showing comparison of reliability test results between some factors, like dimensions. However from WLCSP end-user point of view whole system is more complex; there are several factors effecting to the overall mechanical and thermo-mechanical robustness of WLCSP packages, especially metallurgical factors play very remarkable role, including different underbump material and solder ball combinations. From WLCSP user point of view it is important to understand the variety of structures in the field and the complexity of factors effecting reliability in the area. Aim of the study is to increase knowledge of complexity of this area and factors effecting reliability of various WLCSP structures. As an introduction, data from last years WLCSP volumes in Nokia portable devices will be shown, together with an estimate of further usage volume. Overview of most common WLCSP structures will be presented, to give an overview of variety of different structures in the field. Reliability test results of mechanical shock will be presented and different package types and bump pitches will be compared. Also \"weak links\" between different package types will be compared, in terms of failure analysis results. As a conclusion there will be discussion of pros and cons of different package types, there is also not only one correct type to be used but several possibly good ones, defined also by electrical design.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550263
Jang-Hee Lee, Gi-Tae Lim, Young-Bae Park, Seungtaek Yang, M. Suh, Q. Chung, Kwang-yoo Byun
To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.
{"title":"Size effect on electromigration reliability of pb-free flip chip solder bump","authors":"Jang-Hee Lee, Gi-Tae Lim, Young-Bae Park, Seungtaek Yang, M. Suh, Q. Chung, Kwang-yoo Byun","doi":"10.1109/ECTC.2008.4550263","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550263","url":null,"abstract":"To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131720396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550146
Jin Liu, J. Goud, P. Raj, M. Iyer, Z. Wang, R. Tummala
A nanoscale semiconducting ZnO based biosensor with integrated microfluidics is designed, fabricated and tested to demonstrate the detection of streptavidin, a commonly used protein. Amperometric (I-t) measurement is utilized to detect the change of conductivity over time. By comparing with the control experiment, the specific binding event between biotin and streptavidin is detected. The data indicates a conductivity change by more than 20% after the protein hybridization. The second part of the papers presents a ZnO thin film based biosensor which is integated with a microfluidic system. Same experiment protocols are carried and similar change in I-t characteristics is observed. This is the first demonstration of real time biosensing with ZnO nanowires and thin films that are integrated with microfluidic systems. This can be further extended to fabricate bio-sensors which can potentially detect any protein in real time. Amperometric sensing results in a label-free detection system as it detects the protein hybridization events electrically. when integrated on the system-on-package (SOP) platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.
{"title":"Real-time protein detection using ZnO nanowire/thin film bio-sensor integrated with microfluidic system","authors":"Jin Liu, J. Goud, P. Raj, M. Iyer, Z. Wang, R. Tummala","doi":"10.1109/ECTC.2008.4550146","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550146","url":null,"abstract":"A nanoscale semiconducting ZnO based biosensor with integrated microfluidics is designed, fabricated and tested to demonstrate the detection of streptavidin, a commonly used protein. Amperometric (I-t) measurement is utilized to detect the change of conductivity over time. By comparing with the control experiment, the specific binding event between biotin and streptavidin is detected. The data indicates a conductivity change by more than 20% after the protein hybridization. The second part of the papers presents a ZnO thin film based biosensor which is integated with a microfluidic system. Same experiment protocols are carried and similar change in I-t characteristics is observed. This is the first demonstration of real time biosensing with ZnO nanowires and thin films that are integrated with microfluidic systems. This can be further extended to fabricate bio-sensors which can potentially detect any protein in real time. Amperometric sensing results in a label-free detection system as it detects the protein hybridization events electrically. when integrated on the system-on-package (SOP) platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133762540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550191
U. Ozkan, H. F. Nied
Interface delamination phenomenon has been a great concern for semiconductor package reliability. In order to better understand the package failure mechanisms, crack initiation and propagation behavior of interface flaws have to be investigated in detail. In this paper, three dimensional interface crack propagation is examined using the enriched finite element method. A fatigue crack growth simulation technique, which has been widely studied in the literature to predict steady state crack growth behavior after crack initiation in homogeneous materials, is extended to three dimensional interface cracks. The method described uses a modified version of the classical fatigue crack growth rate "law" developed by Paris and Erdogan to simulate stable crack growth under cyclic loading conditions, with the crack constrained to the plane of the interface. The crack driving force, which is chosen as cyclic strain energy release rate, is calculated using the enriched finite element method. As a practical example in semiconductor package reliability analysis, the method is used to simulate the propagation of a three-dimensional interface crack on a silicon/epoxy interface under various loading conditions. Plots of advancement of the crack front and the changes in total strain energy release rates as the crack shape evolves during propagation are also given. Lastly, crack propagation simulation is demonstrated for a generic package model using a submodeling technique.
{"title":"Finite element based three dimensional crack propagation simulation on interfaces in electronic packages","authors":"U. Ozkan, H. F. Nied","doi":"10.1109/ECTC.2008.4550191","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550191","url":null,"abstract":"Interface delamination phenomenon has been a great concern for semiconductor package reliability. In order to better understand the package failure mechanisms, crack initiation and propagation behavior of interface flaws have to be investigated in detail. In this paper, three dimensional interface crack propagation is examined using the enriched finite element method. A fatigue crack growth simulation technique, which has been widely studied in the literature to predict steady state crack growth behavior after crack initiation in homogeneous materials, is extended to three dimensional interface cracks. The method described uses a modified version of the classical fatigue crack growth rate \"law\" developed by Paris and Erdogan to simulate stable crack growth under cyclic loading conditions, with the crack constrained to the plane of the interface. The crack driving force, which is chosen as cyclic strain energy release rate, is calculated using the enriched finite element method. As a practical example in semiconductor package reliability analysis, the method is used to simulate the propagation of a three-dimensional interface crack on a silicon/epoxy interface under various loading conditions. Plots of advancement of the crack front and the changes in total strain energy release rates as the crack shape evolves during propagation are also given. Lastly, crack propagation simulation is demonstrated for a generic package model using a submodeling technique.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"155 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133039639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550200
Zhang Kai, M. Yuen, D. Xiao, Y. Fu, P. Chan
Vertically aligned carbon nanotube (VACNT) arrays were synthesized directly on aluminum alloy substrates by thermal chemical vapor deposition (CVD). Iron nitrate (Fe(NO3)3ldr9H2O) was used as the catalyst. Parameters influencing CNT synthesis were studied and optimized. Several surface treatment methods were proposed to improve the quality of CNTs synthesized on aluminum alloy substrates. The grown CNT arrays were used as thermal interface material (TIM) while the aluminum alloy substrate used as the heat sink in high brightness LED packages. The measured thermal resistance of the grown CNT-TIM was 38 mm2-K/W. The output light power testing demonstrated CNT-TIM is an attractive thermal management solution for HB- LED packages.
{"title":"Directly synthesizing CNT-TIM on aluminum alloy heat sink for HB-LED thermal management","authors":"Zhang Kai, M. Yuen, D. Xiao, Y. Fu, P. Chan","doi":"10.1109/ECTC.2008.4550200","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550200","url":null,"abstract":"Vertically aligned carbon nanotube (VACNT) arrays were synthesized directly on aluminum alloy substrates by thermal chemical vapor deposition (CVD). Iron nitrate (Fe(NO3)3ldr9H2O) was used as the catalyst. Parameters influencing CNT synthesis were studied and optimized. Several surface treatment methods were proposed to improve the quality of CNTs synthesized on aluminum alloy substrates. The grown CNT arrays were used as thermal interface material (TIM) while the aluminum alloy substrate used as the heat sink in high brightness LED packages. The measured thermal resistance of the grown CNT-TIM was 38 mm2-K/W. The output light power testing demonstrated CNT-TIM is an attractive thermal management solution for HB- LED packages.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132885754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550021
M. Degerstrom, B. Buhrow, B. McCoy, P. Zabinski, B. Gilbert, E. Daniel
Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.
{"title":"System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications","authors":"M. Degerstrom, B. Buhrow, B. McCoy, P. Zabinski, B. Gilbert, E. Daniel","doi":"10.1109/ECTC.2008.4550021","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550021","url":null,"abstract":"Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550215
S. Anson, J.G. Slezak, K. Srihari
Enhanced or equivalent solder paste wetting on organic solderability preservative (OSP) circuit boards in 63Sn/37Pb and 96.5Sn/3.0Ag/0.5Cu at lower peak temperature and time above liquidus (TAL) has been published previously. These results are contrary to common belief and practice in microelectronics soldering. Microelectronics and general metal wetting literature will be reviewed to generate hypotheses about the cause of the enhanced or equivalent solder wetting. The former wetted area experiments were conducted using design of experiments (DOE) techniques and now analysis outside of the DOE will be conducted to test the new hypotheses and advance the knowledge of solder wetting. Industry relevant manufacturing equipment, materials and processes were used. After detailed analysis, the enhanced or equivalent wetting appears to be unique to the proprietary flux chemistry.
{"title":"Investigation of enhanced solder wetting in 63Sn/37Pb and Sn-Ag-Cu lead free alloy","authors":"S. Anson, J.G. Slezak, K. Srihari","doi":"10.1109/ECTC.2008.4550215","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550215","url":null,"abstract":"Enhanced or equivalent solder paste wetting on organic solderability preservative (OSP) circuit boards in 63Sn/37Pb and 96.5Sn/3.0Ag/0.5Cu at lower peak temperature and time above liquidus (TAL) has been published previously. These results are contrary to common belief and practice in microelectronics soldering. Microelectronics and general metal wetting literature will be reviewed to generate hypotheses about the cause of the enhanced or equivalent solder wetting. The former wetted area experiments were conducted using design of experiments (DOE) techniques and now analysis outside of the DOE will be conducted to test the new hypotheses and advance the knowledge of solder wetting. Industry relevant manufacturing equipment, materials and processes were used. After detailed analysis, the enhanced or equivalent wetting appears to be unique to the proprietary flux chemistry.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550054
R. Das, S. Rosser, K. Papathomas, M. Poliks, J. Lauffer, V. Markovich
This paper discusses thin film technology based on resin coated copper capacitive (RC3) nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives, their integration in printed wiring boards (PWB), system in package (SiP) and chip package substrates and the reliability of the embedded capacitors. A variety of RC3 nanocomposite thin films ranging from 2 microns to 50 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. Nanocomposites resulted in high capacitance density (7-500 nF/inch2) at 1 MHz. The manufacturability of these films and their reliability has been tested using large area (13 inch times 18 inch or 19.5 inch times24 inch) test vehicles. Reliability of the RC3 nanocomposite was ascertained by IR-reflow, PCT (pressure cooker test) and solder shock. As a case study, an example of RC3 based multilayer embedded capacitor construction for a flip-chip plastic ball grid array package with a 300 mum core via pitch is given. This effort is an integrated approach centering on three interrelated fronts: (1) materials development and characterization; (2) fabrication, and (3) integration at the device level.
{"title":"Resin coated copper capacitive (RC3) nanocomposites for multilayer embedded capacitors","authors":"R. Das, S. Rosser, K. Papathomas, M. Poliks, J. Lauffer, V. Markovich","doi":"10.1109/ECTC.2008.4550054","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550054","url":null,"abstract":"This paper discusses thin film technology based on resin coated copper capacitive (RC3) nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives, their integration in printed wiring boards (PWB), system in package (SiP) and chip package substrates and the reliability of the embedded capacitors. A variety of RC3 nanocomposite thin films ranging from 2 microns to 50 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. Nanocomposites resulted in high capacitance density (7-500 nF/inch2) at 1 MHz. The manufacturability of these films and their reliability has been tested using large area (13 inch times 18 inch or 19.5 inch times24 inch) test vehicles. Reliability of the RC3 nanocomposite was ascertained by IR-reflow, PCT (pressure cooker test) and solder shock. As a case study, an example of RC3 based multilayer embedded capacitor construction for a flip-chip plastic ball grid array package with a 300 mum core via pitch is given. This effort is an integrated approach centering on three interrelated fronts: (1) materials development and characterization; (2) fabrication, and (3) integration at the device level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550189
O. van der Sluis, P. Timmermans, R. van Silfhout, W. V. van Driel, G.Q. Zhang
Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. Numerical modeling can provide more fundamental understanding of these failure phenomena. As a results, predicting, and ultimately, preventing these phenomena will result in an increased reliability of current and future electronic products. In this paper, delamination phenomena occurring in Cu/low-k back-end structures, buckling-driven delamination in flexible electronics and peeling tests on stretchable electronics will be modeled and validated by experimental results. For the Cu/low-k back-end structures, failure sensitivity analysis is performed by the recently developed area release energy (ARE) method while transient delamination processes are described by cohesive zone elements in the critical regions. For the latter, a dedicated solver is applied that is able to deal with brittle interfaces. For the flexible and stretchable electronics applications, cohesive zones are used to characterize the interface properties by combining numerical results with experimental measurements.
{"title":"Delamination modeling of three-dimensional microelectronic systems","authors":"O. van der Sluis, P. Timmermans, R. van Silfhout, W. V. van Driel, G.Q. Zhang","doi":"10.1109/ECTC.2008.4550189","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550189","url":null,"abstract":"Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. Numerical modeling can provide more fundamental understanding of these failure phenomena. As a results, predicting, and ultimately, preventing these phenomena will result in an increased reliability of current and future electronic products. In this paper, delamination phenomena occurring in Cu/low-k back-end structures, buckling-driven delamination in flexible electronics and peeling tests on stretchable electronics will be modeled and validated by experimental results. For the Cu/low-k back-end structures, failure sensitivity analysis is performed by the recently developed area release energy (ARE) method while transient delamination processes are described by cohesive zone elements in the critical regions. For the latter, a dedicated solver is applied that is able to deal with brittle interfaces. For the flexible and stretchable electronics applications, cohesive zones are used to characterize the interface properties by combining numerical results with experimental measurements.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115678052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：