Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550193
S. Hwang, J. Lim, B. Rho
Our suggested VCSEL array optical subassembly (OSA) for 120 Gb/s-level parallel optical interconnect modules was composed of a 12 channel VCSEL array chip, a SiOB, two silicon spacers, and a molded microlens with accurate guide pin holes. For high speed operation above 10 Gb/s per a channel, we carefully designed transmission lines on the SiOB. The results of the transmission lines were measured as large bandwidth more than 26 GHz and low channel crosstalk less than -30 dB. And, to achieve high coupling efficiency, the planar-convex microlens was adopted. The average coupling efficiency coupled to 62.5 mum multi-mode fiber (MMF) ribbon was approximately 85%, the value of which means nothing but material loss itself. In this paper, the fabrication process of the VCSEL OSA is emphasized on low cost packaging. In particular, a suggested passive alignment technique is described in detail to align both the VCSEL and the microlens array. An accurate assembly in this work was carried out through vision alignment using 2-sight camera of a precise pick-and-place machine, Suss MicroTec TRIAD 05 flip-chip bonder. To evaluate the DC and AC characteristics of the completely fabricated VCSEL array OSA, we measured optical output powers (L-I-V curve) and 4.25 Gb/s, 6 Gb/s, 10.31 Gb/s eye-diagrams on condition of setting-up with MT ferrule terminated 12 channel 62.5 mum MMF and a G-S-G probe. We successfully demonstrated high speed and high efficient VCSEL array OSA with clear 10.31 Gb/s eye diagrams and low coupling loss.
{"title":"120 Gb/s-level VCSEL array optical subassembly using passive alignment technique","authors":"S. Hwang, J. Lim, B. Rho","doi":"10.1109/ECTC.2008.4550193","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550193","url":null,"abstract":"Our suggested VCSEL array optical subassembly (OSA) for 120 Gb/s-level parallel optical interconnect modules was composed of a 12 channel VCSEL array chip, a SiOB, two silicon spacers, and a molded microlens with accurate guide pin holes. For high speed operation above 10 Gb/s per a channel, we carefully designed transmission lines on the SiOB. The results of the transmission lines were measured as large bandwidth more than 26 GHz and low channel crosstalk less than -30 dB. And, to achieve high coupling efficiency, the planar-convex microlens was adopted. The average coupling efficiency coupled to 62.5 mum multi-mode fiber (MMF) ribbon was approximately 85%, the value of which means nothing but material loss itself. In this paper, the fabrication process of the VCSEL OSA is emphasized on low cost packaging. In particular, a suggested passive alignment technique is described in detail to align both the VCSEL and the microlens array. An accurate assembly in this work was carried out through vision alignment using 2-sight camera of a precise pick-and-place machine, Suss MicroTec TRIAD 05 flip-chip bonder. To evaluate the DC and AC characteristics of the completely fabricated VCSEL array OSA, we measured optical output powers (L-I-V curve) and 4.25 Gb/s, 6 Gb/s, 10.31 Gb/s eye-diagrams on condition of setting-up with MT ferrule terminated 12 channel 62.5 mum MMF and a G-S-G probe. We successfully demonstrated high speed and high efficient VCSEL array OSA with clear 10.31 Gb/s eye diagrams and low coupling loss.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114419639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549980
T. Shibata, A. Takahashi
We propose a flexible opto-electronic circuit board (FOECB) for in-device interconnection, which is combined with a flexible printed circuit (FPC) with flexible optical waveguides having 45deg mirrors for 90deg beam turning using adhesive film. The fabricated prototype shows total optical loss of 3.7 dB, and the prototype, which mounted a 4-ch vertical-cavity surface-emitting laser (VCSEL) array and a 4-ch photodiode (PD) array, successfully demonstrated optical signal transmission at a data rate of 10 Gbps/ch. These results show that the proposed prototype has considerable potential to realize practical FOECB for in-device interconnection.
{"title":"Flexible opto-electronic circuit board for in-device interconnection","authors":"T. Shibata, A. Takahashi","doi":"10.1109/ECTC.2008.4549980","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549980","url":null,"abstract":"We propose a flexible opto-electronic circuit board (FOECB) for in-device interconnection, which is combined with a flexible printed circuit (FPC) with flexible optical waveguides having 45deg mirrors for 90deg beam turning using adhesive film. The fabricated prototype shows total optical loss of 3.7 dB, and the prototype, which mounted a 4-ch vertical-cavity surface-emitting laser (VCSEL) array and a 4-ch photodiode (PD) array, successfully demonstrated optical signal transmission at a data rate of 10 Gbps/ch. These results show that the proposed prototype has considerable potential to realize practical FOECB for in-device interconnection.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550211
Y. Liu, S. Irving, T. Luk, M. Rioux, Qiuxiao Qian
In this paper, the impact from both mechanical and thermal effects, with different parameters on BPSG of a power package is studied. The impact parameters include wedge wire bonding force, clamping force from the spring clip, wave soldering process and power dissipation from the die. An advanced 3D FEA model framework with a global model and local sub-model is developed. Major modeling work includes two areas: One is to evaluate the impact of the wire bonding force during the wedge bonding assembly process and the clamping force from the spring clip. Another area is to study the thermal stress due to thermal expansion mismatch which includes the wave soldering process and power dissipation. Both the global and sub-model simulation results have shown that the stress distribution in BPSG due to the wire bonding process, spring clip clamping force, wave soldering and power dissipation. The modeling has disclosed that the impact of thermal stress is greater than that of wedge wire bonding process and spring clip clamping force.
{"title":"Impact of wedge wire bonding and thermal mechanical stress on reliability of BPSG/poly layer of a silicon die","authors":"Y. Liu, S. Irving, T. Luk, M. Rioux, Qiuxiao Qian","doi":"10.1109/ECTC.2008.4550211","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550211","url":null,"abstract":"In this paper, the impact from both mechanical and thermal effects, with different parameters on BPSG of a power package is studied. The impact parameters include wedge wire bonding force, clamping force from the spring clip, wave soldering process and power dissipation from the die. An advanced 3D FEA model framework with a global model and local sub-model is developed. Major modeling work includes two areas: One is to evaluate the impact of the wire bonding force during the wedge bonding assembly process and the clamping force from the spring clip. Another area is to study the thermal stress due to thermal expansion mismatch which includes the wave soldering process and power dissipation. Both the global and sub-model simulation results have shown that the stress distribution in BPSG due to the wire bonding process, spring clip clamping force, wave soldering and power dissipation. The modeling has disclosed that the impact of thermal stress is greater than that of wedge wire bonding process and spring clip clamping force.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124488706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550175
B. Dang, D. Shih, Stephen Buchwalter, Cornelia Tsang, Chirag S. Patel, J. Knickerbocker, P. Gruber, Sarah Knickerbocker, J. Garant, Krystyna Semkow, K. Ruhmer, E. Hughlett
Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.
{"title":"50μm pitch Pb-free micro-bumps by C4NP technology","authors":"B. Dang, D. Shih, Stephen Buchwalter, Cornelia Tsang, Chirag S. Patel, J. Knickerbocker, P. Gruber, Sarah Knickerbocker, J. Garant, Krystyna Semkow, K. Ruhmer, E. Hughlett","doi":"10.1109/ECTC.2008.4550175","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550175","url":null,"abstract":"Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"65 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123549415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550041
E. Liu, Xingchang Wei, Z. Oo, E. Li
A two-dimensional full-wave method is presented in this paper for efficient power integrity and EMI Analysis of highspeed electronic packages. The power/ground planes in electronic packages form a parallel-plate structure, which is solved by a 2D finite-different time domain (2D FDTD) method. Both the conductor loss and the substrate loss are modeled by the 2D method. Besides the parallel-plate structure, electronic packages also comprise of many transmission lines including microstrip- and stripline-type structures. Those two types of structures are also resolved by the 2D method. So a unified solver may be developed in the context of 2D method for the signal and power integrity analysis of electronic packages. The electromagnetic interference (EMI) issue of electronic packages is also touched in this paper, which is mainly focused on the radiation due to the edge effect of the parallel plate structure in a package. Numerical examples are given to demonstrate the method.
{"title":"An efficient method for power integrity and EMI Analysis of advanced packages","authors":"E. Liu, Xingchang Wei, Z. Oo, E. Li","doi":"10.1109/ECTC.2008.4550041","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550041","url":null,"abstract":"A two-dimensional full-wave method is presented in this paper for efficient power integrity and EMI Analysis of highspeed electronic packages. The power/ground planes in electronic packages form a parallel-plate structure, which is solved by a 2D finite-different time domain (2D FDTD) method. Both the conductor loss and the substrate loss are modeled by the 2D method. Besides the parallel-plate structure, electronic packages also comprise of many transmission lines including microstrip- and stripline-type structures. Those two types of structures are also resolved by the 2D method. So a unified solver may be developed in the context of 2D method for the signal and power integrity analysis of electronic packages. The electromagnetic interference (EMI) issue of electronic packages is also touched in this paper, which is mainly focused on the radiation due to the edge effect of the parallel plate structure in a package. Numerical examples are given to demonstrate the method.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122825585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550218
J. Chandrasekhar, E. Engin, M. Swaminathan, K. Uriu, T. Yamada
Differential lines are extensively used in high-speed digital circuits due to their ability to improve signal integrity by rejecting common-mode noise. However noise is injected into differential signals when there are irregularities in the signaling setup. These anomalies may be via transitions of differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. This paper quantifies noise due to irregular differential structures in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The effect of signal to power coupling from differential lines on signal jitter is also investigated.
{"title":"Noise induced jitter in differential signaling","authors":"J. Chandrasekhar, E. Engin, M. Swaminathan, K. Uriu, T. Yamada","doi":"10.1109/ECTC.2008.4550218","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550218","url":null,"abstract":"Differential lines are extensively used in high-speed digital circuits due to their ability to improve signal integrity by rejecting common-mode noise. However noise is injected into differential signals when there are irregularities in the signaling setup. These anomalies may be via transitions of differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. This paper quantifies noise due to irregular differential structures in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The effect of signal to power coupling from differential lines on signal jitter is also investigated.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550094
Li Li, M. Nagar, J. Xue
Power and power density increase in microelectronics is a major challenge for packaging high performance ASIC and microprocessor devices. The thermal interface material (TIM) used between the chip and the heat spreader of the Flip Chip Plastic Ball Grid Array (FC-PBGA) package plays a very important role in the package thermal performance. Not only does it affect package thermal performance, it can also affect assembly yield and package reliability during manufacturing and normal operation. In this study attention has been focused on improving thermal performance, manufacturing yield and reliability of the flip-chip PBGA single chip packages and the System in Package (SiP) modules. Computational Fluid Dynamics (CFD) software was used to investigate the effect of TIM on FC-PBGA thermal performance. The effect of thermal interface material was then studied for controlling the interaction between the heat spreader and the FC-PBGA SiP module to reduce module warpage and to improve module assembly yield. Qualification of TIM for FC-PBGA at both the component level and the system level was discussed. Component level testing data showed that the thermal characteristics and mechanical integrity of the TIM selected can be evaluated by using the same stress conditions used in package reliability qualification. Finally, system level non- operational humidity test results showed that good mechanical reliability at the thermal interface of the FC-PBGA can be achieved by optimizing the heat spreader attaching process.
{"title":"Effect of thermal interface materials on manufacturing and reliability of Flip Chip PBGA and SiP packages","authors":"Li Li, M. Nagar, J. Xue","doi":"10.1109/ECTC.2008.4550094","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550094","url":null,"abstract":"Power and power density increase in microelectronics is a major challenge for packaging high performance ASIC and microprocessor devices. The thermal interface material (TIM) used between the chip and the heat spreader of the Flip Chip Plastic Ball Grid Array (FC-PBGA) package plays a very important role in the package thermal performance. Not only does it affect package thermal performance, it can also affect assembly yield and package reliability during manufacturing and normal operation. In this study attention has been focused on improving thermal performance, manufacturing yield and reliability of the flip-chip PBGA single chip packages and the System in Package (SiP) modules. Computational Fluid Dynamics (CFD) software was used to investigate the effect of TIM on FC-PBGA thermal performance. The effect of thermal interface material was then studied for controlling the interaction between the heat spreader and the FC-PBGA SiP module to reduce module warpage and to improve module assembly yield. Qualification of TIM for FC-PBGA at both the component level and the system level was discussed. Component level testing data showed that the thermal characteristics and mechanical integrity of the TIM selected can be evaluated by using the same stress conditions used in package reliability qualification. Finally, system level non- operational humidity test results showed that good mechanical reliability at the thermal interface of the FC-PBGA can be achieved by optimizing the heat spreader attaching process.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124226781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550027
N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Zhang Wu, Yang Rui, L. Ebin
Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.
{"title":"Development of 3D silicon module with TSV for system in packaging","authors":"N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Zhang Wu, Yang Rui, L. Ebin","doi":"10.1109/ECTC.2008.4550027","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550027","url":null,"abstract":"Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550194
S. Koh, R. Tummala, A. Saxena, P. Selvam
The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.
{"title":"A numerical analysis of crack growth and morphology evolution in chip-to-packages nano-interconnections","authors":"S. Koh, R. Tummala, A. Saxena, P. Selvam","doi":"10.1109/ECTC.2008.4550194","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550194","url":null,"abstract":"The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 mum. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 mum down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance. The PRC at Georgia Institute of Technology is proposing re-workable copper based nano-interconnections as a new interconnection paradigm as the next step beyond lead-free solders for future low-cost, high performance and high reliability packages. However, very limited data is published about the fatigue life of nano-crystalline materials and specifically those of nano-crystalline copper. It is important to predict crack growth as it can aid the understanding of the useful life of the IC-packages' interconnections. Multiple mechanisms may be responsible for crack initiation, but eventually most dominant fatigue cracks form a surface crack, which often have a semi-elliptical shape. Hence, the fatigue crack growth life predictions in this study are based on the assumption of elliptical and semi-elliptical cracks being initiated in the nano-interconnections. In this study, numerical analysis using the J-integral stress intensity parameter, in conjunction with experimental fatigue crack growth data, has been employed to study semi-elliptical crack growth and morphology evolution in nano-interconnection subject to uniaxial fatigue loading in linear-elastic conditions. The results indicate that a J-integral finite element analysis, using the loading portion of the fatigue cycle, in conjunction with known rates of fatigue crack growth can approximate surface crack morphology evolution. This study also predicts that the long crack growth is a relatively small portion of the total fatigue life of the material for the experimental LCF conditions. Hence, initiation of the cracks in the interconnection is the main criterion used to predict its fatigue life.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550110
Jinseong Kim, Kiwook Lee, Dongjoo Park, Taekyung Hwang, Kwangho Kim, Daebyoung Kang, Jaedong Kim, Choonheung Lee, C. Scanlan, C. Berry, C. Zwenger, L. Smith, M. Dreiza, R. Darveaux
In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.
{"title":"Application of through mold via (TMV) as PoP base package","authors":"Jinseong Kim, Kiwook Lee, Dongjoo Park, Taekyung Hwang, Kwangho Kim, Daebyoung Kang, Jaedong Kim, Choonheung Lee, C. Scanlan, C. Berry, C. Zwenger, L. Smith, M. Dreiza, R. Darveaux","doi":"10.1109/ECTC.2008.4550110","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550110","url":null,"abstract":"In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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