Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085734
P. Sadagopan, V. Vaithianathan, R. Srinivasan
In this paper, we have analyzed the performance enhancement of reconfigurable field effect transistor (RFET) using gate workfunction, inter-gate length and inter-gate dielectric permittivity through TCAD simulations. The parameters, ON current, OFF current and ION/IOFF ratio are extracted from the saturated ID-VG characteristics. When the inter-gate length is varied, enhanced ION/IOFF ratio is achieved comparing with the conventional RFET. Inter-gate dielectric permittivity variation also offers better ION/IOFF ratio comparatively.
本文通过TCAD仿真分析了栅极工作函数、栅极间长度和栅极间介电常数对可重构场效应晶体管(reconfigurable field effect transistor, RFET)性能的增强作用。参数，ON电流，OFF电流和离子/IOFF比是从饱和ID-VG特性中提取的。当栅极间长度变化时，与传统的fet相比，离子/IOFF比有所提高。栅极间介电常数的变化也提供了相对较好的ION/IOFF比。
{"title":"Performance enhancement of reconfigurable FET using gate workfunctlon, inter-gate length and inter-gate dielectric permittivity","authors":"P. Sadagopan, V. Vaithianathan, R. Srinivasan","doi":"10.1109/ICSCN.2017.8085734","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085734","url":null,"abstract":"In this paper, we have analyzed the performance enhancement of reconfigurable field effect transistor (RFET) using gate workfunction, inter-gate length and inter-gate dielectric permittivity through TCAD simulations. The parameters, ON current, OFF current and I<inf>ON</inf>/I<inf>OFF</inf> ratio are extracted from the saturated I<inf>D</inf>-V<inf>G</inf> characteristics. When the inter-gate length is varied, enhanced I<inf>ON</inf>/I<inf>OFF</inf> ratio is achieved comparing with the conventional RFET. Inter-gate dielectric permittivity variation also offers better I<inf>ON</inf>/I<inf>OFF</inf> ratio comparatively.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130938012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085421
M. Edhayadharshini, V. Bhanumathi
Kidney disease is one of the life threatening diseases prevailing among the humans. Most of the people die because of kidney diseases. It occurs due to the change which is occurring in the production of DNA cells (cancer), protein deficiency (nephritis) etc., In this paper, an automatic detection of the kidney diseases from CT abdominal images is proposed. First, the CT abdominal images are acquired and Region of Interest segmentation is performed for the kidney components, then the segmented image is preprocessed using color phase lab model which intends to remove the irrelevant noises and distinct the colors presented in image. The preprocessed image is further used for obtaining the infected region using Fuzzy C-Means clustering model. Feature selection of the segmented image is done by Gabor and PHOG features. With the use of Random Forest classifier, the segmented image is classified as abnormal and normal classes. A confusion matrix is estimated for analyzing the rate of prediction of the images to its relevant classes. Performance metrics such as True positive rate are estimated.
{"title":"Abnormalities detection in kidney using multithreading technology","authors":"M. Edhayadharshini, V. Bhanumathi","doi":"10.1109/ICSCN.2017.8085421","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085421","url":null,"abstract":"Kidney disease is one of the life threatening diseases prevailing among the humans. Most of the people die because of kidney diseases. It occurs due to the change which is occurring in the production of DNA cells (cancer), protein deficiency (nephritis) etc., In this paper, an automatic detection of the kidney diseases from CT abdominal images is proposed. First, the CT abdominal images are acquired and Region of Interest segmentation is performed for the kidney components, then the segmented image is preprocessed using color phase lab model which intends to remove the irrelevant noises and distinct the colors presented in image. The preprocessed image is further used for obtaining the infected region using Fuzzy C-Means clustering model. Feature selection of the segmented image is done by Gabor and PHOG features. With the use of Random Forest classifier, the segmented image is classified as abnormal and normal classes. A confusion matrix is estimated for analyzing the rate of prediction of the images to its relevant classes. Performance metrics such as True positive rate are estimated.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133761147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085649
K. M. Krishna, M. Madhan
Two Vertical Cavity Surface Emitting Laser (VCSEL) diode structures based on InGaAs-GaAs and GaAs-AlGaAs are considered for thermal analysis and their impact on 850 nm digital optical link are investigated. The effect of Multi Mode Fiber (MMF) link length and VCSEL temperature on the overall link performance is compared for both the cases under 1.25 Gb/s transmissions. Bit Error Rate (BER) of 2.02 × 10−5, 1.48 × 10−5 and 2.15 × 10−5, 1.55 × 10−5 for InGaAs-GaAs based VCSEL and GaAs-AlGaAs based VCSEL at 25°C and 40°C are predicted at a fiber length of 1 km. Optimum biasing conditions pertaining to maximum 3 dB bandwidth for both the structures are also determined.
{"title":"A comparative study of thermal performance in two VCSEL structures for high bit rate digital optical links","authors":"K. M. Krishna, M. Madhan","doi":"10.1109/ICSCN.2017.8085649","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085649","url":null,"abstract":"Two Vertical Cavity Surface Emitting Laser (VCSEL) diode structures based on InGaAs-GaAs and GaAs-AlGaAs are considered for thermal analysis and their impact on 850 nm digital optical link are investigated. The effect of Multi Mode Fiber (MMF) link length and VCSEL temperature on the overall link performance is compared for both the cases under 1.25 Gb/s transmissions. Bit Error Rate (BER) of 2.02 × 10<sup>−5</sup>, 1.48 × 10<sup>−5</sup> and 2.15 × 10<sup>−5</sup>, 1.55 × 10<sup>−5</sup> for InGaAs-GaAs based VCSEL and GaAs-AlGaAs based VCSEL at 25°C and 40°C are predicted at a fiber length of 1 km. Optimum biasing conditions pertaining to maximum 3 dB bandwidth for both the structures are also determined.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115419993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085687
V. V. Kumar, A. Vidya, M. Sharumathy, R. Kanizohi
In this paper, a novel resolution enhancement approach based on Quaternion wavelet transform (QWT) with singular value decomposition (SVD) is proposed. The technique decomposes the input image into sixteen frequency sub bands by using QWT. The singular values of the low-low sub band image are estimated and the high frequency sub bands are interpolated using Lanczos interpolation. Finally, a contrast enhanced super resolution image is obtained by combining the interpolated high frequency sub bands and contrast enhanced image by inverse QWT. The visual and quantitative results show that the proposed QWT-SVD method clearly outperforms the bilinear, bicubic, DWT-bicubic, DTCWT-NLM-SVD with better edge preservation.
{"title":"Super resolution enhancement of medical image using quaternion wavelet transform with SVD","authors":"V. V. Kumar, A. Vidya, M. Sharumathy, R. Kanizohi","doi":"10.1109/ICSCN.2017.8085687","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085687","url":null,"abstract":"In this paper, a novel resolution enhancement approach based on Quaternion wavelet transform (QWT) with singular value decomposition (SVD) is proposed. The technique decomposes the input image into sixteen frequency sub bands by using QWT. The singular values of the low-low sub band image are estimated and the high frequency sub bands are interpolated using Lanczos interpolation. Finally, a contrast enhanced super resolution image is obtained by combining the interpolated high frequency sub bands and contrast enhanced image by inverse QWT. The visual and quantitative results show that the proposed QWT-SVD method clearly outperforms the bilinear, bicubic, DWT-bicubic, DTCWT-NLM-SVD with better edge preservation.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085739
B. Manuel, E. Konguvel, M. Kannan
In recent years the Fast Fourier Transform is widely used in a number of applications as it is considered to be an efficient algorithm to compute the Discrete Fourier Transform. The process of computing the FFT for large sequence real time data becomes complex and tedious. Hence it is necessary to design a system that can perform the FFT computation of large sequence data with reduced power consumption. This paper presents the design of low power Radix-8 DIT FFT. The proposed design aims at reducing the number of multipliers that are used to compute the FFT. This is achieved by swapping the input terms and reordering them. This leads to a reduction in the number of multipliers used to perform the computation and thereby causing a reduction in the power consumption. This method is highly advantageous when the input signals are lengthy since the number of multipliers used is large in number consuming very high power. In order to optimize the FFT architecture the number of multipliers is reduced thereby causing a significant reduction in power. The prototype for Radix-2 (8 point) and Radix-4 (16 point) optimized FFT is designed, implemented and simulated using Altera ModelSim DE2 EP2C35F672C6 FPGA device. The proposed Radix-2 (8 point) and Radix-4 (16 point) optimized FFT operates at a speed of 10.41 Gbps and 21.23 Gbps respectively.
近年来，快速傅里叶变换被认为是一种计算离散傅里叶变换的有效算法，在许多应用中得到了广泛的应用。大序列实时数据的快速傅里叶变换计算过程变得复杂而繁琐。因此，有必要设计一种能够在低功耗的情况下对大序列数据进行FFT计算的系统。本文介绍了低功耗Radix-8 DIT FFT的设计。提出的设计旨在减少用于计算FFT的乘法器的数量。这是通过交换输入项并重新排序来实现的。这导致用于执行计算的乘法器数量减少，从而导致功耗降低。这种方法在输入信号较长的情况下非常有利，因为使用的乘法器数量多，消耗的功率非常高。为了优化FFT架构，减少了乘法器的数量，从而显著降低了功耗。利用Altera ModelSim DE2 EP2C35F672C6 FPGA器件设计、实现和仿真了Radix-2(8点)和Radix-4(16点)优化的FFT原型。所提出的Radix-2(8点)和Radix-4(16点)优化的FFT分别以10.41 Gbps和21.23 Gbps的速度运行。
{"title":"An area efficient high speed optimized FFT algorithm","authors":"B. Manuel, E. Konguvel, M. Kannan","doi":"10.1109/ICSCN.2017.8085739","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085739","url":null,"abstract":"In recent years the Fast Fourier Transform is widely used in a number of applications as it is considered to be an efficient algorithm to compute the Discrete Fourier Transform. The process of computing the FFT for large sequence real time data becomes complex and tedious. Hence it is necessary to design a system that can perform the FFT computation of large sequence data with reduced power consumption. This paper presents the design of low power Radix-8 DIT FFT. The proposed design aims at reducing the number of multipliers that are used to compute the FFT. This is achieved by swapping the input terms and reordering them. This leads to a reduction in the number of multipliers used to perform the computation and thereby causing a reduction in the power consumption. This method is highly advantageous when the input signals are lengthy since the number of multipliers used is large in number consuming very high power. In order to optimize the FFT architecture the number of multipliers is reduced thereby causing a significant reduction in power. The prototype for Radix-2 (8 point) and Radix-4 (16 point) optimized FFT is designed, implemented and simulated using Altera ModelSim DE2 EP2C35F672C6 FPGA device. The proposed Radix-2 (8 point) and Radix-4 (16 point) optimized FFT operates at a speed of 10.41 Gbps and 21.23 Gbps respectively.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085682
K. Nandhini, M. Pavithra, K. Revathi, A. Rajiv
In crowded scene abnormal event detection is a major issue. Many existing methods are there. Abnormal events are those which cannot be well represented. For example, if a flight is hijacked or it is damaged, it is due to some abnormal activities. Abnormal activities may occur due to human intervention or due to some weather conditions. So in this system we are using abnormal detector to detect the events. Abnormal patterns are extracted from incoming events. The major contribution to this paper are: 1) In this abnormal detector is used to identify abnormal events. In this complexity is high in video events due to the presence of noise. By using mixture of Gaussian interference can be avoided. 2) In this, we are using Gaussian Mixture Model to reduce interference. Even though the method has high complexity. 3) Unusually normal events occur in testing videos which differ from training once this is due to existence of abnormalities. They presented as an online updating strategy is proposed to cover these cases in normal patterns as a result, it mostly eliminates false detections. Effectiveness of the proposed algorithm Is verified by using state of the art.
{"title":"Anamoly detection for safety monitoring","authors":"K. Nandhini, M. Pavithra, K. Revathi, A. Rajiv","doi":"10.1109/ICSCN.2017.8085682","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085682","url":null,"abstract":"In crowded scene abnormal event detection is a major issue. Many existing methods are there. Abnormal events are those which cannot be well represented. For example, if a flight is hijacked or it is damaged, it is due to some abnormal activities. Abnormal activities may occur due to human intervention or due to some weather conditions. So in this system we are using abnormal detector to detect the events. Abnormal patterns are extracted from incoming events. The major contribution to this paper are: 1) In this abnormal detector is used to identify abnormal events. In this complexity is high in video events due to the presence of noise. By using mixture of Gaussian interference can be avoided. 2) In this, we are using Gaussian Mixture Model to reduce interference. Even though the method has high complexity. 3) Unusually normal events occur in testing videos which differ from training once this is due to existence of abnormalities. They presented as an online updating strategy is proposed to cover these cases in normal patterns as a result, it mostly eliminates false detections. Effectiveness of the proposed algorithm Is verified by using state of the art.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125983032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085731
P. MohanaPriya, S. Shalinie
Software Defined Network is an innovative network architecture which provides network control through software logic. It decouples control and data plane to customize the network according to the user needs. OpenFlow, a standardized network protocol acts as an interface between controllers and switches. The softwarized controllers are highly vulnerable for Distributed Denial of Service attacks. The proposed detection system uses an unsupervised stochastic Restricted Boltzmann Machine algorithm to self-learn the reliable network metrics. This algorithm detects and classifies the type of DDoS attacks in a dynamic network environment by framing a new context. The results prove that RBM based DDoS detection system achieves higher accuracy than the existing methods.
{"title":"Restricted Boltzmann Machine based detection system for DDoS attack in Software Defined Networks","authors":"P. MohanaPriya, S. Shalinie","doi":"10.1109/ICSCN.2017.8085731","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085731","url":null,"abstract":"Software Defined Network is an innovative network architecture which provides network control through software logic. It decouples control and data plane to customize the network according to the user needs. OpenFlow, a standardized network protocol acts as an interface between controllers and switches. The softwarized controllers are highly vulnerable for Distributed Denial of Service attacks. The proposed detection system uses an unsupervised stochastic Restricted Boltzmann Machine algorithm to self-learn the reliable network metrics. This algorithm detects and classifies the type of DDoS attacks in a dynamic network environment by framing a new context. The results prove that RBM based DDoS detection system achieves higher accuracy than the existing methods.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127154899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085693
V. Gokilapriya, P. Bhuvaneswari
In 6LoWPAN, RPL routing protocol is suggested by IETF standard to enhance the Quality of Service of data transfer that occurs between non-root node to root node. In this paper, the performance of RPL is analyzed in terms of Packet Delivery Ratio and Round Trip Time. The analysis is carried out to study the behavior of topology control strategy in 6LoWPAN. Hence, the analysis is executed on various topologies namely linear, manual, elliptical and random. The proposed work is simulated using Cooja in Contiki Operating System environment. From the simulation results, it is inferred that the performance of both PDR and RTT in the manual topology outperforms the other three topologies. The reason being that manual topology are well planned topology which takes into account the channel impairment at the time of deployment which decides the QoS of the nodes.
{"title":"Analysis of RPL routing protocol on topology control mechanism","authors":"V. Gokilapriya, P. Bhuvaneswari","doi":"10.1109/ICSCN.2017.8085693","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085693","url":null,"abstract":"In 6LoWPAN, RPL routing protocol is suggested by IETF standard to enhance the Quality of Service of data transfer that occurs between non-root node to root node. In this paper, the performance of RPL is analyzed in terms of Packet Delivery Ratio and Round Trip Time. The analysis is carried out to study the behavior of topology control strategy in 6LoWPAN. Hence, the analysis is executed on various topologies namely linear, manual, elliptical and random. The proposed work is simulated using Cooja in Contiki Operating System environment. From the simulation results, it is inferred that the performance of both PDR and RTT in the manual topology outperforms the other three topologies. The reason being that manual topology are well planned topology which takes into account the channel impairment at the time of deployment which decides the QoS of the nodes.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085724
N. Jagadeeshkumar, D. Meganathan
This paper presents the design of a rounded, truncated hybrid multiplier. The maximum absolute error is ensured to be less than one unit of least position. The proposed strategy includes deletion, reduction of partial product bits of multiplier in order to reduce the number of full adders and half adders used during partial product reduction. The high speed computing system requires high-speed and low-power multipliers. This paper proposes a high performance hybrid tree multiplier by using both Wallace and Dadda methods in partial product reduction. The partial products are separated into four groups. Dadda reduction is used in group1 and group4, whereas Wallace tree reduction method is used in the remaining groups. Additionally, the Ling adder is incorporated in the proposed hybrid multiplier in the final stage, to reduce the final carry-propagation delay. The design is implemented, simulated and evaluated using H-SPICE tool with 32nm CMOS predictive technology model(PTM).
{"title":"A novel design of low power and high speed hybrid multiplier","authors":"N. Jagadeeshkumar, D. Meganathan","doi":"10.1109/ICSCN.2017.8085724","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085724","url":null,"abstract":"This paper presents the design of a rounded, truncated hybrid multiplier. The maximum absolute error is ensured to be less than one unit of least position. The proposed strategy includes deletion, reduction of partial product bits of multiplier in order to reduce the number of full adders and half adders used during partial product reduction. The high speed computing system requires high-speed and low-power multipliers. This paper proposes a high performance hybrid tree multiplier by using both Wallace and Dadda methods in partial product reduction. The partial products are separated into four groups. Dadda reduction is used in group1 and group4, whereas Wallace tree reduction method is used in the remaining groups. Additionally, the Ling adder is incorporated in the proposed hybrid multiplier in the final stage, to reduce the final carry-propagation delay. The design is implemented, simulated and evaluated using H-SPICE tool with 32nm CMOS predictive technology model(PTM).","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/ICSCN.2017.8085732
M. Sukhanya, K. Gavaskar
Inter-Integrated Circuit (I2C) plays an important role as an interface in communication between devices. EEPROMS, ADC, DAC and RTC require an interface for communication and I2C is used as an interface between them. The RTL behavior of the I2C Master Controller is verified using System Verilog and its verification is carried out in Mentor Graphics tool. The functionality of the design is verified and there is no data loss in transmission. The proposed verification environment includes the constrained randomization, functional coverage and code coverage. In the proposed system, DUT is subjected to the verification with various coverage metrics such as code coverage, functional coverage, etc. Complex scenarios are covered with multiple cover groups which have many cover points. The code coverage obtained for the DUT is 92.38 percentage. The functional coverage for the parameters such as address and data are obtained as 100 percentage.
{"title":"Functional verification environment for I2C master controller using system verilog","authors":"M. Sukhanya, K. Gavaskar","doi":"10.1109/ICSCN.2017.8085732","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085732","url":null,"abstract":"Inter-Integrated Circuit (I2C) plays an important role as an interface in communication between devices. EEPROMS, ADC, DAC and RTC require an interface for communication and I2C is used as an interface between them. The RTL behavior of the I2C Master Controller is verified using System Verilog and its verification is carried out in Mentor Graphics tool. The functionality of the design is verified and there is no data loss in transmission. The proposed verification environment includes the constrained randomization, functional coverage and code coverage. In the proposed system, DUT is subjected to the verification with various coverage metrics such as code coverage, functional coverage, etc. Complex scenarios are covered with multiple cover groups which have many cover points. The code coverage obtained for the DUT is 92.38 percentage. The functional coverage for the parameters such as address and data are obtained as 100 percentage.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125065636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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