Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399667
K. Wawryn, R. Suszynski, B. Strzeszewski
The paper presents a high speed and a high resolution pipelined A/D converter relying on a current mode technique. The A/D converter structure is composed of current mode building blocks. All building blocks have been designed, then manufactured, in CMOS AMS 0.8 /spl mu/m technology and measured to verify the proposed concept.
{"title":"Signal processing building blocks for pipelined A/D converter","authors":"K. Wawryn, R. Suszynski, B. Strzeszewski","doi":"10.1109/ICECS.2004.1399667","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399667","url":null,"abstract":"The paper presents a high speed and a high resolution pipelined A/D converter relying on a current mode technique. The A/D converter structure is composed of current mode building blocks. All building blocks have been designed, then manufactured, in CMOS AMS 0.8 /spl mu/m technology and measured to verify the proposed concept.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75419574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399643
Hung-Pin Chen, J. Kuo
The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.
本文报道了一种新颖的0.8 V CMOS真单相时钟(TSPC)绝热差分级联电压开关(DCVS)逻辑电路，该电路采用自举技术用于低功耗VLSI。通过通通晶体管和补偿晶体管，获得了易于实现时钟的TSPC方案。利用自举晶体管的电容耦合，这种采用自举技术的0.8 V TSPC绝热DCVS逻辑电路比采用时钟绝热锁存器(CAL)方法的电路能耗低31%。
{"title":"A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI","authors":"Hung-Pin Chen, J. Kuo","doi":"10.1109/ICECS.2004.1399643","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399643","url":null,"abstract":"The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72547017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399723
A. Morgenshtein, Evgeny Bolotin, I. Cidon, A. Kolodny, R. Ginosar
A new concept of micro-modem interface for reliable communications in networks on chip (NoC) is presented. The micro-modem addresses the major problems of sub-micron interconnect and contains techniques for reliability improvement. The architecture, data flow and components of the micro-modem are presented. Various techniques and processes are analyzed for compact on-chip implementation. Design and application considerations are discussed.
{"title":"Micro-modem - reliability solution for NoC communications","authors":"A. Morgenshtein, Evgeny Bolotin, I. Cidon, A. Kolodny, R. Ginosar","doi":"10.1109/ICECS.2004.1399723","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399723","url":null,"abstract":"A new concept of micro-modem interface for reliable communications in networks on chip (NoC) is presented. The micro-modem addresses the major problems of sub-micron interconnect and contains techniques for reliability improvement. The architecture, data flow and components of the micro-modem are presented. Various techniques and processes are analyzed for compact on-chip implementation. Design and application considerations are discussed.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74802515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399646
Rong-Jian Chen, Jui-Lin Lai
The VLSI implementation of the universal two-dimensional (2D) cellular automata transform (CAT) as well as inverse CAT (ICAT) is present in this paper. The universal 2D CAT/ICAT chip is based on the 2D CAB generator. To facilitate the development of a universal 2D CAB generator, we adopted a CA cell structure with programmable additive rules to generate 1D CAB first, and then utilized the canonical products of 2D CAB to perform the 2D CAB. We have accomplished simulations of the universal 2D 8/spl times/8 CAT/ICAT chip by using CANDENCE tools. We also have completed the circuit synthesis of the 2D CAT/ICAT chip by using the SYNOPSE tools with the TSMC 0.35 /spl mu/m CMOS data-path cell-library. The maximum operation frequency was 120 MHz, and the area size was 6.8225 mm/sup 2/. It shows that the architecture of the proposed universal 2D CAT/ICAT is suitable for VLSI realization.
{"title":"VLSI implementation of the universal 2-D CAT/ICAT system","authors":"Rong-Jian Chen, Jui-Lin Lai","doi":"10.1109/ICECS.2004.1399646","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399646","url":null,"abstract":"The VLSI implementation of the universal two-dimensional (2D) cellular automata transform (CAT) as well as inverse CAT (ICAT) is present in this paper. The universal 2D CAT/ICAT chip is based on the 2D CAB generator. To facilitate the development of a universal 2D CAB generator, we adopted a CA cell structure with programmable additive rules to generate 1D CAB first, and then utilized the canonical products of 2D CAB to perform the 2D CAB. We have accomplished simulations of the universal 2D 8/spl times/8 CAT/ICAT chip by using CANDENCE tools. We also have completed the circuit synthesis of the 2D CAT/ICAT chip by using the SYNOPSE tools with the TSMC 0.35 /spl mu/m CMOS data-path cell-library. The maximum operation frequency was 120 MHz, and the area size was 6.8225 mm/sup 2/. It shows that the architecture of the proposed universal 2D CAT/ICAT is suitable for VLSI realization.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74014149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399627
Boaz Shem-Tov, M. Kozak, E. Friedman
Single-bit delta-sigma (/spl Delta//spl Sigma/) modulation reduces the complexity of receive beamformers in ultrasound and sonar imaging applications. These applications, however, require a sampling rate in excess of 220 MHz due to the high bandwidth of the echo signals. In this paper, the design and implementation of a 250 MHz second-order single-bit /spl Delta//spl Sigma/ modulator suitable for ultrasound/sonar applications is presented. The circuit is realized in a 0.18 /spl mu/m P-well CMOS technology and dissipates 20 mW average power when clocked at 250 MHz. The area of the circuit is 0.24 mm/sup 2/. Post-layout simulations show that the modulator achieves 48 dB maximum SNR and 50 dB dynamic range for a 5 MHz input signal bandwidth.
{"title":"A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications","authors":"Boaz Shem-Tov, M. Kozak, E. Friedman","doi":"10.1109/ICECS.2004.1399627","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399627","url":null,"abstract":"Single-bit delta-sigma (/spl Delta//spl Sigma/) modulation reduces the complexity of receive beamformers in ultrasound and sonar imaging applications. These applications, however, require a sampling rate in excess of 220 MHz due to the high bandwidth of the echo signals. In this paper, the design and implementation of a 250 MHz second-order single-bit /spl Delta//spl Sigma/ modulator suitable for ultrasound/sonar applications is presented. The circuit is realized in a 0.18 /spl mu/m P-well CMOS technology and dissipates 20 mW average power when clocked at 250 MHz. The area of the circuit is 0.24 mm/sup 2/. Post-layout simulations show that the modulator achieves 48 dB maximum SNR and 50 dB dynamic range for a 5 MHz input signal bandwidth.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77642997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399638
I. Brouk, Y. Nemirovsky
Design, operation and measurement results of a CMOS camera implemented within a SOI wafer are presented. The peak of photodiode quantum efficiency is obtained for the wavelengths of 400-500 nm. In addition, noise measurements of the 1/f noise in P-MOS and N-MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in regular and SOI wafers) of 0.35 /spl mu/m CMOS analog process are compared and it is found that they exhibit similar 1/f noise. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.
介绍了在SOI晶圆内实现的CMOS相机的设计、运行和测量结果。在400 ~ 500 nm波长处，光电二极管量子效率达到峰值。此外，在从亚阈值到饱和的宽偏置条件下，对用于模拟应用的P-MOS和N-MOS晶体管中的1/f噪声进行了噪声测量。比较了两种0.35 /spl μ l /m CMOS模拟工艺的实现(在普通晶圆和SOI晶圆上)，发现它们具有相似的1/f噪声。研究结果对CMOS模拟电路1/f噪声的设计和建模具有一定的指导意义。
{"title":"CMOS SOI image sensor","authors":"I. Brouk, Y. Nemirovsky","doi":"10.1109/ICECS.2004.1399638","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399638","url":null,"abstract":"Design, operation and measurement results of a CMOS camera implemented within a SOI wafer are presented. The peak of photodiode quantum efficiency is obtained for the wavelengths of 400-500 nm. In addition, noise measurements of the 1/f noise in P-MOS and N-MOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two implementations (in regular and SOI wafers) of 0.35 /spl mu/m CMOS analog process are compared and it is found that they exhibit similar 1/f noise. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77895763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399669
A. Kuperman, R. Rabinovici
For pt. I, see ibid., p.262-5. The paper presents different kinds of circuits used for autonomous induction generator output voltage regulation. Operation of SVC (static VAr compensator) and STATCON (static condenser) based voltage regulators is explained, and the advantages and disadvantages of each type are shown. Different control strategies of voltage source and current source inverter based STATCONs are discussed. A novel current sensorless fixed frequency type of voltage regulator is also shown. In addition, extended simulation results are given, based on a real induction machine data.
{"title":"Shunt voltage regulators for autonomous induction generators. Part II: circuits and systems","authors":"A. Kuperman, R. Rabinovici","doi":"10.1109/ICECS.2004.1399669","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399669","url":null,"abstract":"For pt. I, see ibid., p.262-5. The paper presents different kinds of circuits used for autonomous induction generator output voltage regulation. Operation of SVC (static VAr compensator) and STATCON (static condenser) based voltage regulators is explained, and the advantages and disadvantages of each type are shown. Different control strategies of voltage source and current source inverter based STATCONs are discussed. A novel current sensorless fixed frequency type of voltage regulator is also shown. In addition, extended simulation results are given, based on a real induction machine data.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85238000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399721
Z. Zalevsky, A. Shemer, V. Eckhouse, D. Mendlovic, S. Zach
A highly resolved carrier and information extraction of an optically modulated radar signal is presented. The extraction is done by passing the optical beam through a monitoring path that realizes an FIR filter. Replications of the monitoring signal realize the required spectral scan of the filter. Despite the fact that the filter configuration is fixed, each replication experiences different spectral filtering. The radar carrier is detected by observing the energetic fluctuations in a low rate detector. The RF information is extracted by positioning a low rate tunable filter at the detected carrier frequency.
{"title":"Compact RF-photonic configuration for highly resolved and ultra-fast extraction of carrier and information of radar signal","authors":"Z. Zalevsky, A. Shemer, V. Eckhouse, D. Mendlovic, S. Zach","doi":"10.1109/ICECS.2004.1399721","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399721","url":null,"abstract":"A highly resolved carrier and information extraction of an optically modulated radar signal is presented. The extraction is done by passing the optical beam through a monitoring path that realizes an FIR filter. Replications of the monitoring signal realize the required spectral scan of the filter. Despite the fact that the filter configuration is fixed, each replication experiences different spectral filtering. The radar carrier is detected by observing the energetic fluctuations in a low rate detector. The RF information is extracted by positioning a low rate tunable filter at the detected carrier frequency.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80291139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399753
B. Taskin, I. Kourtev
The paper addresses the advanced timing analysis of multiphase level-sensitive synchronous circuits under clock skew scheduling (Kourtev, I.S. and Friedman, E.G., "Optimization Through Clock Skew Scheduling", Kluwer Academic Publishers, 2000). The timing analysis framework previously offered for a single-phase clocking scheme (Taskin, B. and Kourtev, I.S., Proc. 15th IEEE Int. ASIC/SOC Conf. p.358-62, 2002) is enhanced to accommodate a multiphase clocking scheme. In particular, the timing analysis framework is used to formulate the clock period minimization problem of multiphase level-sensitive circuits. The modified big M method of Taskin and Kourtev is used to linearize the formulation of the clock period minimization problem and experiments are performed on the ISCAS'89 benchmark circuits. In single-phase level-sensitive circuits, up to 63% improvements over conventional zero clock skew, edge-triggered circuits are achieved through the simultaneous application of non-zero clock skew scheduling and time borrowing. Comparable improvements of up to 62% are achieved for the same circuit topologies under a multiphase clocking scheme.
{"title":"Advanced timing of level-sensitive sequential circuits","authors":"B. Taskin, I. Kourtev","doi":"10.1109/ICECS.2004.1399753","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399753","url":null,"abstract":"The paper addresses the advanced timing analysis of multiphase level-sensitive synchronous circuits under clock skew scheduling (Kourtev, I.S. and Friedman, E.G., \"Optimization Through Clock Skew Scheduling\", Kluwer Academic Publishers, 2000). The timing analysis framework previously offered for a single-phase clocking scheme (Taskin, B. and Kourtev, I.S., Proc. 15th IEEE Int. ASIC/SOC Conf. p.358-62, 2002) is enhanced to accommodate a multiphase clocking scheme. In particular, the timing analysis framework is used to formulate the clock period minimization problem of multiphase level-sensitive circuits. The modified big M method of Taskin and Kourtev is used to linearize the formulation of the clock period minimization problem and experiments are performed on the ISCAS'89 benchmark circuits. In single-phase level-sensitive circuits, up to 63% improvements over conventional zero clock skew, edge-triggered circuits are achieved through the simultaneous application of non-zero clock skew scheduling and time borrowing. Comparable improvements of up to 62% are achieved for the same circuit topologies under a multiphase clocking scheme.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90699120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399623
M. Kahane, Y. Ben-Shimol, D. Sadot
Several studies demonstrated that network traffic exhibits self-similarity and long-range dependence. Of the new methods for modeling self-similar traffic, the pseudo self-similar traffic model (PSST) (Robert and Le Boudec (1997)) is especially attractive since it is simple, has only two parameters to fit and is readily analyzed by classical queueing theory methods. In this paper we perform a performance evaluation of the PSST model by investigating its suitability to model the queueing behavior of self-similar traffic. We simulate a system fed by self-similar traffic traces with a single server and geometrically distributed service times. The observed steady state queue size distribution is compared to the one predicted by a PSST model fitted to the parameters of the traffic traces.
{"title":"Performance evaluation of pseudo self-similar traffic","authors":"M. Kahane, Y. Ben-Shimol, D. Sadot","doi":"10.1109/ICECS.2004.1399623","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399623","url":null,"abstract":"Several studies demonstrated that network traffic exhibits self-similarity and long-range dependence. Of the new methods for modeling self-similar traffic, the pseudo self-similar traffic model (PSST) (Robert and Le Boudec (1997)) is especially attractive since it is simple, has only two parameters to fit and is readily analyzed by classical queueing theory methods. In this paper we perform a performance evaluation of the PSST model by investigating its suitability to model the queueing behavior of self-similar traffic. We simulate a system fed by self-similar traffic traces with a single server and geometrically distributed service times. The observed steady state queue size distribution is compared to the one predicted by a PSST model fitted to the parameters of the traffic traces.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89554128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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