Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367875
J. Anthony, M. Payne, C. A. Landis, J. E. Bullock
Acenes such as anthracene, tetracene and pentacene are high-performance components of several classes of organic devices. Significant research has been aimed at making these normally insoluble materials into compounds that can be processed by solution methods. We report our approach to acene solubilization by careful consideration of how substituents affect the solid-state order of the materials. This change in native order leads to increases in conductivity, and in collaboration with the Jackson group has shown TFT mobilities >0.5 cm/sup 2//Vs from both vapor and solution. With this initial data in hand, we report our progress on second-generation materials designed to address the shortcomings of our initial compounds.
{"title":"The molecular engineering of acenes: avoiding the drawbacks of improved solubility [organic electronics materials]","authors":"J. Anthony, M. Payne, C. A. Landis, J. E. Bullock","doi":"10.1109/DRC.2004.1367875","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367875","url":null,"abstract":"Acenes such as anthracene, tetracene and pentacene are high-performance components of several classes of organic devices. Significant research has been aimed at making these normally insoluble materials into compounds that can be processed by solution methods. We report our approach to acene solubilization by careful consideration of how substituents affect the solid-state order of the materials. This change in native order leads to increases in conductivity, and in collaboration with the Jackson group has shown TFT mobilities >0.5 cm/sup 2//Vs from both vapor and solution. With this initial data in hand, we report our progress on second-generation materials designed to address the shortcomings of our initial compounds.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117127227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367754
U. Mishra
This work presents a summary of the use of gallium nitride and its alloys in the development of semiconductor devices. It begins with a description of the HEMT and its use in microwave and power switching applications. Then follows a brief examination of MOSHFETs, MISHFETs and MISFETs. HBTs are discussed, along with the problems of poor electronic properties of p-type GaN and leakage through p-n junctions and etched surfaces. The paper concludes by referring to the POLFET which is based on modulating a 3D electron slab created by grading the polarization in the system, resulting in a MESFET with no doping.
{"title":"Gallium nitride electronics: Watt is the limit? [summary of GaN semiconductor devices]","authors":"U. Mishra","doi":"10.1109/DRC.2004.1367754","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367754","url":null,"abstract":"This work presents a summary of the use of gallium nitride and its alloys in the development of semiconductor devices. It begins with a description of the HEMT and its use in microwave and power switching applications. Then follows a brief examination of MOSHFETs, MISHFETs and MISFETs. HBTs are discussed, along with the problems of poor electronic properties of p-type GaN and leakage through p-n junctions and etched surfaces. The paper concludes by referring to the POLFET which is based on modulating a 3D electron slab created by grading the polarization in the system, resulting in a MESFET with no doping.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367861
N. Guisinger, R. Basu, M. Greene, A. Baluch, M. Hersam
In recent years, substantial progress has been made in the emerging field of molecular electronics. In particular, metal-molecule-metal junctions have been widely studied. In this paper, charge transport through molecule-semiconductor junctions is considered. The presence of the energy band gap in semiconductors provides opportunities for resonant tunneling through individual molecules, leading to interesting effects such as negative differential resistance (NDR). Furthermore, by doping the substrate, the majority charge carrier can be tailored, thus allowing asymmetry to be intentionally designed into the current-voltage characteristic. Through judicious choice of the molecular species, the bias voltage of the NDR can also be controlled. By demonstrating these effects on the Si(100) surface, semiconductor-based molecular electronic devices have the potential of being directly interfaced to conventional silicon integrated circuit technology. This paper summarizes recent theoretical and experimental work on silicon-based molecular resonant tunneling diodes.
{"title":"Characterization of silicon-based molecular resonant tunneling diodes with scanning tunneling microscopy","authors":"N. Guisinger, R. Basu, M. Greene, A. Baluch, M. Hersam","doi":"10.1109/DRC.2004.1367861","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367861","url":null,"abstract":"In recent years, substantial progress has been made in the emerging field of molecular electronics. In particular, metal-molecule-metal junctions have been widely studied. In this paper, charge transport through molecule-semiconductor junctions is considered. The presence of the energy band gap in semiconductors provides opportunities for resonant tunneling through individual molecules, leading to interesting effects such as negative differential resistance (NDR). Furthermore, by doping the substrate, the majority charge carrier can be tailored, thus allowing asymmetry to be intentionally designed into the current-voltage characteristic. Through judicious choice of the molecular species, the bias voltage of the NDR can also be controlled. By demonstrating these effects on the Si(100) surface, semiconductor-based molecular electronic devices have the potential of being directly interfaced to conventional silicon integrated circuit technology. This paper summarizes recent theoretical and experimental work on silicon-based molecular resonant tunneling diodes.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127312051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367788
N. Parthasarathy, Y. Dong, D. Scott, M. Urteaga, M. Rodwell
Device isolation of InP based HBTs in the mesa technology, is done by etching down to the substrate; this process suffers from lack of planarity and does not lend itself well to high levels of integration. We report on two techniques for planar isolation of InP based HBTs using selective implantation. The first method involves Fe implantation to isolate the InP collector-subcollector layers. In the second approach, we have utilized selective Si implantation in SI InP to form an isolated, N++ subcollector.
{"title":"Planar device isolation for InP based DHBTs","authors":"N. Parthasarathy, Y. Dong, D. Scott, M. Urteaga, M. Rodwell","doi":"10.1109/DRC.2004.1367788","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367788","url":null,"abstract":"Device isolation of InP based HBTs in the mesa technology, is done by etching down to the substrate; this process suffers from lack of planarity and does not lend itself well to high levels of integration. We report on two techniques for planar isolation of InP based HBTs using selective implantation. The first method involves Fe implantation to isolate the InP collector-subcollector layers. In the second approach, we have utilized selective Si implantation in SI InP to form an isolated, N++ subcollector.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129006419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367867
Y. Liu, A. Masahara, K. Ishii, T. Sekigawa, H. Takashirna, H. Yarnauchi, T. Tsutsurni, K. Sakamoto, E. Suzuki
For future ultra-low power circuit designs, flexible V/sub th/ control will inevitably be required. To meet this requirement, four-terminal (4-T) DG MOSFETs are promising, thanks to the static and/or dynamic V/sub th/ controllability by one of the double gates. Recently, we demonstrated independent double gate FinFETs, fabricated by using orientation-dependent wet etching. This method has great advantages in forming precise Si-fins with an atomically flat channel surface. In this paper, we present the successful fabrication of the ultra-thin Si-fins by wet etching, and the fine separated double gates. We show the excellent V/sub th/ controllability of the fabricated 4-T FinFETs by reducing the Si-fin thickness (T/sub Si/) down to 13 nm. We also discuss the T/sub Si/ dependence of the V/sub th/ tunable range on the T/sub Si/.
{"title":"4-terminal FinFETs with high threshold voltage controllability","authors":"Y. Liu, A. Masahara, K. Ishii, T. Sekigawa, H. Takashirna, H. Yarnauchi, T. Tsutsurni, K. Sakamoto, E. Suzuki","doi":"10.1109/DRC.2004.1367867","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367867","url":null,"abstract":"For future ultra-low power circuit designs, flexible V/sub th/ control will inevitably be required. To meet this requirement, four-terminal (4-T) DG MOSFETs are promising, thanks to the static and/or dynamic V/sub th/ controllability by one of the double gates. Recently, we demonstrated independent double gate FinFETs, fabricated by using orientation-dependent wet etching. This method has great advantages in forming precise Si-fins with an atomically flat channel surface. In this paper, we present the successful fabrication of the ultra-thin Si-fins by wet etching, and the fine separated double gates. We show the excellent V/sub th/ controllability of the fabricated 4-T FinFETs by reducing the Si-fin thickness (T/sub Si/) down to 13 nm. We also discuss the T/sub Si/ dependence of the V/sub th/ tunable range on the T/sub Si/.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130828862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367797
K. Long, H. Gleskova, S. Wagner, J. Sturm
In this paper, we present TFTs with excellent short-channel performance, fabricated at a temperature of 180/spl deg/C on clear plastic substrates. The performance of the TFTs on this clear plastic substrate is as good as that of TFTs made on glass substrates at the same temperature. In contrast to previous work on high temperature plastic substrates, the substrates were freestanding and not mounted to rigid substrates for fabrication, which is critical for maintaining a clean and clear back surface for the optical devices (e.g. OLEDs). These results will enable AMOLED displays on clear plastic substrates.
{"title":"Short channel amorphous-silicon TFTs on high-temperature clear plastic substrates [LED display applications]","authors":"K. Long, H. Gleskova, S. Wagner, J. Sturm","doi":"10.1109/DRC.2004.1367797","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367797","url":null,"abstract":"In this paper, we present TFTs with excellent short-channel performance, fabricated at a temperature of 180/spl deg/C on clear plastic substrates. The performance of the TFTs on this clear plastic substrate is as good as that of TFTs made on glass substrates at the same temperature. In contrast to previous work on high temperature plastic substrates, the substrates were freestanding and not mounted to rigid substrates for fabrication, which is critical for maintaining a clean and clear back surface for the optical devices (e.g. OLEDs). These results will enable AMOLED displays on clear plastic substrates.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367863
Yuyuan Tian, Bingqian Xu, X. Xiao
We have developed a method to determine the conductance of single molecules covalently bonded to gold electrodes by repeatedly forming a large number of molecular junctions. We create each molecular junction by separating two Au electrodes from contact in a solution containing the sample molecules. During the separation, we simultaneously measure the conductance and the force between the two electrodes. The conductance decreases in discrete steps, corresponding to the breakdown of individual molecules covalently bonded to the electrodes. Each discrete drop in the conductance is accompanied by a discrete drop in the force, which allows us to determine the bonding strength of the molecule to the electrodes. We have also determined the effective spring constant of a single molecule and the dependence of the conductance on the applied force.
{"title":"Measurement of electron transport and mechanical properties of single molecules","authors":"Yuyuan Tian, Bingqian Xu, X. Xiao","doi":"10.1109/DRC.2004.1367863","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367863","url":null,"abstract":"We have developed a method to determine the conductance of single molecules covalently bonded to gold electrodes by repeatedly forming a large number of molecular junctions. We create each molecular junction by separating two Au electrodes from contact in a solution containing the sample molecules. During the separation, we simultaneously measure the conductance and the force between the two electrodes. The conductance decreases in discrete steps, corresponding to the breakdown of individual molecules covalently bonded to the electrodes. Each discrete drop in the conductance is accompanied by a discrete drop in the force, which allows us to determine the bonding strength of the molecule to the electrodes. We have also determined the effective spring constant of a single molecule and the dependence of the conductance on the applied force.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115641174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367804
Yuh‐Renn Wu, J. Singh
It is well known that polar oxides such as BaTiO/sub 3/ and LiNbO/sub 3/ have extremely large piezoelectric and pyroelectric effects which make them highly suitable for sensor application. Semiconductors on the other hand have poor piezoelectric and pyroelectric effects but have their abilities to show large change in conductivity with small bias. In this paper we examine the potential of devices based on heterostructures made from highly polar materials and semiconductors. Such functional devices have superior sensor properties as well as transistor properties. The basis device examined is based on the use of a thin oxide with high piezoelectric coefficients or pyroelectric coefficients under the gate region. Channel charge and current are directly controlled by gate voltage (normal FET), temperature (thermal sensor), or stress (stress sensor). We examine the performance of three classes of heterostructures that form the basis of important semiconductor technologies: (i) Si/SiO/sub 2//BaTiO/sub 3/ heterostructure junctions that would be an important breakthrough for silicon sensor technology; (ii) GaN/AlN/BaTiO/sub 3/ heterostructure junctions that would be important especially in high temperature sensor application; and (iii) GaAs/AlGaAs/BaTiO/sub 3/ heterostructure field effect transistors.
{"title":"Polar heterostructure for multi-function devices: theoretical studies","authors":"Yuh‐Renn Wu, J. Singh","doi":"10.1109/DRC.2004.1367804","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367804","url":null,"abstract":"It is well known that polar oxides such as BaTiO/sub 3/ and LiNbO/sub 3/ have extremely large piezoelectric and pyroelectric effects which make them highly suitable for sensor application. Semiconductors on the other hand have poor piezoelectric and pyroelectric effects but have their abilities to show large change in conductivity with small bias. In this paper we examine the potential of devices based on heterostructures made from highly polar materials and semiconductors. Such functional devices have superior sensor properties as well as transistor properties. The basis device examined is based on the use of a thin oxide with high piezoelectric coefficients or pyroelectric coefficients under the gate region. Channel charge and current are directly controlled by gate voltage (normal FET), temperature (thermal sensor), or stress (stress sensor). We examine the performance of three classes of heterostructures that form the basis of important semiconductor technologies: (i) Si/SiO/sub 2//BaTiO/sub 3/ heterostructure junctions that would be an important breakthrough for silicon sensor technology; (ii) GaN/AlN/BaTiO/sub 3/ heterostructure junctions that would be important especially in high temperature sensor application; and (iii) GaAs/AlGaAs/BaTiO/sub 3/ heterostructure field effect transistors.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116726952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367783
T. Khan, D. Vasileska, T. Thornton
Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. Alternate device structures are needed that will satisfy both the low-power and RF requirements and will allow much better operation of, for example, pacemakers. A candidate structure is the SOI-MESFET that is currently being fabricated and theoretically characterized within our Nanostructures Research Group at Arizona State University. Since the mobility is the key factor in determining the device cut-off frequency, it is the purpose of this study to investigate the electron mobility improvement of SOI MESFET when compared to SOI and conventional MOSFET devices. To accomplish this goal, we have utilized our in-house Ensemble Monte Carlo device simulator and performed extensive simulations of similar geometry SOI MOSFETs and Si MESFET channels.
{"title":"Study of subthreshold electron mobility behavior in SOI-MESFETs","authors":"T. Khan, D. Vasileska, T. Thornton","doi":"10.1109/DRC.2004.1367783","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367783","url":null,"abstract":"Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. Alternate device structures are needed that will satisfy both the low-power and RF requirements and will allow much better operation of, for example, pacemakers. A candidate structure is the SOI-MESFET that is currently being fabricated and theoretically characterized within our Nanostructures Research Group at Arizona State University. Since the mobility is the key factor in determining the device cut-off frequency, it is the purpose of this study to investigate the electron mobility improvement of SOI MESFET when compared to SOI and conventional MOSFET devices. To accomplish this goal, we have utilized our in-house Ensemble Monte Carlo device simulator and performed extensive simulations of similar geometry SOI MOSFETs and Si MESFET channels.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367765
Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee
In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.
{"title":"Impact of reducing RTA temperature on sub-10nm ultra-thin body SOI","authors":"Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee","doi":"10.1109/DRC.2004.1367765","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367765","url":null,"abstract":"In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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