Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367877
W. Wong, R. Lujan, S. Ready, M. Chabinyc, A. Arias, R. Street
This work presents a novel digital-lithographic method, in which an electronically generated and digitally aligned etch mask is jet-printed onto a process surface. This method was used to fabricate hydrogenated amorphous silicon thin-film transistor (TFT) arrays. The digital lithographically fabricated arrays had features as small a 40 μm with 5 μm layer-to-layer registration and pixel resolution of 75 dpi over a four-inch diameter wafer. The resulting TFTs, with on/off ratios of 108 and threshold voltages of 2-3 V were then integrated with a-Si sensor media for an image sensor. The image sensor was operated as an X-ray and light detector.
{"title":"Digital lithography for thin-film transistor fabrication","authors":"W. Wong, R. Lujan, S. Ready, M. Chabinyc, A. Arias, R. Street","doi":"10.1109/DRC.2004.1367877","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367877","url":null,"abstract":"This work presents a novel digital-lithographic method, in which an electronically generated and digitally aligned etch mask is jet-printed onto a process surface. This method was used to fabricate hydrogenated amorphous silicon thin-film transistor (TFT) arrays. The digital lithographically fabricated arrays had features as small a 40 μm with 5 μm layer-to-layer registration and pixel resolution of 75 dpi over a four-inch diameter wafer. The resulting TFTs, with on/off ratios of 108 and threshold voltages of 2-3 V were then integrated with a-Si sensor media for an image sensor. The image sensor was operated as an X-ray and light detector.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121100230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367827
A. Matulionis
The cutoff frequency of a transistor is determined mainly by gate length and electron drift velocity. In general, the velocity reaches high values in a two-dimensional electron gas channel (2DEG). Thus, a high electron mobility transistor (HEMT) with a 2DEG channel can operate at frequencies corresponding to short millimeter waves. Though the highest values of drift velocity are similar for electrons in nitride and arsenide 2DEG channels, the frequency performance of an arsenide HEMT is superior, as compared with nitride HEMTs. However, it is not straightforward to see why hot phonons do not limit drift velocity in arsenide 2DEG channels and, in this paper, a comparative analysis of hot-phonon effects in AlInAs/GaInAs/AlInAs/InP, AlGaN/GaN and AlGaN/AlN/GaN channels is carried out.
{"title":"Comparative analysis of hot-phonon effects in nitride and arsenide channels for HEMTs","authors":"A. Matulionis","doi":"10.1109/DRC.2004.1367827","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367827","url":null,"abstract":"The cutoff frequency of a transistor is determined mainly by gate length and electron drift velocity. In general, the velocity reaches high values in a two-dimensional electron gas channel (2DEG). Thus, a high electron mobility transistor (HEMT) with a 2DEG channel can operate at frequencies corresponding to short millimeter waves. Though the highest values of drift velocity are similar for electrons in nitride and arsenide 2DEG channels, the frequency performance of an arsenide HEMT is superior, as compared with nitride HEMTs. However, it is not straightforward to see why hot phonons do not limit drift velocity in arsenide 2DEG channels and, in this paper, a comparative analysis of hot-phonon effects in AlInAs/GaInAs/AlInAs/InP, AlGaN/GaN and AlGaN/AlN/GaN channels is carried out.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129583256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367791
C. Lai, M. Ma, C.F. Cheng, A. Chin, S. Mcalister, C.X. Zhu, M. Li, D. Kwong
We demonstrate, for the first time, a novel high-/spl kappa/ AlN capacitor that can be program-erasable at voltages of /spl plusmn/4 V and that has good retention for 1T1C memory. These features are not shown by Al/sub 2/O/sub 3/, or other known single high-/spl kappa/ layer capacitors. Good data retention occurs with a threshold change of only 0.06 after /spl plusmn/4 V P/E for 10/sup 4/s and shows potentially long memory time.
{"title":"A novel program-erasable capacitor using high-/spl kappa/ AlN dielectric","authors":"C. Lai, M. Ma, C.F. Cheng, A. Chin, S. Mcalister, C.X. Zhu, M. Li, D. Kwong","doi":"10.1109/DRC.2004.1367791","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367791","url":null,"abstract":"We demonstrate, for the first time, a novel high-/spl kappa/ AlN capacitor that can be program-erasable at voltages of /spl plusmn/4 V and that has good retention for 1T1C memory. These features are not shown by Al/sub 2/O/sub 3/, or other known single high-/spl kappa/ layer capacitors. Good data retention occurs with a threshold change of only 0.06 after /spl plusmn/4 V P/E for 10/sup 4/s and shows potentially long memory time.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367801
K. Yadavalli, N. R. Anderson, T. Orlova, A. Orlov, G. Snider
The emerging research devices section of the 2003 edition of the semiconductor industry roadmap (ITRS 2003) lists single electron memories as one possible family of devices with the potential to continue the historical scaling trends in the density and performance of semiconductor memories. Furthermore, the ITRS 2003 roadmap calls attention to the introduction of high K gate dielectrics in DRAM's and their future integration into flash memory process. In light of this, a study of the behavior of single electron memory devices utilizing high K dielectrics is essential to clearly understand the potential of these devices in extending the roadmap. In the aluminum tunnel junction based single electron memory cell (K.K. Yadavalli et al., J. Vac. Sci. B vol. 21, 2860, 2003), the memory node is an aluminum floating gate closely coupled with the single electron transistor used as a readout device. We have developed a process for the fabrication of Al/sub 2/O/sub 3/ tunnel junctions with precise physical and electrical properties using plasma oxidation of aluminum.
{"title":"A floating gate single electron memory device with Al/sub 2/O/sub 3/ tunnel barriers","authors":"K. Yadavalli, N. R. Anderson, T. Orlova, A. Orlov, G. Snider","doi":"10.1109/DRC.2004.1367801","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367801","url":null,"abstract":"The emerging research devices section of the 2003 edition of the semiconductor industry roadmap (ITRS 2003) lists single electron memories as one possible family of devices with the potential to continue the historical scaling trends in the density and performance of semiconductor memories. Furthermore, the ITRS 2003 roadmap calls attention to the introduction of high K gate dielectrics in DRAM's and their future integration into flash memory process. In light of this, a study of the behavior of single electron memory devices utilizing high K dielectrics is essential to clearly understand the potential of these devices in extending the roadmap. In the aluminum tunnel junction based single electron memory cell (K.K. Yadavalli et al., J. Vac. Sci. B vol. 21, 2860, 2003), the memory node is an aluminum floating gate closely coupled with the single electron transistor used as a readout device. We have developed a process for the fabrication of Al/sub 2/O/sub 3/ tunnel junctions with precise physical and electrical properties using plasma oxidation of aluminum.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131183318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367775
C. Sanabria, Hongtao Xu, Tomas Palacios, P. Chakraborty, S. Heikman, Umesh K. Mishra, R. A. York
In this work, we cover four topics. Three studies are presented on the effect of different epilayer structures on the noise figure of AlGaN/GaN HEMTs in the 4-12 GHz frequency range. The material studies include varying aluminum composition in the barrier, sapphire vs. SiC substrates, and, for the first time, the influence of a thin AlN layer on the noise parameters; all three against frequency and drain current. In addition is a comparison of two equivalent circuit models at 5 GHz.
{"title":"Influence of the heterostructure design on noise figure of AlGaN/GaN HEMTs","authors":"C. Sanabria, Hongtao Xu, Tomas Palacios, P. Chakraborty, S. Heikman, Umesh K. Mishra, R. A. York","doi":"10.1109/DRC.2004.1367775","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367775","url":null,"abstract":"In this work, we cover four topics. Three studies are presented on the effect of different epilayer structures on the noise figure of AlGaN/GaN HEMTs in the 4-12 GHz frequency range. The material studies include varying aluminum composition in the barrier, sapphire vs. SiC substrates, and, for the first time, the influence of a thin AlN layer on the noise parameters; all three against frequency and drain current. In addition is a comparison of two equivalent circuit models at 5 GHz.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133836918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367824
T. Kamimura, C. Hyon, A. Kojima, M. Maeda, K. Matsumoto
In this paper, we have succeeded in observing the coexistence of the Coulomb charging effect and the coherent transport of holes in a carbon nanotube of length 4.5 /spl mu/m at 8.6 K. A back gate type carbon nanotube field effect transistor was fabricated for this purpose. The drain current-gate voltage characteristics, Coulomb diamond characteristics, and periodic negative differential conductance were measured. Results confirm the coexistence of the Coulomb charging effect and ballistic transport of the holes in semiconductive carbon nanotubes.
本文成功地观察了长度为4.5 /spl μ m /m的碳纳米管在8.6 K下库仑电荷效应和空穴相干输运的共存。为此制备了一种后栅型碳纳米管场效应晶体管。测量了漏极电流-栅极电压特性、库仑金刚石特性和周期负差分电导。结果证实了半导体碳纳米管中空穴的库仑电荷效应和弹道输运共存。
{"title":"Coherent transport of hole in p type semiconductive carbon nanotube","authors":"T. Kamimura, C. Hyon, A. Kojima, M. Maeda, K. Matsumoto","doi":"10.1109/DRC.2004.1367824","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367824","url":null,"abstract":"In this paper, we have succeeded in observing the coexistence of the Coulomb charging effect and the coherent transport of holes in a carbon nanotube of length 4.5 /spl mu/m at 8.6 K. A back gate type carbon nanotube field effect transistor was fabricated for this purpose. The drain current-gate voltage characteristics, Coulomb diamond characteristics, and periodic negative differential conductance were measured. Results confirm the coexistence of the Coulomb charging effect and ballistic transport of the holes in semiconductive carbon nanotubes.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134194391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367787
Daehyun Kim, Kangil Lee, Jaehak Lee, K. Seo
A new two-step recess (TSR) technology was successfully demonstrated using SiN/sub x/ passivation and Pt-buried gate process. Applying the developed two-step recess (TSR) process to the fabrication of 0.15 /spl mu/m Al/sub 0.6/InAs/In/sub 0.65/GaAs HEMTs, remarkable improvements could be obtained such as the suppression of the kink effect, and the increase of G/sub m,max/, f/sub T/ and f/sub max/. Since the side-recessed region was fully passivated by SiN/sub x/ dielectric layer, this TSR technology is also to offer additional advantage of good reliability.
{"title":"A new two-step recess technology using SiN/sub x/ passivation and Pt-buried gate process and its application to 0.15 /spl mu/m Al/sub 0.6/InAs/In/sub 0.65/GaAs HEMTs","authors":"Daehyun Kim, Kangil Lee, Jaehak Lee, K. Seo","doi":"10.1109/DRC.2004.1367787","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367787","url":null,"abstract":"A new two-step recess (TSR) technology was successfully demonstrated using SiN/sub x/ passivation and Pt-buried gate process. Applying the developed two-step recess (TSR) process to the fabrication of 0.15 /spl mu/m Al/sub 0.6/InAs/In/sub 0.65/GaAs HEMTs, remarkable improvements could be obtained such as the suppression of the kink effect, and the increase of G/sub m,max/, f/sub T/ and f/sub max/. Since the side-recessed region was fully passivated by SiN/sub x/ dielectric layer, this TSR technology is also to offer additional advantage of good reliability.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132345089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367809
B. Paul, K. Roy
In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.
{"title":"Device optimization for digital sub-threshold operation","authors":"B. Paul, K. Roy","doi":"10.1109/DRC.2004.1367809","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367809","url":null,"abstract":"In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367831
M. Bergmann, T. Kuhr, K. Haberem, C. Hussell, A. Abare, D. Emerson
AlGaInN-based ultraviolet (UV) light emitters have recently become the focus of intense research since semiconductor UV optical sources offer the potential of low cost, small size, low power, and high reliability. In this paper, we summarize critical elements for optimizing LED and LD performance in the sub-390 nm range. Lifetime results on both LEDs and LDs are discussed along with issues concerning further increasing the lifetime of these short wavelength devices, increasing their efficiency, and pushing emission wavelength even shorter.
{"title":"Materials and device developments for ultraviolet LEDs and laser diodes","authors":"M. Bergmann, T. Kuhr, K. Haberem, C. Hussell, A. Abare, D. Emerson","doi":"10.1109/DRC.2004.1367831","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367831","url":null,"abstract":"AlGaInN-based ultraviolet (UV) light emitters have recently become the focus of intense research since semiconductor UV optical sources offer the potential of low cost, small size, low power, and high reliability. In this paper, we summarize critical elements for optimizing LED and LD performance in the sub-390 nm range. Lifetime results on both LEDs and LDs are discussed along with issues concerning further increasing the lifetime of these short wavelength devices, increasing their efficiency, and pushing emission wavelength even shorter.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114734629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367814
Lisong Zhou, T. Jackson, E. Brandon, W. West
We have fabricated hydrogenated amorphous silicon (a-Si:H) TFTs on Kapton/sup (R)/ polyimide flexible substrates and characterized their response to deployment-like mechanical stresses and to radiation exposure. To maintain substrate flatness and provide improved thermal transfer during fabrication, we used a pressure-sensitive silicone gel adhesive layer to mount Kapton/sup (R)/ substrates onto glass carriers. The test results, presented in this paper, are encouraging for space use of a-Si:H TFTs on polymeric substrates. Device function was retained even after 1 Mrad fast electron irradiation, and irradiation-induced device changes were removed by low-temperature thermal annealing. Although some TFTs were destroyed by substrate stressing, the majority survived with only small changes, suggesting that care in device design and placement may reduce or eliminate this problem.
{"title":"Flexible substrate a-Si:H TFTs for space applications","authors":"Lisong Zhou, T. Jackson, E. Brandon, W. West","doi":"10.1109/DRC.2004.1367814","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367814","url":null,"abstract":"We have fabricated hydrogenated amorphous silicon (a-Si:H) TFTs on Kapton/sup (R)/ polyimide flexible substrates and characterized their response to deployment-like mechanical stresses and to radiation exposure. To maintain substrate flatness and provide improved thermal transfer during fabrication, we used a pressure-sensitive silicone gel adhesive layer to mount Kapton/sup (R)/ substrates onto glass carriers. The test results, presented in this paper, are encouraging for space use of a-Si:H TFTs on polymeric substrates. Device function was retained even after 1 Mrad fast electron irradiation, and irradiation-induced device changes were removed by low-temperature thermal annealing. Although some TFTs were destroyed by substrate stressing, the majority survived with only small changes, suggesting that care in device design and placement may reduce or eliminate this problem.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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