Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367762
N. Wu, Qingchun Zhang, Chunxiang Zhu, D. Chan, M. Li, N. Balasubramanian, A. Du, A. Chin, J. Sin, D. Kwong
This work presents a novel surface passivation process for HfO/sub 2/ Ge MOSFETs which we have developed, using in-situ SiH/sub 4/ treatment prior to HfO/sub 2/ deposition. Results show that, compared to conventional surface nitridation, TaN/HfO/sub 2//Ge pMOSFETs with in-situ SiH/sub 4/ surface treatment have much reduced frequency dispersion and hysteresis, improved gate leakage distribution, better subthreshold swing and higher hole mobility.
{"title":"A novel surface passivation process for HfO/sub 2/ Ge MOSFETs","authors":"N. Wu, Qingchun Zhang, Chunxiang Zhu, D. Chan, M. Li, N. Balasubramanian, A. Du, A. Chin, J. Sin, D. Kwong","doi":"10.1109/DRC.2004.1367762","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367762","url":null,"abstract":"This work presents a novel surface passivation process for HfO/sub 2/ Ge MOSFETs which we have developed, using in-situ SiH/sub 4/ treatment prior to HfO/sub 2/ deposition. Results show that, compared to conventional surface nitridation, TaN/HfO/sub 2//Ge pMOSFETs with in-situ SiH/sub 4/ surface treatment have much reduced frequency dispersion and hysteresis, improved gate leakage distribution, better subthreshold swing and higher hole mobility.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127992840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367759
S. Banerjee, D. Kim, T. Kim, L. Weltzer, Y. Liu, S. Tang, M. Palard
This work presents the use of SiGe nanoparticle floating gates on high-k gate tunneling dielectrics, which, along with SiGe cold cathodes in the channel, are ways to enhance the low voltage/power operation of flash cells, improve the speed and charge retention. Control of dot sizes and spatial distributions may be improved by templated growth. Instead of an array of nanoparticles, it is also possible to use single quantum dots, and exploit Coulomb blockade and multi-level storage in single electron/few electron charge memories, but such devices are susceptible to background charges. It is possible to envision vertical cell structures in a cross-point array at the intersections of the wordlines and bitlines, which can result in an ideal 4F/sup 2/ architecture.
{"title":"Nanoparticle floating gate flash memories","authors":"S. Banerjee, D. Kim, T. Kim, L. Weltzer, Y. Liu, S. Tang, M. Palard","doi":"10.1109/DRC.2004.1367759","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367759","url":null,"abstract":"This work presents the use of SiGe nanoparticle floating gates on high-k gate tunneling dielectrics, which, along with SiGe cold cathodes in the channel, are ways to enhance the low voltage/power operation of flash cells, improve the speed and charge retention. Control of dot sizes and spatial distributions may be improved by templated growth. Instead of an array of nanoparticles, it is also possible to use single quantum dots, and exploit Coulomb blockade and multi-level storage in single electron/few electron charge memories, but such devices are susceptible to background charges. It is possible to envision vertical cell structures in a cross-point array at the intersections of the wordlines and bitlines, which can result in an ideal 4F/sup 2/ architecture.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128665258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367783
T. Khan, D. Vasileska, T. Thornton
Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. Alternate device structures are needed that will satisfy both the low-power and RF requirements and will allow much better operation of, for example, pacemakers. A candidate structure is the SOI-MESFET that is currently being fabricated and theoretically characterized within our Nanostructures Research Group at Arizona State University. Since the mobility is the key factor in determining the device cut-off frequency, it is the purpose of this study to investigate the electron mobility improvement of SOI MESFET when compared to SOI and conventional MOSFET devices. To accomplish this goal, we have utilized our in-house Ensemble Monte Carlo device simulator and performed extensive simulations of similar geometry SOI MOSFETs and Si MESFET channels.
{"title":"Study of subthreshold electron mobility behavior in SOI-MESFETs","authors":"T. Khan, D. Vasileska, T. Thornton","doi":"10.1109/DRC.2004.1367783","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367783","url":null,"abstract":"Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. Alternate device structures are needed that will satisfy both the low-power and RF requirements and will allow much better operation of, for example, pacemakers. A candidate structure is the SOI-MESFET that is currently being fabricated and theoretically characterized within our Nanostructures Research Group at Arizona State University. Since the mobility is the key factor in determining the device cut-off frequency, it is the purpose of this study to investigate the electron mobility improvement of SOI MESFET when compared to SOI and conventional MOSFET devices. To accomplish this goal, we have utilized our in-house Ensemble Monte Carlo device simulator and performed extensive simulations of similar geometry SOI MOSFETs and Si MESFET channels.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367765
Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee
In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.
{"title":"Impact of reducing RTA temperature on sub-10nm ultra-thin body SOI","authors":"Jong-Heon Yang, Jihun Oh, W. Cho, C. Ahn, K. Im, I. Baek, J. Park, Seongjae Lee","doi":"10.1109/DRC.2004.1367765","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367765","url":null,"abstract":"In this work, we fabricated sub-10 nm UTB SOI and investigated its properties by using plasma doping (PLAD) and rapid thermal annealing (RTA). It is shown, for the first time, that electrical properties and device scalability of the sub-10 nm thin body were improved with reduced RTA temperature. In scaling down, SOI thickness decreases, but also RTA temperature scaling should be considered. RTA temperature is directly connected to the suppression of the short-channel effect and also it gives more chance for device scalability, especially for sub-20 nm SOI devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367872
K. Kim, Hyun Ho Kim, Ki-Whan Song, J. Huh, J. Lee, Byung-Gook Park
We have previously reported the controllable complementary n- and p-type negative-differential transconductance (NDT) characteristics of a FIBTET (field-induced band-to-band tunneling effect transistor) on a degenerately doped SOI MOSFET. In this work, we investigate key parameters of device design and demonstrate negative-differential conductance (NDC) as well as NDT characteristics in FIBTETs, which have a structure totally compatible with SOI MOSFETs. the critical dose condition distinguishing FIBTET from MOSFET has been found and room temperature NDC as well as NDT was demonstrated in a SOI MOSFET compatible tunnel device. The NDC combined with NDT characteristics of FIBTETs will give room for various analog and digital circuit applications based on Si technology.
{"title":"SOI MOSFET-based quantum tunneling device - FIBTET","authors":"K. Kim, Hyun Ho Kim, Ki-Whan Song, J. Huh, J. Lee, Byung-Gook Park","doi":"10.1109/DRC.2004.1367872","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367872","url":null,"abstract":"We have previously reported the controllable complementary n- and p-type negative-differential transconductance (NDT) characteristics of a FIBTET (field-induced band-to-band tunneling effect transistor) on a degenerately doped SOI MOSFET. In this work, we investigate key parameters of device design and demonstrate negative-differential conductance (NDC) as well as NDT characteristics in FIBTETs, which have a structure totally compatible with SOI MOSFETs. the critical dose condition distinguishing FIBTET from MOSFET has been found and room temperature NDC as well as NDT was demonstrated in a SOI MOSFET compatible tunnel device. The NDC combined with NDT characteristics of FIBTETs will give room for various analog and digital circuit applications based on Si technology.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"739 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367828
M. Singh, Yuh‐Renn Wu, J. Singh
Monte Carlo simulation of AlGaN/GaN HEMTs were carried out and compared with GaAs based devices. The following outcomes of our simulations are noteworthy: i) partially due to the relatively heavy electron effective mass in GaN, the velocities of the electrons are mostly below the steady state values through most of the channel; ii) unlike what is observed in GaAs based short channel devices, there is no pronounced overshoot effect, even at high drain source biases, due to increased scattering; iii) our simulations show that the suppression of overshoot is directly related to the length of the high field region. This length is quite small for usual bias conditions. We suggest that a non-uniform composition of the barrier region could conceivably help in spreading out the high field region, which is present at the drain end of the device. Other results of the Monte Carlo simulation include transconductance, noise information and unity current gain frequency.
{"title":"Velocity overshoot effects and transit times in III-V nitride HFETs : a Monte Carlo study","authors":"M. Singh, Yuh‐Renn Wu, J. Singh","doi":"10.1109/DRC.2004.1367828","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367828","url":null,"abstract":"Monte Carlo simulation of AlGaN/GaN HEMTs were carried out and compared with GaAs based devices. The following outcomes of our simulations are noteworthy: i) partially due to the relatively heavy electron effective mass in GaN, the velocities of the electrons are mostly below the steady state values through most of the channel; ii) unlike what is observed in GaAs based short channel devices, there is no pronounced overshoot effect, even at high drain source biases, due to increased scattering; iii) our simulations show that the suppression of overshoot is directly related to the length of the high field region. This length is quite small for usual bias conditions. We suggest that a non-uniform composition of the barrier region could conceivably help in spreading out the high field region, which is present at the drain end of the device. Other results of the Monte Carlo simulation include transconductance, noise information and unity current gain frequency.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127769337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367885
Yun Wei, D. Scott, Yingda Dong, A. Gossard, M. Rodwell
We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) with a 0.3 /spl mu/m/spl times/4 /spl mu/m regrown base-emitter junction. The HBT exhibits a 280 GHz current gain cutoff frequency (f/sub /spl tau//) and 148 GHz power gain cutoff frequency (f/sub max/). This DHBT was fabricated in a molecular beam epitaxy (MBE) regrown-emitter technology and has the highest f/sub /spl tau// yet reported for a III-V regrown-emitter HBT. The device has V/sub CE.sat/<0.9 V even at J/sub E/=11 mA //spl mu/m/sup 2/, peak AC current gain h/sub 21/=30, and collector breakdown voltage V/sub CEO/=5 V. In this technology, the area of base-emitter junction has been scaled to as small as 1.2 /spl mu/m/sup 2/ while a larger-area extrinsic emitter contact maintains a low 11 /spl Omega/ emitter access resistance.
{"title":"280 GHz f/sub T/ InP DHBT with 1.2 /spl mu/m/sup 2/ base-emitter junction area in MBE regrown-emitter technology","authors":"Yun Wei, D. Scott, Yingda Dong, A. Gossard, M. Rodwell","doi":"10.1109/DRC.2004.1367885","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367885","url":null,"abstract":"We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) with a 0.3 /spl mu/m/spl times/4 /spl mu/m regrown base-emitter junction. The HBT exhibits a 280 GHz current gain cutoff frequency (f/sub /spl tau//) and 148 GHz power gain cutoff frequency (f/sub max/). This DHBT was fabricated in a molecular beam epitaxy (MBE) regrown-emitter technology and has the highest f/sub /spl tau// yet reported for a III-V regrown-emitter HBT. The device has V/sub CE.sat/<0.9 V even at J/sub E/=11 mA //spl mu/m/sup 2/, peak AC current gain h/sub 21/=30, and collector breakdown voltage V/sub CEO/=5 V. In this technology, the area of base-emitter junction has been scaled to as small as 1.2 /spl mu/m/sup 2/ while a larger-area extrinsic emitter contact maintains a low 11 /spl Omega/ emitter access resistance.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367847
J. Meteer, S. Eikenberry, J. Huffman, E. Kan
Si/SiGe quantum well (QW) impact diodes are demonstrated with multiplication up to 200 at 10 V reverse bias between 10-150 K. These diodes are ideal gain structures for use with Si impurity band conduction (IBC) infrared detectors, due to the available integration platform, appropriate low temperature characteristics, low voltage operation, and low noise multiplication mechanism as required for compatibility with mid- and far infrared detection. Physical characterization, including composition and doping profiles, are obtained from STEM and SIMS analyses. Photocurrent multiplication is measured to confirm our device design.
{"title":"A low-temperature Si/SiGe impact diode for improved infrared sensing","authors":"J. Meteer, S. Eikenberry, J. Huffman, E. Kan","doi":"10.1109/DRC.2004.1367847","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367847","url":null,"abstract":"Si/SiGe quantum well (QW) impact diodes are demonstrated with multiplication up to 200 at 10 V reverse bias between 10-150 K. These diodes are ideal gain structures for use with Si impurity band conduction (IBC) infrared detectors, due to the available integration platform, appropriate low temperature characteristics, low voltage operation, and low noise multiplication mechanism as required for compatibility with mid- and far infrared detection. Physical characterization, including composition and doping profiles, are obtained from STEM and SIMS analyses. Photocurrent multiplication is measured to confirm our device design.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"617 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126902095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367772
H. Yu, L. McCarthy, S. Rajan, S. Keller, S. Denbaars, J. Speck, U. Mishra
We report on the use of Si ion implantation for the fabrication of AlGaN/GaN HEMTs with an as-deposited ohmic contact resistance of 0.4 /spl Omega/mm. Currently ohmic contact technology requires a high temperature (/spl sim/870/spl deg/C) alloying step. The resulting contacts have an irregular shape and surface that can create difficulties in device reproducibility, reliability and yield, particularly for large periphery devices. The use of ion implantation to enable unalloyed ohmic contacts has the potential to reduce these obstacles to the manufacturability of AlGaN/GaN HEMTs. Using ion implantation also has the potential to reduce access resistance by reducing ohmic contact resistance and gate-source spacing, to eliminate the need for etched device isolation, and to enable sophisticated device designs that take advantage of lateral dopant engineering.
{"title":"Ion implantation for unalloyed ohmic contacts to AlGaN/GaN HEMTs","authors":"H. Yu, L. McCarthy, S. Rajan, S. Keller, S. Denbaars, J. Speck, U. Mishra","doi":"10.1109/DRC.2004.1367772","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367772","url":null,"abstract":"We report on the use of Si ion implantation for the fabrication of AlGaN/GaN HEMTs with an as-deposited ohmic contact resistance of 0.4 /spl Omega/mm. Currently ohmic contact technology requires a high temperature (/spl sim/870/spl deg/C) alloying step. The resulting contacts have an irregular shape and surface that can create difficulties in device reproducibility, reliability and yield, particularly for large periphery devices. The use of ion implantation to enable unalloyed ohmic contacts has the potential to reduce these obstacles to the manufacturability of AlGaN/GaN HEMTs. Using ion implantation also has the potential to reduce access resistance by reducing ohmic contact resistance and gate-source spacing, to eliminate the need for etched device isolation, and to enable sophisticated device designs that take advantage of lateral dopant engineering.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126336036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367887
P. Chahal, F. Morris, G. Frazier
InAlAs/AlAs based RTDs with a peak current density over 500 kA/cm/sup 2/ have been designed and fabricated. Relaxation oscillator circuits for 20 and 50 GHz were designed using these 0.6 /spl mu/m/sup 2/ RTDs. They consist of an RTD and a 5 /spl Omega/ resistor placed in a coplanar waveguide (CPW). The measured spectrum of the 20 GHz and 50 GHz oscillators showed only odd harmonics. The measured results of the relaxation oscillators show that they have very low phase noise (low jitter), below -110 dBc/Hz at 1 MHz offset in locked-mode, and can easily be phase locked. RTD based relaxation oscillation can be readily used as clocks in high-speed signal processing applications.
{"title":"50 GHz resonant tunneling diode relaxation oscillator","authors":"P. Chahal, F. Morris, G. Frazier","doi":"10.1109/DRC.2004.1367887","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367887","url":null,"abstract":"InAlAs/AlAs based RTDs with a peak current density over 500 kA/cm/sup 2/ have been designed and fabricated. Relaxation oscillator circuits for 20 and 50 GHz were designed using these 0.6 /spl mu/m/sup 2/ RTDs. They consist of an RTD and a 5 /spl Omega/ resistor placed in a coplanar waveguide (CPW). The measured spectrum of the 20 GHz and 50 GHz oscillators showed only odd harmonics. The measured results of the relaxation oscillators show that they have very low phase noise (low jitter), below -110 dBc/Hz at 1 MHz offset in locked-mode, and can easily be phase locked. RTD based relaxation oscillation can be readily used as clocks in high-speed signal processing applications.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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