Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367784
Niu Jin, Dongmin Liu, Sung-Yong Chung, Ronghua Yu, Wu Lu, P. R. Berger, P. Thompson
In this paper, we present a combined model which unites both the small and large signal models for resonant interband tunneling diodes (RITD) grown on silicon-on-insulator (SOI) substrates. In this combined model, the dependent current source, I/sub j/(V), is from the large signal model while R, and C/sub j/(V) are obtained from the small signal model. The combined model was then implemented using ADS software. A transient simulation was performed to simulate the response of the RITD with a serially connected 50 /spl mu/H inductor to a ramped voltage from 0 V to 1 V in 0.1 ms. The simulation results show strong oscillations when the diode is biased in its negative differential resistance region (NDR) during DC measurements, which would result in the commonly observed plateau in the NDR region, where the needle probe acts as an inductor.
在本文中，我们提出了一个结合小信号和大信号模型的谐振带间隧道二极管(RITD)生长在绝缘体上硅(SOI)衬底上。在该组合模型中，依赖电流源I/sub j/(V)来自大信号模型，R和C/sub j/(V)来自小信号模型。然后利用ADS软件对组合模型进行实现。利用一个50 /spl μ l /H的电感，模拟了RITD在0.1 ms内对从0 V到1 V的斜坡电压的响应。仿真结果表明，在直流测量过程中，当二极管偏置在负差分电阻区(NDR)时，会产生强烈的振荡，这将导致在NDR区出现常见的平台，其中针探头充当电感器。
{"title":"A combined model for Si-based resonant interband tunneling diodes grown on SOI","authors":"Niu Jin, Dongmin Liu, Sung-Yong Chung, Ronghua Yu, Wu Lu, P. R. Berger, P. Thompson","doi":"10.1109/DRC.2004.1367784","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367784","url":null,"abstract":"In this paper, we present a combined model which unites both the small and large signal models for resonant interband tunneling diodes (RITD) grown on silicon-on-insulator (SOI) substrates. In this combined model, the dependent current source, I/sub j/(V), is from the large signal model while R, and C/sub j/(V) are obtained from the small signal model. The combined model was then implemented using ADS software. A transient simulation was performed to simulate the response of the RITD with a serially connected 50 /spl mu/H inductor to a ramped voltage from 0 V to 1 V in 0.1 ms. The simulation results show strong oscillations when the diode is biased in its negative differential resistance region (NDR) during DC measurements, which would result in the commonly observed plateau in the NDR region, where the needle probe acts as an inductor.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128786904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367803
S. Rhee, C. Kang, Young Hee Kim, C. Kang, Hag-ju Cho, R. Choi, C. Choi, M. Akbar, J.C. Lee
Threshold voltage instability characteristics of high-k HfO/sub 2/ with SiON interface NMOSFETs under three different dynamic stress conditions, positive, negative, and bipolar stress, have been investigated for the first time. Frequency and duty cycle dependencies have been observed in all three conditions. In contrast to positive AC stress, negative dynamic stress showed decrease in the threshold voltage. Bipolar stress resulted in the highest threshold voltage shift, but the degradation in transconductance and subthreshold swing was actually smaller in comparison to those in negative unipolar stress. A plausible mechanism has been proposed.
{"title":"Threshold voltage instability of ultra-thin HfO/sub 2/ NMOSFETs: characteristics of polarity dependences","authors":"S. Rhee, C. Kang, Young Hee Kim, C. Kang, Hag-ju Cho, R. Choi, C. Choi, M. Akbar, J.C. Lee","doi":"10.1109/DRC.2004.1367803","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367803","url":null,"abstract":"Threshold voltage instability characteristics of high-k HfO/sub 2/ with SiON interface NMOSFETs under three different dynamic stress conditions, positive, negative, and bipolar stress, have been investigated for the first time. Frequency and duty cycle dependencies have been observed in all three conditions. In contrast to positive AC stress, negative dynamic stress showed decrease in the threshold voltage. Bipolar stress resulted in the highest threshold voltage shift, but the degradation in transconductance and subthreshold swing was actually smaller in comparison to those in negative unipolar stress. A plausible mechanism has been proposed.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367811
S.S. Ahmed, D. Vasileska
The ultimate limits in scaling of conventional MOSFET devices have led the researchers to look for novel device concepts such as dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. However, a lot of the old issues still remain and new issues begin to appear. For example, in both dual-gate SOI MOSFETs and in FinFET devices, quantum mechanical size-quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in the device parameters, and the electron-electron interactions affect the thermalization of the carriers at the drain end of the device. In this work, we investigate the influence of these relatively new and challenging issues on the operation of a narrow-width SOI device structure.
{"title":"Modeling of narrow-width SOI devices: the impact of quantum mechanical size quantization effects and unintentional doping on device operation","authors":"S.S. Ahmed, D. Vasileska","doi":"10.1109/DRC.2004.1367811","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367811","url":null,"abstract":"The ultimate limits in scaling of conventional MOSFET devices have led the researchers to look for novel device concepts such as dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. However, a lot of the old issues still remain and new issues begin to appear. For example, in both dual-gate SOI MOSFETs and in FinFET devices, quantum mechanical size-quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in the device parameters, and the electron-electron interactions affect the thermalization of the carriers at the drain end of the device. In this work, we investigate the influence of these relatively new and challenging issues on the operation of a narrow-width SOI device structure.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"71 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121811179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367766
Yan Yan, Jialin Zhao, Qingmin Liu, Wei Zhao, A. Seabaugh
We demonstrate for the first time vertical tunnel diodes formed by rapid thermal diffusion using spin-on diffusants on high resistivity (100) Si substrates, 1000-5000 /spl Omega/ cm, 100 mm, allowing the extraction of an RF device model. The simple process flow is compatible with techniques found in any commercial front end. The device model is extracted from DC, microwave frequency S-parameter, and RF impedance measurements. The tunnel diode characteristics are well described by the Schulman-Broekaert analytic model, developed for the resonant tunneling diode, and therefore fit readily into SPICE and ADS modeling environments.
我们首次展示了利用自旋扩散剂在高电阻率(100)Si衬底(1000-5000 /spl ω / cm, 100 mm)上通过快速热扩散形成的垂直隧道二极管，从而可以提取射频器件模型。简单的流程流与任何商业前端中的技术兼容。从直流、微波频率s参数和射频阻抗测量中提取器件模型。隧道二极管的特性很好地描述了Schulman-Broekaert分析模型，该模型是为谐振隧道二极管开发的，因此很容易适用于SPICE和ADS建模环境。
{"title":"Vertical tunnel diodes on high resistivity silicon","authors":"Yan Yan, Jialin Zhao, Qingmin Liu, Wei Zhao, A. Seabaugh","doi":"10.1109/DRC.2004.1367766","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367766","url":null,"abstract":"We demonstrate for the first time vertical tunnel diodes formed by rapid thermal diffusion using spin-on diffusants on high resistivity (100) Si substrates, 1000-5000 /spl Omega/ cm, 100 mm, allowing the extraction of an RF device model. The simple process flow is compatible with techniques found in any commercial front end. The device model is extracted from DC, microwave frequency S-parameter, and RF impedance measurements. The tunnel diode characteristics are well described by the Schulman-Broekaert analytic model, developed for the resonant tunneling diode, and therefore fit readily into SPICE and ADS modeling environments.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130733389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367763
D. S. Yu, A. Chin, B. Hung, W. Chen, C.X. Zhu, M. Li, S. Y. Zhu, D. Kwong
The main challenges for metal-gate/high-k CMOS are to find dual workfunction gates and robust high-k dielectrics. The low workfunction metal-gate for n-MOS is especially difficult since it reacts with oxygen rapidly and is hard to form a silicide or nitride. We have successfully developed 4.2 and 4.3 eV low workfunction NiSi:Hf and NiTiSi gates that were integrated onto SiO/sub 2//Si, novel high-k LaAlO/sub 3//Si and LaAlO/sub 3//GOI n-MOSFETs. The Hf or TiSi is for low workfunction control and the NiSi is for low resistivity.
{"title":"Low workfunction fully silicided gate on SiO/sub 2//Si and LaAlO/sub 3//GOI n-MOSFETs","authors":"D. S. Yu, A. Chin, B. Hung, W. Chen, C.X. Zhu, M. Li, S. Y. Zhu, D. Kwong","doi":"10.1109/DRC.2004.1367763","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367763","url":null,"abstract":"The main challenges for metal-gate/high-k CMOS are to find dual workfunction gates and robust high-k dielectrics. The low workfunction metal-gate for n-MOS is especially difficult since it reacts with oxygen rapidly and is hard to form a silicide or nitride. We have successfully developed 4.2 and 4.3 eV low workfunction NiSi:Hf and NiTiSi gates that were integrated onto SiO/sub 2//Si, novel high-k LaAlO/sub 3//Si and LaAlO/sub 3//GOI n-MOSFETs. The Hf or TiSi is for low workfunction control and the NiSi is for low resistivity.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129102170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367776
M. Neuburger, T. Zimmermann, P. Benkart, M. Kunze, I. Daumiller, A. Dadgar, A. Krost, E. Kohn
This work presents a technology which has been developed to fabricate free-standing GaN membrane and cantilever structures. First experiments have enabled us to verify the piezo response of these GaN based cantilever structures. Especially, the bulk polarization doping generated in the base layer is a new important contribution. GaN heterostructures grown on 111-oriented Si wafers have been used. Free standing cantilevers and membranes have been fabricated using RIE and ICP dry etching. Cantilevers have been etched from the rear side or from the surface. It is expected that this technology will enable new device concepts based on stress induced pn-junction effects.
{"title":"GaN based piezo sensors","authors":"M. Neuburger, T. Zimmermann, P. Benkart, M. Kunze, I. Daumiller, A. Dadgar, A. Krost, E. Kohn","doi":"10.1109/DRC.2004.1367776","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367776","url":null,"abstract":"This work presents a technology which has been developed to fabricate free-standing GaN membrane and cantilever structures. First experiments have enabled us to verify the piezo response of these GaN based cantilever structures. Especially, the bulk polarization doping generated in the base layer is a new important contribution. GaN heterostructures grown on 111-oriented Si wafers have been used. Free standing cantilevers and membranes have been fabricated using RIE and ICP dry etching. Cantilevers have been etched from the rear side or from the surface. It is expected that this technology will enable new device concepts based on stress induced pn-junction effects.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125565510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367902
R. Tsai, J. B. Boos, B. R. Bennett, M. Lange, R. Grundbacher, C. Namba, P. Liu, J. Lee, M. Barsky, A. Gutierrez
In this paper, we report record AlSb/InAs HEMT high frequency gain performance up to 275 GHz f/sub MAX/. The 0.1-/spl mu/m gate length and 80-/spl mu/m total gate periphery devices exhibited a small-signal available gain of 10 dB at 100 GHz, and extrapolated f/sub T/ and f/sub MAX/ performance of 220 and 275 GHz, respectively, at a drain voltage of 0.5 V and drain current of 27 mA. To the best of our knowledge, this is the highest reported f/sub MAX/ and high-frequency available gain reported for InAs-channel HEMTs. Furthermore, it is first AlSb/InAs HEMT result that has achieved f/sub MAX/ greater than f/sub T/, which clearly demonstrates that this approach is not intrinsically limited in regards to achieving high frequency and high-gain characteristics.
{"title":"275 GHz f/sub MAX/, 220 GHz f/sub T/ AlSb/InAs HEMT technology","authors":"R. Tsai, J. B. Boos, B. R. Bennett, M. Lange, R. Grundbacher, C. Namba, P. Liu, J. Lee, M. Barsky, A. Gutierrez","doi":"10.1109/DRC.2004.1367902","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367902","url":null,"abstract":"In this paper, we report record AlSb/InAs HEMT high frequency gain performance up to 275 GHz f/sub MAX/. The 0.1-/spl mu/m gate length and 80-/spl mu/m total gate periphery devices exhibited a small-signal available gain of 10 dB at 100 GHz, and extrapolated f/sub T/ and f/sub MAX/ performance of 220 and 275 GHz, respectively, at a drain voltage of 0.5 V and drain current of 27 mA. To the best of our knowledge, this is the highest reported f/sub MAX/ and high-frequency available gain reported for InAs-channel HEMTs. Furthermore, it is first AlSb/InAs HEMT result that has achieved f/sub MAX/ greater than f/sub T/, which clearly demonstrates that this approach is not intrinsically limited in regards to achieving high frequency and high-gain characteristics.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125628709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367821
J. Knoch, S. Mantl, Y. Lin, Z. Chen, P. Avouris, J. Appenzeller
In this paper, we present an extended Schottky barrier model that includes two new crucial aspects: i) current injection from the metal contacts into the channel does not occur directly but is mediated by the segment of the nanotube underneath the metal contacts whose density of states (DOS) is altered through the proximity of the metal (referred to in the following as "metal-modified" nanotube segment); and ii) the energy gap of carbon nanotubes with an average diameter of /spl sim/1.4 nm seems to be rather /spl sim/1.2 eV than /spl sim/0.7 eV as typically assumed for these type of tubes. Our simulation allows us for the first time to quantitatively describe subthreshold characteristics of CNFETs over the entire gate voltage range.
{"title":"An extended model for carbon nanotube field-effect transistors","authors":"J. Knoch, S. Mantl, Y. Lin, Z. Chen, P. Avouris, J. Appenzeller","doi":"10.1109/DRC.2004.1367821","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367821","url":null,"abstract":"In this paper, we present an extended Schottky barrier model that includes two new crucial aspects: i) current injection from the metal contacts into the channel does not occur directly but is mediated by the segment of the nanotube underneath the metal contacts whose density of states (DOS) is altered through the proximity of the metal (referred to in the following as \"metal-modified\" nanotube segment); and ii) the energy gap of carbon nanotubes with an average diameter of /spl sim/1.4 nm seems to be rather /spl sim/1.2 eV than /spl sim/0.7 eV as typically assumed for these type of tubes. Our simulation allows us for the first time to quantitatively describe subthreshold characteristics of CNFETs over the entire gate voltage range.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367769
Y. Ando, Y. Okamoto, T. Nakayama, T. Inoue, K. Hataya, H. Miyamoto, M. Senda, K. Hirata, M. Kosaki, N. Shibata, M. Kuzuhara
This work describes high power AlGaN/GaN heterojunction FETs on SiC substrates which we have developed. To our knowledge, Psat values of 203 W and 4 W are the highest ever achieved at 2 GHz and 30 GHz, respectively, for GaN FETs. We believe that GaN FET technology will play a dominant role in future base station systems.
{"title":"High power AlGaN/GaN heterojunction FETs for base station applications","authors":"Y. Ando, Y. Okamoto, T. Nakayama, T. Inoue, K. Hataya, H. Miyamoto, M. Senda, K. Hirata, M. Kosaki, N. Shibata, M. Kuzuhara","doi":"10.1109/DRC.2004.1367769","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367769","url":null,"abstract":"This work describes high power AlGaN/GaN heterojunction FETs on SiC substrates which we have developed. To our knowledge, Psat values of 203 W and 4 W are the highest ever achieved at 2 GHz and 30 GHz, respectively, for GaN FETs. We believe that GaN FET technology will play a dominant role in future base station systems.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367850
C. Lee, S. Jin, Keum-dong Jung, J. Lee, Byung-Gook Park
In this paper, we propose a pentacene organic thin-film transistor (OTFT) logic inverter circuit with a depletion mode load OTFT and an enhancement mode driving OTFT. It is confirmed that, with only two OTFTs, the minimum output voltage goes down to 0 V and it improves the noise margin characteristics. We believe that this scheme is a first but significant step for simple and reliable pentacene OTFT logic circuits.
{"title":"Full-swing pentacene organic thin-film transistor inverter with enhancement-mode driver and depletion-mode load","authors":"C. Lee, S. Jin, Keum-dong Jung, J. Lee, Byung-Gook Park","doi":"10.1109/DRC.2004.1367850","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367850","url":null,"abstract":"In this paper, we propose a pentacene organic thin-film transistor (OTFT) logic inverter circuit with a depletion mode load OTFT and an enhancement mode driving OTFT. It is confirmed that, with only two OTFTs, the minimum output voltage goes down to 0 V and it improves the noise margin characteristics. We believe that this scheme is a first but significant step for simple and reliable pentacene OTFT logic circuits.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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