Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367764
Yanfeng Wang, Marco A. Cabassi, T. Ho, K. Lew, J. Redwing, T. Mayer
There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. The ability to integrate field effect devices with p- and n-type conduction channels is a challenge that must be overcome to fabricate complementary logic circuits using such technologies. In this talk, we present the results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type, and n-type silicon nanowires (SiNWs). These results emphasize that future efforts must address the source of the high p-type background doping concentration in vapor-liquid-solid grown SiNWs to facilitate improvements in the properties of n-channel devices.
{"title":"Electrical properties of p- and n-type silicon nanowires","authors":"Yanfeng Wang, Marco A. Cabassi, T. Ho, K. Lew, J. Redwing, T. Mayer","doi":"10.1109/DRC.2004.1367764","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367764","url":null,"abstract":"There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. The ability to integrate field effect devices with p- and n-type conduction channels is a challenge that must be overcome to fabricate complementary logic circuits using such technologies. In this talk, we present the results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type, and n-type silicon nanowires (SiNWs). These results emphasize that future efforts must address the source of the high p-type background doping concentration in vapor-liquid-solid grown SiNWs to facilitate improvements in the properties of n-channel devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367816
E. Menard, D. Khang, K. Lee, R. Nuzzo, J. Rogers
This talk describes the fabrication and electrical characteristics of high performance thin film transistors derived from printed and solution cast micro/nanoscale objects of single crystal silicon. These elements are fabricated from conventional bulk silicon substrates or from silicon-on-insulator wafers by patterning a layer of resist by soft lithography, anisotropically wet etching the exposed silicon, and then lifting off the silicon. A large collection of such objects - which can have geometries that range from ribbons to platelets, sheets, disks and other shapes - constitutes a type of material, which we refer to as microstructured silicon (ps-Si), that can be deposited and patterned, by dry transfer printing or solution casting, onto plastic substrates to yield mechanically flexible thin film transistors that have excellent electrical properties.
{"title":"A printable form of single crystal silicon for high performance thin film transistors on plastic","authors":"E. Menard, D. Khang, K. Lee, R. Nuzzo, J. Rogers","doi":"10.1109/DRC.2004.1367816","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367816","url":null,"abstract":"This talk describes the fabrication and electrical characteristics of high performance thin film transistors derived from printed and solution cast micro/nanoscale objects of single crystal silicon. These elements are fabricated from conventional bulk silicon substrates or from silicon-on-insulator wafers by patterning a layer of resist by soft lithography, anisotropically wet etching the exposed silicon, and then lifting off the silicon. A large collection of such objects - which can have geometries that range from ribbons to platelets, sheets, disks and other shapes - constitutes a type of material, which we refer to as microstructured silicon (ps-Si), that can be deposited and patterned, by dry transfer printing or solution casting, onto plastic substrates to yield mechanically flexible thin film transistors that have excellent electrical properties.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367884
J. Rieh, M. Khater, K. Schonenberg, F. Pagette, P. Smith, T. Adam, K. Stein, D. Ahlgren, G. Freeman
This study investigates the impact of the collector vertical scaling on the tradeoff between f/sub T/ and f/sub max/ with SiGe HBTs of /spl sim/300 GHz performance. We further proceed to discuss its impact on the avalanche breakdown behavior of the devices. It is observed that the selectively implanted collector (SIC) dose variation affects f/sub T/ and f/sub max/ in opposite directions, in 300 GHz SiGe HBTs, which can be exploited to selectively optimize the devices for either f/sub T/ or f/sub max/ depending on the requirement from a given application. This trend also indicates, along with the observed SIC dose dependence of the breakdown voltages, that the traditional speed-breakdown voltage (BV) tradeoff is valid for f/sub T/-BV, but not necessarily for f/sub max/-BV.
{"title":"Collector vertical scaling and performance tradeoffs in 300 GHz SiGe HBTs","authors":"J. Rieh, M. Khater, K. Schonenberg, F. Pagette, P. Smith, T. Adam, K. Stein, D. Ahlgren, G. Freeman","doi":"10.1109/DRC.2004.1367884","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367884","url":null,"abstract":"This study investigates the impact of the collector vertical scaling on the tradeoff between f/sub T/ and f/sub max/ with SiGe HBTs of /spl sim/300 GHz performance. We further proceed to discuss its impact on the avalanche breakdown behavior of the devices. It is observed that the selectively implanted collector (SIC) dose variation affects f/sub T/ and f/sub max/ in opposite directions, in 300 GHz SiGe HBTs, which can be exploited to selectively optimize the devices for either f/sub T/ or f/sub max/ depending on the requirement from a given application. This trend also indicates, along with the observed SIC dose dependence of the breakdown voltages, that the traditional speed-breakdown voltage (BV) tradeoff is valid for f/sub T/-BV, but not necessarily for f/sub max/-BV.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126102563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367868
H. Cho, J. Choe, Ming Li, J. Y. Kim, S. Chung, C. Oh, E. Yoon, Dong-Won Kim, Donggun Park, Kinam Kim
For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L/sub g//W/sub fin/) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V/sub th/) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.
{"title":"Fin width scaling criteria of body-tied FinFET in sub-50 nm regime","authors":"H. Cho, J. Choe, Ming Li, J. Y. Kim, S. Chung, C. Oh, E. Yoon, Dong-Won Kim, Donggun Park, Kinam Kim","doi":"10.1109/DRC.2004.1367868","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367868","url":null,"abstract":"For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L/sub g//W/sub fin/) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V/sub th/) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367771
Y. Wu, A. Saxler, T. Wisleder, M. Moore, R.P. Smith, S. Sheppard, P. Chavarkar, P. Parikh
Recently, electric field modification with GaN-based high-electron-mobility-transistors (HEMTs) using field plates (FP) has resulted in dramatically enhanced power performance. Power densities up to 32 W/mm at 4 GHz have been demonstrated with power-added-efficiency (PAE) of 55%. When scaled to a large periphery, a total output power of 149 W was obtained at 2 GHz. Modern communication applications also require high linearity for power devices. Here we present the linearity performance of GaN-channel HEMTs with various FP lengths at biases up to 108V.
{"title":"Linearity performance of GaN HEMTs with field plates","authors":"Y. Wu, A. Saxler, T. Wisleder, M. Moore, R.P. Smith, S. Sheppard, P. Chavarkar, P. Parikh","doi":"10.1109/DRC.2004.1367771","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367771","url":null,"abstract":"Recently, electric field modification with GaN-based high-electron-mobility-transistors (HEMTs) using field plates (FP) has resulted in dramatically enhanced power performance. Power densities up to 32 W/mm at 4 GHz have been demonstrated with power-added-efficiency (PAE) of 55%. When scaled to a large periphery, a total output power of 149 W was obtained at 2 GHz. Modern communication applications also require high linearity for power devices. Here we present the linearity performance of GaN-channel HEMTs with various FP lengths at biases up to 108V.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126326962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367822
J. Chen, C. Klinke, A. Afzali, P. Avouris
In this paper, we have successfully demonstrated, for the first time, air-stable chemical p-doping of CNFETs via charge transfer; introduced tunability of the V/sub th/, transformed scaled CNFETs from ambipolar to unipolar, improved I/sub on/ by 2-3 orders of magnitude, suppressed minority carrier injection (immunity from drain induced I/sub off/ degradation from intrinsic Schottky barrier CNFET), yielding an excellent I/sub on//I/sub off/ ratio of 10/sup 6/, and demonstrated excellent DIBL-like behavior.
{"title":"Air-stable chemical doping of carbon nanotube transistors [CNFETs]","authors":"J. Chen, C. Klinke, A. Afzali, P. Avouris","doi":"10.1109/DRC.2004.1367822","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367822","url":null,"abstract":"In this paper, we have successfully demonstrated, for the first time, air-stable chemical p-doping of CNFETs via charge transfer; introduced tunability of the V/sub th/, transformed scaled CNFETs from ambipolar to unipolar, improved I/sub on/ by 2-3 orders of magnitude, suppressed minority carrier injection (immunity from drain induced I/sub off/ degradation from intrinsic Schottky barrier CNFET), yielding an excellent I/sub on//I/sub off/ ratio of 10/sup 6/, and demonstrated excellent DIBL-like behavior.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367869
W. Choi, B. Choi, D. Woo, J. Lee, Byung-Gook Park
I-MOS uses modulation of the avalanche breakdown voltage of a gated p-i-n structure to control the output current. Because the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold swing to less than 60 mV/dec at room temperature. However, there are two main obstacles to scale the I-MOS down to nanoscale regime: 1) the source and drain are made up of different types of dopants; 2) the i-region, which is not overlapped by the gate, lies between channel and source. Therefore, in the conventional I-MOS process, the gate, the source and the drain cannot be self-aligned. In this paper, a 130 nm n-channel I-MOS was fabricated for the first time using a novel self-aligned fabrication method. It showed normal transistor operation with dramatically small subthreshold swing (7.2 mV/dec) at room temperature. In addition, to make the I-MOS more practical, we also proposed a novel biasing scheme based on the device physics.
{"title":"A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)","authors":"W. Choi, B. Choi, D. Woo, J. Lee, Byung-Gook Park","doi":"10.1109/DRC.2004.1367869","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367869","url":null,"abstract":"I-MOS uses modulation of the avalanche breakdown voltage of a gated p-i-n structure to control the output current. Because the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold swing to less than 60 mV/dec at room temperature. However, there are two main obstacles to scale the I-MOS down to nanoscale regime: 1) the source and drain are made up of different types of dopants; 2) the i-region, which is not overlapped by the gate, lies between channel and source. Therefore, in the conventional I-MOS process, the gate, the source and the drain cannot be self-aligned. In this paper, a 130 nm n-channel I-MOS was fabricated for the first time using a novel self-aligned fabrication method. It showed normal transistor operation with dramatically small subthreshold swing (7.2 mV/dec) at room temperature. In addition, to make the I-MOS more practical, we also proposed a novel biasing scheme based on the device physics.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367851
P. Chang, Mole Se, A. Murphy, J. Fréchet, V. Subramanian
Through the use of a novel oligothiophene precursor, we have demonstrated organic TFTs exhibiting relatively high mobility while simultaneously retaining ultra-low leakage and excellent on-off ratios. The unique tendency of this material to self-assemble into a crystalline morphology allows non-uniform printed droplets to reorganize into high-quality monolayers. The resulting structure provides excellent electrostatic characteristics, ideal for low power analog applications.
{"title":"Single-monolayer inkjetted oligothiophene organic TFTs exhibiting high performance and low leakage","authors":"P. Chang, Mole Se, A. Murphy, J. Fréchet, V. Subramanian","doi":"10.1109/DRC.2004.1367851","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367851","url":null,"abstract":"Through the use of a novel oligothiophene precursor, we have demonstrated organic TFTs exhibiting relatively high mobility while simultaneously retaining ultra-low leakage and excellent on-off ratios. The unique tendency of this material to self-assemble into a crystalline morphology allows non-uniform printed droplets to reorganize into high-quality monolayers. The resulting structure provides excellent electrostatic characteristics, ideal for low power analog applications.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367842
C. Lent, Mo Liu, J. Timler
We examine the scaling limits of energy dissipation in a specific and concrete physical model - that of clocked quantum-dot cellular automata (QCA). Prototype QCA devices exist and have demonstrated true power gain, an essential feature for any general-purpose computational technology. Though present devices operate at cryogenic temperatures, much work has been done on molecular implementations which can operate at room temperature and are notably smaller than 1.5 nm. QCA represents a radical departure from CMOS, but is still a charge-based binary approach. We solve the equations of motion for the system in the presence of a thermal environment with no a priori assumptions about energy flow. We show directly the effect of the logical structure of the calculation on the heat generated by a circuit. These calculations point to the real nature of the thermodynamic limitations of scaling binary logic devices and suggest strategies for achieving the ultimate limits of device scaling.
{"title":"Physical limits on binary logic switch scaling","authors":"C. Lent, Mo Liu, J. Timler","doi":"10.1109/DRC.2004.1367842","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367842","url":null,"abstract":"We examine the scaling limits of energy dissipation in a specific and concrete physical model - that of clocked quantum-dot cellular automata (QCA). Prototype QCA devices exist and have demonstrated true power gain, an essential feature for any general-purpose computational technology. Though present devices operate at cryogenic temperatures, much work has been done on molecular implementations which can operate at room temperature and are notably smaller than 1.5 nm. QCA represents a radical departure from CMOS, but is still a charge-based binary approach. We solve the equations of motion for the system in the presence of a thermal environment with no a priori assumptions about energy flow. We show directly the effect of the logical structure of the calculation on the heat generated by a circuit. These calculations point to the real nature of the thermodynamic limitations of scaling binary logic devices and suggest strategies for achieving the ultimate limits of device scaling.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114360153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367834
S. Fathpour, Z. Mi, S. Chakrabarti, P. Bhattacharya, A. R. Kovsh, S. Mikhrin, I. Krestnikov, A. Kozhukhov, N. Ledentsov
There is a need to understand the performance limitations and the role of special techniques to enhance quantum dot (QD) laser performance. In this context, we have examined the role of p-doping in the dots and tunnel injection of electrons into the active dots in the lasers. Utilizing these techniques, we demonstrate QD lasers with zero temperature dependence of the threshold current (T/sub 0/=/spl infin/) and the output slope efficiency and small signal modulation bandwidth /spl cong/25 GHz. It is apparent that an optimal level of p-doping, combined with tunnel injection, will lead to lasers with high modulation bandwidth, zero chirp and very high T/sub 0/. These results are presented and discussed.
{"title":"Characteristics of high-performance 1.0 /spl mu/m and 1.3 /spl mu/m quantum dot lasers: impact of p-doping and tunnel injection","authors":"S. Fathpour, Z. Mi, S. Chakrabarti, P. Bhattacharya, A. R. Kovsh, S. Mikhrin, I. Krestnikov, A. Kozhukhov, N. Ledentsov","doi":"10.1109/DRC.2004.1367834","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367834","url":null,"abstract":"There is a need to understand the performance limitations and the role of special techniques to enhance quantum dot (QD) laser performance. In this context, we have examined the role of p-doping in the dots and tunnel injection of electrons into the active dots in the lasers. Utilizing these techniques, we demonstrate QD lasers with zero temperature dependence of the threshold current (T/sub 0/=/spl infin/) and the output slope efficiency and small signal modulation bandwidth /spl cong/25 GHz. It is apparent that an optimal level of p-doping, combined with tunnel injection, will lead to lasers with high modulation bandwidth, zero chirp and very high T/sub 0/. These results are presented and discussed.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123962525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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