Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367800
Y. Katayama, S. Laux
Tunneling devices being studied so far are mostly inter-band or resonant tunneling devices where discrete energy levels due to quantum confinement do not exist or exist only in the channel. Tunneling devices with quantum confinement in the source and drain (discrete energy levels there), such as coupled quantum well devices, are relatively new (A. Simmons et al., Tech. Dig. IEEE IEDM, pp. 755-758, 1997). We present self-consistent DC analyses of the electron transport in coupled quantum well systems through 2D computer simulation for the first time.
目前所研究的隧道装置多为带间或共振隧道装置，由于量子约束而不存在离散能级或仅存在于通道中。在源极和漏极(那里的离散能级)中具有量子约束的隧道装置，如耦合量子阱装置，是相对较新的(A. Simmons等人，Tech. Dig)。IEEE IEDM, pp. 755-758, 1997)。本文首次通过二维计算机模拟对耦合量子阱系统中的电子输运进行了自洽直流电分析。
{"title":"Simulation study of tunneling devices with quantum confinement in source and drain","authors":"Y. Katayama, S. Laux","doi":"10.1109/DRC.2004.1367800","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367800","url":null,"abstract":"Tunneling devices being studied so far are mostly inter-band or resonant tunneling devices where discrete energy levels due to quantum confinement do not exist or exist only in the channel. Tunneling devices with quantum confinement in the source and drain (discrete energy levels there), such as coupled quantum well devices, are relatively new (A. Simmons et al., Tech. Dig. IEEE IEDM, pp. 755-758, 1997). We present self-consistent DC analyses of the electron transport in coupled quantum well systems through 2D computer simulation for the first time.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115878121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367798
K. Felmet, Yangming Sun, Y. Loo
In this paper, we report a solventless, additive approach for patterning conductive copper in the 1-100 /spl mu/m range at ambient conditions. A freshly-etched GaAs substrate is treated with 1,8-octanedithiol molecules, resulting in covalent bonds between the GaAs substrate and one of the thiol functionalities. A poly(dimethylsiloxane), PDMS, elastomeric stamp, freshly evaporated with Cu, is then brought into contact with the substrate. Intimate molecular contact between the raised regions of the stamp and the substrate facilitates the permanent attachment of Cu to the GaAs substrate via the formation of covalent bonds between the unreacted thiol endgroups of octanedithiol and Cu. Pattern transfer is completed upon stamp removal; this process occurs at ambient conditions with less than 30 seconds of contact time. Currently, this technique permits large-area patterning of features with sizes ranging from 1 /spl mu/m to 500 /spl mu/m.
{"title":"Conductive copper patterning by nanotransfer printing","authors":"K. Felmet, Yangming Sun, Y. Loo","doi":"10.1109/DRC.2004.1367798","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367798","url":null,"abstract":"In this paper, we report a solventless, additive approach for patterning conductive copper in the 1-100 /spl mu/m range at ambient conditions. A freshly-etched GaAs substrate is treated with 1,8-octanedithiol molecules, resulting in covalent bonds between the GaAs substrate and one of the thiol functionalities. A poly(dimethylsiloxane), PDMS, elastomeric stamp, freshly evaporated with Cu, is then brought into contact with the substrate. Intimate molecular contact between the raised regions of the stamp and the substrate facilitates the permanent attachment of Cu to the GaAs substrate via the formation of covalent bonds between the unreacted thiol endgroups of octanedithiol and Cu. Pattern transfer is completed upon stamp removal; this process occurs at ambient conditions with less than 30 seconds of contact time. Currently, this technique permits large-area patterning of features with sizes ranging from 1 /spl mu/m to 500 /spl mu/m.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122611338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367820
Y. Lin, J. Appenzeller, P. Avouris
In order to alleviate the disadvantages associated with Schottky barriers in CNFETs, it is necessary to design CNFETs with bulk switching properties meaning that the bulk portion of the nanotube rather than the interface controls the CNFET characteristics. Here we present the first self-aligned bulk-switched CNFET that operates in the enhancement mode with a p-i-p (or n-i-n) doping profile along the tube. With our novel approach, we successfully fabricated CNFETs with excellent switching (S/spl sim/63 mV/dec), the smallest value reported for CNFETs so far, and very good performance in terms of their drain-induced-barrier-lowering (DIBL)-like behavior.
{"title":"Novel structures enabling bulk switching in carbon nanotube FETs","authors":"Y. Lin, J. Appenzeller, P. Avouris","doi":"10.1109/DRC.2004.1367820","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367820","url":null,"abstract":"In order to alleviate the disadvantages associated with Schottky barriers in CNFETs, it is necessary to design CNFETs with bulk switching properties meaning that the bulk portion of the nanotube rather than the interface controls the CNFET characteristics. Here we present the first self-aligned bulk-switched CNFET that operates in the enhancement mode with a p-i-p (or n-i-n) doping profile along the tube. With our novel approach, we successfully fabricated CNFETs with excellent switching (S/spl sim/63 mV/dec), the smallest value reported for CNFETs so far, and very good performance in terms of their drain-induced-barrier-lowering (DIBL)-like behavior.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367813
S. May, B. Wessels
In this work, (InMn)As/InAs p-n heterojunctions have been fabricated and their electronic and magnetic properties characterized. The (In,Mn)As films, deposited by atmospheric pressure meta organic vapor phase epitaxy, are ferromagnetic at room temperature as determined by magneto-optical Kerr effect (MOKE) measurements and variable-temperature magnetic force microscopy. The J-V characteristics of these junctions were measured over the temperature range of 78 to 300 K. In addition, the magnetic field dependence of the I-V characteristics has been measured. The magnetoresistive properties of these heterojunctions suggest they may be suitable for use in spintronic devices.
{"title":"Electronic and magnetic properties of ferromagnetic p-(In,Mn)As/n-InAs heterojunctions [spintronic device applications]","authors":"S. May, B. Wessels","doi":"10.1109/DRC.2004.1367813","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367813","url":null,"abstract":"In this work, (InMn)As/InAs p-n heterojunctions have been fabricated and their electronic and magnetic properties characterized. The (In,Mn)As films, deposited by atmospheric pressure meta organic vapor phase epitaxy, are ferromagnetic at room temperature as determined by magneto-optical Kerr effect (MOKE) measurements and variable-temperature magnetic force microscopy. The J-V characteristics of these junctions were measured over the temperature range of 78 to 300 K. In addition, the magnetic field dependence of the I-V characteristics has been measured. The magnetoresistive properties of these heterojunctions suggest they may be suitable for use in spintronic devices.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129224702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367779
D. V. Singh, K. Jenkins
Carbon nanotube field-effect transistors are expected to operate at very high frequencies, possibly in the THz regime, making them attractive for future nanoelectronics technologies. However, due to formidable measurement difficulties, this performance has not yet been demonstrated. This paper reports: 1) the first direct observation of CNFETs operating at several hundred MHz; and 2) illustrates how to extend direct frequency response measurements to the GHz regime.
{"title":"Direct measurements of the AC performance of carbon nanotube field effect transistors","authors":"D. V. Singh, K. Jenkins","doi":"10.1109/DRC.2004.1367779","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367779","url":null,"abstract":"Carbon nanotube field-effect transistors are expected to operate at very high frequencies, possibly in the THz regime, making them attractive for future nanoelectronics technologies. However, due to formidable measurement difficulties, this performance has not yet been demonstrated. This paper reports: 1) the first direct observation of CNFETs operating at several hundred MHz; and 2) illustrates how to extend direct frequency response measurements to the GHz regime.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116594670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367870
B. Choi, Yong-kyu Lee, W. Choi, Han Park, D. Woo, J. Lee, Byung-Gook Park, Changho Oh, C. Chung, Donggun Park
In this work, we fabricated twin silicon-oxide-nitride-oxide-silicon (SONOS) memory (TSM) cell transistors, based on the 90 nm non-volatile memory technology and showed the implementation of programmable threshold voltage (V/sub th/) MOSFETs in the nano-scale regime. It was clearly observed that the transistor has high I/sub on//I/sub off/ ratio (>106) and small drain leakage (/spl sim/10 pA) in the 30 nm regime. From the experimental result from fabricated devices, it can be deduced that the TSM transistor has various MOSFET applications due to charged states in the nitride. To evaluate the various MOSFET applications of the TSM transistor in the nano-scale regime, the simulation of a 30 nm-long gate TSM transistor was carried out on the 2D ATLAS, including tunneling and impact ionization models. It is concluded that the proposed TSM MOSFET structure promises a well-controlled short channel effect and high I/sub on//I/sub off/ characteristics.
{"title":"Nano-scale MOSFETs with programmable virtual source/drain","authors":"B. Choi, Yong-kyu Lee, W. Choi, Han Park, D. Woo, J. Lee, Byung-Gook Park, Changho Oh, C. Chung, Donggun Park","doi":"10.1109/DRC.2004.1367870","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367870","url":null,"abstract":"In this work, we fabricated twin silicon-oxide-nitride-oxide-silicon (SONOS) memory (TSM) cell transistors, based on the 90 nm non-volatile memory technology and showed the implementation of programmable threshold voltage (V/sub th/) MOSFETs in the nano-scale regime. It was clearly observed that the transistor has high I/sub on//I/sub off/ ratio (>106) and small drain leakage (/spl sim/10 pA) in the 30 nm regime. From the experimental result from fabricated devices, it can be deduced that the TSM transistor has various MOSFET applications due to charged states in the nitride. To evaluate the various MOSFET applications of the TSM transistor in the nano-scale regime, the simulation of a 30 nm-long gate TSM transistor was carried out on the 2D ATLAS, including tunneling and impact ionization models. It is concluded that the proposed TSM MOSFET structure promises a well-controlled short channel effect and high I/sub on//I/sub off/ characteristics.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114273330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367846
S. Koester, J. Schaub, G. Dehlinger, J. Chu, Q. Ouyang, A. Grill
Ge has tremendous potential for high-speed operation at /spl lambda/=850 nm, an important wavelength for short range highly-parallel interconnects, because the absorption length of Ge is only a few hundred nm. However, for thin Ge-on-Si detectors, the Ge film must be isolated from the underlying Si in order to prevent collection of slow carriers generated deep within the substrate. In this work, we present results of lateral PIN photodetectors fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. These devices have bandwidths as high as 29 GHz, and the highest bandwidth-efficiency product reported to date for a group-IV photodetector.
{"title":"High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth","authors":"S. Koester, J. Schaub, G. Dehlinger, J. Chu, Q. Ouyang, A. Grill","doi":"10.1109/DRC.2004.1367846","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367846","url":null,"abstract":"Ge has tremendous potential for high-speed operation at /spl lambda/=850 nm, an important wavelength for short range highly-parallel interconnects, because the absorption length of Ge is only a few hundred nm. However, for thin Ge-on-Si detectors, the Ge film must be isolated from the underlying Si in order to prevent collection of slow carriers generated deep within the substrate. In this work, we present results of lateral PIN photodetectors fabricated using Ge films deposited on ultra-thin silicon-on-insulator (SOI) substrates. These devices have bandwidths as high as 29 GHz, and the highest bandwidth-efficiency product reported to date for a group-IV photodetector.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132720354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367871
K. Bhuwalka, J. Schulze, I. Eisele
The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, I/sub on/, and threshold voltage, V/sub T/, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for V/sub GS/=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, t/sub ox/, according to technology requirements.
{"title":"Scaling issues of n-channel vertical tunnel FET with /spl delta/p/sup +/ SiGe layer","authors":"K. Bhuwalka, J. Schulze, I. Eisele","doi":"10.1109/DRC.2004.1367871","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367871","url":null,"abstract":"The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, I/sub on/, and threshold voltage, V/sub T/, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for V/sub GS/=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, t/sub ox/, according to technology requirements.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367903
D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki
To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.
{"title":"Planarized InP/InGaAs heterojunction bipolar transistors with f/sub MAX/ > 500 GHz","authors":"D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki","doi":"10.1109/DRC.2004.1367903","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367903","url":null,"abstract":"To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126476607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-21DOI: 10.1109/DRC.2004.1367792
B. K. Ng, J. David, W. M. Soong, J. Ng, C. Tan, H. Liu, M. Hopkinson, P. Robson
Currently available avalanche photodiodes (APDs) for use in telecommunication systems operating at 1.3/1.55 /spl mu/m utilize InP and InGaAs as the multiplication and absorption medium respectively. The excess noise performance of the InP avalanching region is relatively poor, and is limited by the hole to electron ionization coefficient ratio (/spl beta///spl alpha/). We have recently reported that Al/sub 0.8/Ga/sub 0.2/As may be a suitable material for the multiplication region in APDs due to its large /spl alpha///spl beta/ ratio in bulk structures (B.K. Ng et al, IEEE Photon. Technol. Lett., vol. 14, p. 522, 2002), which results in a very low avalanche excess noise. In this work, we extend our previous study by investigating the excess noise characteristics in both bulk and sub-micron Al/sub x/Ga/sub 1-x/As diodes as a function of x. Our results here suggest that long wavelength GaAs-based APDs of superior noise characteristics than InP-based APDs can now be realized.
{"title":"Low noise GaAs-based avalanche photodiodes for long wavelength applications","authors":"B. K. Ng, J. David, W. M. Soong, J. Ng, C. Tan, H. Liu, M. Hopkinson, P. Robson","doi":"10.1109/DRC.2004.1367792","DOIUrl":"https://doi.org/10.1109/DRC.2004.1367792","url":null,"abstract":"Currently available avalanche photodiodes (APDs) for use in telecommunication systems operating at 1.3/1.55 /spl mu/m utilize InP and InGaAs as the multiplication and absorption medium respectively. The excess noise performance of the InP avalanching region is relatively poor, and is limited by the hole to electron ionization coefficient ratio (/spl beta///spl alpha/). We have recently reported that Al/sub 0.8/Ga/sub 0.2/As may be a suitable material for the multiplication region in APDs due to its large /spl alpha///spl beta/ ratio in bulk structures (B.K. Ng et al, IEEE Photon. Technol. Lett., vol. 14, p. 522, 2002), which results in a very low avalanche excess noise. In this work, we extend our previous study by investigating the excess noise characteristics in both bulk and sub-micron Al/sub x/Ga/sub 1-x/As diodes as a function of x. Our results here suggest that long wavelength GaAs-based APDs of superior noise characteristics than InP-based APDs can now be realized.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130539063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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