A. Girardi, Lucas Compassi-Severo, Paulo César Comassetto de Aguirre
The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.
{"title":"Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial","authors":"A. Girardi, Lucas Compassi-Severo, Paulo César Comassetto de Aguirre","doi":"10.29292/jics.v17i1.573","DOIUrl":"https://doi.org/10.29292/jics.v17i1.573","url":null,"abstract":"The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47909065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analysis of generic single-pole, two-pole, and three-pole operational transconductance amplifiers (OTAs) is carried out based on settling time. The most important design metrics of the open-loop frequency response, such as the stability margins and the gain-bandwidth product (GBW) are related to the settling time of single-, two- and three-stage OTAs in closed-loop configuration, enabling to present a design procedure for each OTA based on the settling time specifications. Transistor-level design examples are provided for each case to validate the described settling-based design strategies.
{"title":"Analysis and Design Procedures of CMOS OTAs Based on Settling Time","authors":"H. Aminzadeh, Dalton Martini Colombo","doi":"10.29292/jics.v17i1.590","DOIUrl":"https://doi.org/10.29292/jics.v17i1.590","url":null,"abstract":"Analysis of generic single-pole, two-pole, and three-pole operational transconductance amplifiers (OTAs) is carried out based on settling time. The most important design metrics of the open-loop frequency response, such as the stability margins and the gain-bandwidth product (GBW) are related to the settling time of single-, two- and three-stage OTAs in closed-loop configuration, enabling to present a design procedure for each OTA based on the settling time specifications. Transistor-level design examples are provided for each case to validate the described settling-based design strategies.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49098889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The requirements of portable devices and other applications for a compact and efficient power converter drives the integration of power converters. However, conventional switched-inductor and switched-capacitor converters struggle with these requirements in integrated circuit dimensions. This paper introduces the state-of-the-art of a growing trend in integrated power converters, called hybrid switched converters. Here, the issues of conventional topologies are introduced, as well as the improvements addressed by hybrid converters, in terms of power efficiency, power density and voltage conversion ratio. Also, the characteristics of the four main trends in fully and highly integrated hybrid switched converters topologies are discussed. Finally, their state-of-the-art metrics are presented and compared to the metrics of conventional integrated switched converters.
{"title":"Integrated Hybrid Switched Converters: A Review","authors":"J. Castellanos","doi":"10.29292/jics.v17i1.570","DOIUrl":"https://doi.org/10.29292/jics.v17i1.570","url":null,"abstract":"The requirements of portable devices and other applications for a compact and efficient power converter drives the integration of power converters. However, conventional switched-inductor and switched-capacitor converters struggle with these requirements in integrated circuit dimensions. This paper introduces the state-of-the-art of a growing trend in integrated power converters, called hybrid switched converters. Here, the issues of conventional topologies are introduced, as well as the improvements addressed by hybrid converters, in terms of power efficiency, power density and voltage conversion ratio. Also, the characteristics of the four main trends in fully and highly integrated hybrid switched converters topologies are discussed. Finally, their state-of-the-art metrics are presented and compared to the metrics of conventional integrated switched converters.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49063829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Input referred offset voltage, 1/f noise and thermal noise are amplifier properties that directly restrict the ability of discerning signals beyond a certain limit. The ever increasing spectrum of applications of integrated circuits and trends in the semiconductor market have pushed engineers to design circuits with successively lower voltage, less power consumption, higher dynamic range, accurate gain and wider bandwidth, preferably altogether. Amplifiers input errors are key properties, which have to be minimized, however with the least negative impact upon the other equally important properties. This paper reviews some the most relevant techniques applied to reducing input errors of CMOS amplifiers aiming at to provide a condensed set of information that can help designers at the starting point of a new design of a precision analog circuit. The focus in all cases that were selected to be studied in this review work was the reduction of offset and noise regardless of any commitment of the used technique with other characteristics of the amplifier and its impacts on figures of merit like NEF and PEF.
{"title":"Review of Offset and Noise Reduction Techniques for CMOS","authors":"Carlos Alberto Dos Reis","doi":"10.29292/jics.v17i1.572","DOIUrl":"https://doi.org/10.29292/jics.v17i1.572","url":null,"abstract":"Input referred offset voltage, 1/f noise and thermal noise are amplifier properties that directly restrict the ability of discerning signals beyond a certain limit. The ever increasing spectrum of applications of integrated circuits and trends in the semiconductor market have pushed engineers to design circuits with successively lower voltage, less power consumption, higher dynamic range, accurate gain and wider bandwidth, preferably altogether. Amplifiers input errors are key properties, which have to be minimized, however with the least negative impact upon the other equally important properties. This paper reviews some the most relevant techniques applied to reducing input errors of CMOS amplifiers aiming at to provide a condensed set of information that can help designers at the starting point of a new design of a precision analog circuit. The focus in all cases that were selected to be studied in this review work was the reduction of offset and noise regardless of any commitment of the used technique with other characteristics of the amplifier and its impacts on figures of merit like NEF and PEF. ","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48053476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Joao Roberto Raposo de Oliveira Martins, Francisco de Oliveira Alves, Pietro Maris Ferreira
The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes a general gm over Id technique for designing temperature-aware circuits that can be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a circuit design example.
物联网的出现给电路设计带来了新的挑战。电路和传感器在恶劣环境中的存在带来了对解决这些问题的方法的需求。自晶体管问世以来，已知温度对性能有重大影响，尽管已经提出了非常低的温度敏感度电路，但还不存在设计它们的通用方法。本文提出了一种用于设计温度感知电路的通用gm over Id技术，该技术可以用于测量数据、分析或基于仿真模型。该模型通过X-FAB XT018晶体管高达250°C的测量值进行了验证，随后通过电路设计示例进行了验证。
{"title":"A General gm/Id Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 °C","authors":"Joao Roberto Raposo de Oliveira Martins, Francisco de Oliveira Alves, Pietro Maris Ferreira","doi":"10.29292/jics.v17i1.552","DOIUrl":"https://doi.org/10.29292/jics.v17i1.552","url":null,"abstract":" The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes a general gm over Id technique for designing temperature-aware circuits that can be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a circuit design example.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47334415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Berndt, B. Abreu, I. S. Campos, B. Lima, M. Grellert, J. T. Carvalho, C. Meinhardt
Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Machine learning techniques show high performance in solving specific problems, being an attractive option to improve electronic design tools. We explore Cartesian Genetic Programming (CGP) for logic optimization of exact or approximate Boolean functions in our work. The proposed CGP-based flow receives the expected circuit behavior as a truth-table and either performs the synthesis starting from random circuits or optimizes a circuit description provided in the format of an AND-Inverter Graph. The optimization flow improves solutions found by other techniques, using them for bootstrapping the evolutionary process. We use two metrics to evaluate our CGP-based flow: (i) the number of AIG nodes or (ii) the circuit accuracy. The results obtained showed that the CGP-based flow provided at least 22.6% superior results when considering the trade-off between accuracy and size compared with two other methods that brought the best accuracy and size outcomes, respectively.
{"title":"CGP-based Logic Flow: Optimizing Accuracy and Size of Approximate Circuits","authors":"A. Berndt, B. Abreu, I. S. Campos, B. Lima, M. Grellert, J. T. Carvalho, C. Meinhardt","doi":"10.29292/jics.v17i1.546","DOIUrl":"https://doi.org/10.29292/jics.v17i1.546","url":null,"abstract":"Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Machine learning techniques show high performance in solving specific problems, being an attractive option to improve electronic design tools. We explore Cartesian Genetic Programming (CGP) for logic optimization of exact or approximate Boolean functions in our work. The proposed CGP-based flow receives the expected circuit behavior as a truth-table and either performs the synthesis starting from random circuits or optimizes a circuit description provided in the format of an AND-Inverter Graph. The optimization flow improves solutions found by other techniques, using them for bootstrapping the evolutionary process. We use two metrics to evaluate our CGP-based flow: (i) the number of AIG nodes or (ii) the circuit accuracy. The results obtained showed that the CGP-based flow provided at least 22.6% superior results when considering the trade-off between accuracy and size compared with two other methods that brought the best accuracy and size outcomes, respectively.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45557620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ian Christian Fernandez, M. T. De Leon, A. Alvarez, J. Hizon, M. Rosales
The CMOS thyristor delay element and its basic operation are presented in this paper. Six variations of the thyristor design developed over the years to extend the delay length, to improve the consistency of the delay, or to control the sensitivities of the delay are also discussed. This includes the complementary thyristor, the thyristor without the current source, the thyristor with threshold elevation, the thyristor with opposing current source, the single-ended thyristor, and the thyristor-type feedback delay element. Design considerations common to all CMOS thyristors are also discussed to provide insights on topology selection, capacitive loading, and transistor sizing.
{"title":"Properties and Design of CMOS Thyristor Delay Elements","authors":"Ian Christian Fernandez, M. T. De Leon, A. Alvarez, J. Hizon, M. Rosales","doi":"10.29292/jics.v17i1.580","DOIUrl":"https://doi.org/10.29292/jics.v17i1.580","url":null,"abstract":"The CMOS thyristor delay element and its basic operation are presented in this paper. Six variations of the thyristor design developed over the years to extend the delay length, to improve the consistency of the delay, or to control the sensitivities of the delay are also discussed. This includes the complementary thyristor, the thyristor without the current source, the thyristor with threshold elevation, the thyristor with opposing current source, the single-ended thyristor, and the thyristor-type feedback delay element. Design considerations common to all CMOS thyristors are also discussed to provide insights on topology selection, capacitive loading, and transistor sizing.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49169488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
César William Vera Casañas, Thainann Henrique Pereira de Castro, Gabriel Antonio Fanelli de Souza, R. Moreno, Dalton Martini Colombo
A current reference is able to provide a precise and accurate current for other circuits inside a chip. This type of electronic circuit is employed as a building block in numerous analog and mixed-signal circuits. Moreover, it is a fundamental component of current-mode circuits. This work discusses the basic and essential concepts of designing CMOS integrated current references. A review of conventional topologies is presented, including current mirrors and current references. Temperature dependence is discussed, along with PTAT and CTAT topologies, and some low-power/low-voltage implementations are also presented.
{"title":"Review of CMOS Currente References","authors":"César William Vera Casañas, Thainann Henrique Pereira de Castro, Gabriel Antonio Fanelli de Souza, R. Moreno, Dalton Martini Colombo","doi":"10.29292/jics.v17i1.592","DOIUrl":"https://doi.org/10.29292/jics.v17i1.592","url":null,"abstract":"A current reference is able to provide a precise and accurate current for other circuits inside a chip. This type of electronic circuit is employed as a building block in numerous analog and mixed-signal circuits. Moreover, it is a fundamental component of current-mode circuits. This work discusses the basic and essential concepts of designing CMOS integrated current references. A review of conventional topologies is presented, including current mirrors and current references. Temperature dependence is discussed, along with PTAT and CTAT topologies, and some low-power/low-voltage implementations are also presented.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43041660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Secure components and devices have always been and always will be a challenge for the electronics industry. In this sense, there is a constant and growing demand for new solutions that can allow reliability in the use and authenticity of components and devices. The end-user is not able to assess the existing risk, much less if the component or device is reliable in several aspects, mainly improper access to its information. This work presents a new integration of two technologies: Blockchains networks, which implement a kind of decentralized and inviolable database, which can increase resilience, security and guarantee against the alteration of the information registered in its structure; Physical Unclonable Functions (PUF), which allow the generation of a unique cryptographic key, since they use unique physical characteristics of each semiconductor component, considerably increasing security, the protection of industrial property and the opportunity for remote authentication of devices. The unprecedented contribution here is in the integration of existing technologies, in order to obtain an innovative solution of authentication and cyber security for the internet of things and other devices.
{"title":"Authentication for Integrated Circuit and Devices Using Blockchain and Physical Unclonable Functions","authors":"Alessandro Augusto Nunes Campos, T. Pimenta","doi":"10.29292/jics.v17i1.555","DOIUrl":"https://doi.org/10.29292/jics.v17i1.555","url":null,"abstract":"Secure components and devices have always been and always will be a challenge for the electronics industry. In this sense, there is a constant and growing demand for new solutions that can allow reliability in the use and authenticity of components and devices. The end-user is not able to assess the existing risk, much less if the component or device is reliable in several aspects, mainly improper access to its information. This work presents a new integration of two technologies: Blockchains networks, which implement a kind of decentralized and inviolable database, which can increase resilience, security and guarantee against the alteration of the information registered in its structure; Physical Unclonable Functions (PUF), which allow the generation of a unique cryptographic key, since they use unique physical characteristics of each semiconductor component, considerably increasing security, the protection of industrial property and the opportunity for remote authentication of devices. The unprecedented contribution here is in the integration of existing technologies, in order to obtain an innovative solution of authentication and cyber security for the internet of things and other devices.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45028454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pietro Maris Ferreira, Emilie Avignon-Meseldzija, P. Bénabès, Francis Trélin
Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.
{"title":"Surface versus Performance Trade-offs: A Review of Layout Techniques","authors":"Pietro Maris Ferreira, Emilie Avignon-Meseldzija, P. Bénabès, Francis Trélin","doi":"10.29292/jics.v17i1.589","DOIUrl":"https://doi.org/10.29292/jics.v17i1.589","url":null,"abstract":"Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48890015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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