Bruno W. S. Arruda, E. Gurjão, Raimundo C. S. Freire
Analog to Information Converters (AIC) implements signal acquisition in Compressed Sensing. AIC performance is affected by noise and hardware imperfections. In parallel Random Modulator Pre-Integrator (RMPI) architectures, delay among channels reduces the performance; thus, delay estimation and compensation methods are necessary. In previous works, delay estimation compares a reference signal with a reconstructed signal from the AIC output; however, such methods produce different results according to the recovery method. To avoid this problem, we present a method based on a controlled delay signal to estimate channel delay without the necessity of signal recovery. The obtained results show the technique's feasibility and the possibility of its use as a built-in calibration process for AIC.
{"title":"A method for delay estimation between channels of Analog to Information Converters","authors":"Bruno W. S. Arruda, E. Gurjão, Raimundo C. S. Freire","doi":"10.29292/jics.v17i2.562","DOIUrl":"https://doi.org/10.29292/jics.v17i2.562","url":null,"abstract":"Analog to Information Converters (AIC) implements signal acquisition in Compressed Sensing. AIC performance is affected by noise and hardware imperfections. In parallel Random Modulator Pre-Integrator (RMPI) architectures, delay among channels reduces the performance; thus, delay estimation and compensation methods are necessary. In previous works, delay estimation compares a reference signal with a reconstructed signal from the AIC output; however, such methods produce different results according to the recovery method. To avoid this problem, we present a method based on a controlled delay signal to estimate channel delay without the necessity of signal recovery. The obtained results show the technique's feasibility and the possibility of its use as a built-in calibration process for AIC.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48025144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article begins with a brief overview of the structure, physical characteristics, and peculiarities of organic field effect transistors. The main differences from the silicon MOSFET are emphasized. The results of poly 3-hexylthiophene and cross-linked polyvinyl alcohol top gate-bottom contact transistors with different channel lengths fabricated by standard photolithography and plasma etching are described. Transistors showed good charge mobility, high ION/IOFF and excellent environmental stability. The Shockley model and the Transmission Line Method (TLM) were applied to characterize the transistors. Mobility was extracted by both methods and differences were discussed. The shorter the channel length and the higher the conductivity of the semiconductor, the greater the impact of contact resistance. In these cases, the use of TLM for parameters extraction becomes essential. The transistors were submitted to extended current-voltage measurements and drain current degradation was observed. Drain current as a function of the integral charge passing through the channel was investigated. The strong decrease in current was found to be related to reduced mobility of charge carriers. Reasons for this behavior are suggested.
{"title":"Organic Field Effect Transistors","authors":"Henry Boudinov, G. V. Leite","doi":"10.29292/jics.v17i2.615","DOIUrl":"https://doi.org/10.29292/jics.v17i2.615","url":null,"abstract":"This article begins with a brief overview of the structure, physical characteristics, and peculiarities of organic field effect transistors. The main differences from the silicon MOSFET are emphasized. The results of poly 3-hexylthiophene and cross-linked polyvinyl alcohol top gate-bottom contact transistors with different channel lengths fabricated by standard photolithography and plasma etching are described. Transistors showed good charge mobility, high ION/IOFF and excellent environmental stability. The Shockley model and the Transmission Line Method (TLM) were applied to characterize the transistors. Mobility was extracted by both methods and differences were discussed. The shorter the channel length and the higher the conductivity of the semiconductor, the greater the impact of contact resistance. In these cases, the use of TLM for parameters extraction becomes essential. The transistors were submitted to extended current-voltage measurements and drain current degradation was observed. Drain current as a function of the integral charge passing through the channel was investigated. The strong decrease in current was found to be related to reduced mobility of charge carriers. Reasons for this behavior are suggested.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42327566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.
{"title":"Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures","authors":"M. Pavanello, M. de Souza","doi":"10.29292/jics.v17i2.621","DOIUrl":"https://doi.org/10.29292/jics.v17i2.621","url":null,"abstract":"This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42701559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a historical analysis of reconfigurable field effect transistors (RFETs). History shows the naturalness of its development from the evolution of integrated circuits (ICs) technology. Next, its operating principles are detailed to further study the variety of structures proposed in the specialized literature. Among these structures, the Back Enhanced SOI MOSFET (BESOI MOSFET) has been studied in detail, which stands out for its simplicity of fabrication and the possibility of integration with conventional technologies. The BESOI MOSFET is used to present proofs of concept for RFET applications such as: reconfigurable digital circuits, light sensor, permittivity-based biosensor and charge-based biosensor. The latter may allow, for example, obtaining a glucose sensor. Finally, future perspectives of applications of RFETs are presented, as in systems of protection of the intellectual property of ICs.
{"title":"Reconfigurable SOI-MOSFET: Past, Present and Future Applications","authors":"R. Rangel, K. Sasaki, J. Martino","doi":"10.29292/jics.v17i2.626","DOIUrl":"https://doi.org/10.29292/jics.v17i2.626","url":null,"abstract":"This paper presents a historical analysis of reconfigurable field effect transistors (RFETs). History shows the naturalness of its development from the evolution of integrated circuits (ICs) technology. Next, its operating principles are detailed to further study the variety of structures proposed in the specialized literature. Among these structures, the Back Enhanced SOI MOSFET (BESOI MOSFET) has been studied in detail, which stands out for its simplicity of fabrication and the possibility of integration with conventional technologies. The BESOI MOSFET is used to present proofs of concept for RFET applications such as: reconfigurable digital circuits, light sensor, permittivity-based biosensor and charge-based biosensor. The latter may allow, for example, obtaining a glucose sensor. Finally, future perspectives of applications of RFETs are presented, as in systems of protection of the intellectual property of ICs.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46535096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.
{"title":"Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs","authors":"Gabriel Augusto DaSilva, S. Gimenez","doi":"10.29292/jics.v17i2.586","DOIUrl":"https://doi.org/10.29292/jics.v17i2.586","url":null,"abstract":"Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45193570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The technological discoveries and developments since dawn of civilization that resulted in the modern wristwatch are linked to the evolution of Science itself. A history of over 6000 years filled with amazing technical prowess since the emergence of the first cities in Mesopotamia established by the v{S}umer civilization. Usage of gears for timekeeping has its origin in the Islamic Golden Age about 1000 years ago. Although gears have been known for over 2000 years such as found in the Antikythera Mechanism. Only in the seventeenth century springs started to be used in clock making. In the eighteenth century the amazing textit{Tourbillon} was designed and built to increase clock accuracy. In the nineteenth century the tuning fork was used for the first time as timebase. Wristwatches started to become popular in the beginning of the twentieth century. Later in the second half of the twentieth century the first electronic wristwatch was designed and produced, which brings us to the curious case of the Bulova textit{ACCUTRON} caliber 214 the first transistorized wristwatch, another marvel of technological innovation and craftsmanship whose operation is frequently misunderstood. In this paper the historical evolution of timekeeping is presented. The goal is to show the early connection between Science and Engineering in the development of timekeeping devices. This linked development only became common along the twentieth century and beyond.
{"title":"Evolution of Timekeeping from Water Clock to Quartz Clock - the Curious Case of the Bulova ACCUTRON 214 the First Transistorized Wristwatch","authors":"Edval J. P. Santos","doi":"10.29292/jics.v17i3.629","DOIUrl":"https://doi.org/10.29292/jics.v17i3.629","url":null,"abstract":"The technological discoveries and developments since dawn of civilization that resulted in the modern wristwatch are linked to the evolution of Science itself. A history of over 6000 years filled with amazing technical prowess since the emergence of the first cities in Mesopotamia established by the v{S}umer civilization. Usage of gears for timekeeping has its origin in the Islamic Golden Age about 1000 years ago. Although gears have been known for over 2000 years such as found in the Antikythera Mechanism. Only in the seventeenth century springs started to be used in clock making. In the eighteenth century the amazing textit{Tourbillon} was designed and built to increase clock accuracy. In the nineteenth century the tuning fork was used for the first time as timebase. Wristwatches started to become popular in the beginning of the twentieth century. Later in the second half of the twentieth century the first electronic wristwatch was designed and produced, which brings us to the curious case of the Bulova textit{ACCUTRON} caliber 214 the first transistorized wristwatch, another marvel of technological innovation and craftsmanship whose operation is frequently misunderstood. In this paper the historical evolution of timekeeping is presented. The goal is to show the early connection between Science and Engineering in the development of timekeeping devices. This linked development only became common along the twentieth century and beyond.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46246060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Silva, João V. C. Leal, W. Perina, J. Martino, E. Simoen, A. Veloso, P. Agopian
This work presents a trade-off analysis between transistor efficiency (gm/ID which is proportional to the intrinsic voltage gain Av) and the unit gain frequency (fT) of nanosheet (NSH) NMOS devices for temperatures from room temperature down to -100 °C. The analyses were performed experimentally as a function of the inversion coefficient (IC) in order to determine the optimal application region for optimization of both parameters. These analyses were performed with NSH NMOS for channel lengths of 28 nm, 70 nm and 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10) for the three analyzed temperatures, where the highest value obtained for gm/ID x fT was found. In this optimum bias point the AV is 45 dB (L=200 nm) and 39 dB (L=28 nm) and fT is 9 GHz (L=200 nm) and 186 GHz (L=28nm) both for T=25 °C, which should be suitable for many applications.
这项工作提出了晶体管效率(gm/ID，与固有电压增益Av成正比)和纳米片(NSH) NMOS器件的单位增益频率(fT)之间的权衡分析，温度从室温降至-100°C。实验分析了反演系数(IC)的函数，以确定两个参数优化的最佳应用区域。这些分析是用NSH NMOS进行的，通道长度为28 nm, 70 nm和200 nm。结果表明，三种分析温度的最佳工作点发生在中等和强反转(IC=10)之间的转变，其中gm/ID x fT的值最高。在此最佳偏置点，当温度为25°C时，AV分别为45 dB (L=200 nm)和39 dB (L=28nm)， fT分别为9 GHz (L=200 nm)和186 GHz (L=28nm)，这应该适用于许多应用。
{"title":"Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOSFET down to -100 oC","authors":"V. Silva, João V. C. Leal, W. Perina, J. Martino, E. Simoen, A. Veloso, P. Agopian","doi":"10.29292/jics.v17i1.550","DOIUrl":"https://doi.org/10.29292/jics.v17i1.550","url":null,"abstract":"This work presents a trade-off analysis between transistor efficiency (gm/ID which is proportional to the intrinsic voltage gain Av) and the unit gain frequency (fT) of nanosheet (NSH) NMOS devices for temperatures from room temperature down to -100 °C. The analyses were performed experimentally as a function of the inversion coefficient (IC) in order to determine the optimal application region for optimization of both parameters. These analyses were performed with NSH NMOS for channel lengths of 28 nm, 70 nm and 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10) for the three analyzed temperatures, where the highest value obtained for gm/ID x fT was found. In this optimum bias point the AV is 45 dB (L=200 nm) and 39 dB (L=28 nm) and fT is 9 GHz (L=200 nm) and 186 GHz (L=28nm) both for T=25 °C, which should be suitable for many applications.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44887694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive review of the state of the art for oscillators operating at reduced supply voltage. The analysis and implementation examples of differ-ent types of oscillators, such as LC oscillators, transformer-based oscillators, and CMOS oscillators are presented. Expres-sions for the oscillation frequency and the minimum supply voltage limit are provided. The characteristics, advantages, and constrains of different topologies are discussed, providing a reference guideline for the choice of the best topology for a given application.
{"title":"Overview of Sub-100 mV Oscillators","authors":"Márcio Bender Machado, Rafael Luciano Radin","doi":"10.29292/jics.v17i1.577","DOIUrl":"https://doi.org/10.29292/jics.v17i1.577","url":null,"abstract":"This paper presents a comprehensive review of the state of the art for oscillators operating at reduced supply voltage. The analysis and implementation examples of differ-ent types of oscillators, such as LC oscillators, transformer-based oscillators, and CMOS oscillators are presented. Expres-sions for the oscillation frequency and the minimum supply voltage limit are provided. The characteristics, advantages, and constrains of different topologies are discussed, providing a reference guideline for the choice of the best topology for a given application.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44427900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The demand for analog and mixed-signal integrated circuits has increased significantly in the last decades, although we have been living in a “digital era”. One of the reasons for such high demand is simply explicated by the increase of devices in our daily life. Such scenario can be simply called as “Ubiquitous computing” and/or the Internet of Everything. This Special Issue brings ten invited papers from experts in the field. The readers will be provided with an extensive literature review.
{"title":"Guest Editors' Words","authors":"C. Fayomi, Dalton Martini Colombo","doi":"10.29292/jics.v17i1.607","DOIUrl":"https://doi.org/10.29292/jics.v17i1.607","url":null,"abstract":"The demand for analog and mixed-signal integrated circuits has increased significantly in the last decades, although we have been living in a “digital era”. One of the reasons for such high demand is simply explicated by the increase of devices in our daily life. Such scenario can be simply called as “Ubiquitous computing” and/or the Internet of Everything. This Special Issue brings ten invited papers from experts in the field. The readers will be provided with an extensive literature review.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44429952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Girardi, Lucas Compassi-Severo, Paulo César Comassetto de Aguirre
The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.
{"title":"Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial","authors":"A. Girardi, Lucas Compassi-Severo, Paulo César Comassetto de Aguirre","doi":"10.29292/jics.v17i1.573","DOIUrl":"https://doi.org/10.29292/jics.v17i1.573","url":null,"abstract":"The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47909065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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