Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898197
Z. Tung, D. Ang
Examining the drain current recovery traces of a small area SiON p-MOSFET subjected to repeated NBTI stress and relaxation cycling reveals direct evidence of transient to permanent hole trapping transformation inferred from previous studies on big area devices. The results show that the emission times of hole traps are not time-invariant (as normally presumed) but can increase due to evolution of the defect sites into more structurally stable forms. In addition, a new type of switching hole traps, exhibiting intermittent charging during stress and occasional increase in emission time by ~5 orders of magnitude, is observed.
{"title":"Transient to temporarily permanent and permanent hole trapping transformation in the small area SiON P-MOSFET subjected to negative-bias temperature stress","authors":"Z. Tung, D. Ang","doi":"10.1109/IPFA.2014.6898197","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898197","url":null,"abstract":"Examining the drain current recovery traces of a small area SiON p-MOSFET subjected to repeated NBTI stress and relaxation cycling reveals direct evidence of transient to permanent hole trapping transformation inferred from previous studies on big area devices. The results show that the emission times of hole traps are not time-invariant (as normally presumed) but can increase due to evolution of the defect sites into more structurally stable forms. In addition, a new type of switching hole traps, exhibiting intermittent charging during stress and occasional increase in emission time by ~5 orders of magnitude, is observed.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124854178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898189
C. Hollerith, B. Kruger, Gurcan Gezerci, S. Pauthner, G. Zimmermann
As packages get smaller and more complex the necessity grows to do electrical modifications in packages to assist design process. Milling machines with accuracy of sub-μm enable a fast and effective approach to do such a kind of modification. In combination with other techniques, cutting of package connections as well as reconnecting of metal lines is possible.
{"title":"Advanced package circuit modification by μMilling","authors":"C. Hollerith, B. Kruger, Gurcan Gezerci, S. Pauthner, G. Zimmermann","doi":"10.1109/IPFA.2014.6898189","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898189","url":null,"abstract":"As packages get smaller and more complex the necessity grows to do electrical modifications in packages to assist design process. Milling machines with accuracy of sub-μm enable a fast and effective approach to do such a kind of modification. In combination with other techniques, cutting of package connections as well as reconnecting of metal lines is possible.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123486978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898143
T. P. Chua, C. H. Chong, K. Liew
Deep Vertical Interconnect Access (DVIA) was developed in the semiconductor industry for high performance technique which used to create advanced packages and advance integrated circuits. With its physically large diameter (~15um)and depth (~60um) substantial hours will be needed to mill entire DVI using Focosed Ion Beam (FIB) upon locating the failing DVIA. Thermally Induced Voltage Alterations (TIVA) technique has demonstrated significant capability for DVIA fault isolation. We had successfully narrow down failing DVIA inspection area to ~10um and manage to reduce FIB usage time from 4hrs to 2hrs. Save 50% on FIB usage time with novel technique for DVIA fault isolation.
{"title":"Novel technique for deep vertical interconnect access fault isolation","authors":"T. P. Chua, C. H. Chong, K. Liew","doi":"10.1109/IPFA.2014.6898143","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898143","url":null,"abstract":"Deep Vertical Interconnect Access (DVIA) was developed in the semiconductor industry for high performance technique which used to create advanced packages and advance integrated circuits. With its physically large diameter (~15um)and depth (~60um) substantial hours will be needed to mill entire DVI using Focosed Ion Beam (FIB) upon locating the failing DVIA. Thermally Induced Voltage Alterations (TIVA) technique has demonstrated significant capability for DVIA fault isolation. We had successfully narrow down failing DVIA inspection area to ~10um and manage to reduce FIB usage time from 4hrs to 2hrs. Save 50% on FIB usage time with novel technique for DVIA fault isolation.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898186
Andrew C. Sabate, Rowin V. Galarce
With the growing complexity of Integrated Circuit (IC) design having multiple metallization layers and copper wire bonded devices, most of the time backside fault isolation is a better approach. This paper evaluated wet chemical backside sample preparation as an alternative method for the traditional milling/polishing backside sample preparation.
{"title":"Characterization of wet chemical etching for effective backside sample preparation on devices with exposed pads","authors":"Andrew C. Sabate, Rowin V. Galarce","doi":"10.1109/IPFA.2014.6898186","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898186","url":null,"abstract":"With the growing complexity of Integrated Circuit (IC) design having multiple metallization layers and copper wire bonded devices, most of the time backside fault isolation is a better approach. This paper evaluated wet chemical backside sample preparation as an alternative method for the traditional milling/polishing backside sample preparation.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123405069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898170
J. Gambino, W. Bowe, D. M. Bronson, S. Adderly
X-Ray computed tomography (CT) can be useful in evaluating defects in through-silicon vias (TSVs). X-Ray CT images of two different TSV processes are presented; copper TSVs used for stacked memory on logic and tungsten TSVs used for power amplifiers. It is found that TSVs in the edge exclusion region are susceptible to defects from the TSV etch and TSV metallization processes.
{"title":"Imaging of through-silicon vias using X-Ray computed tomography","authors":"J. Gambino, W. Bowe, D. M. Bronson, S. Adderly","doi":"10.1109/IPFA.2014.6898170","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898170","url":null,"abstract":"X-Ray computed tomography (CT) can be useful in evaluating defects in through-silicon vias (TSVs). X-Ray CT images of two different TSV processes are presented; copper TSVs used for stacked memory on logic and tungsten TSVs used for power amplifiers. It is found that TSVs in the edge exclusion region are susceptible to defects from the TSV etch and TSV metallization processes.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"27 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126126570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-01DOI: 10.1109/IPFA.2014.6898178
Jason H. Lagar, Rudolf A. Sia, Marlyn C. Grancapal
Non-destructive inspection of Chip Scale Package-Ball Grid Array (CSP-BGA) package for anomalies related to continuity test failures specifically on the internal solder bumps, which connect the die to the Printed Circuit Board (PCB) substrate, is a challenge. Curve trace analysis can trace which internal solder bumps are involved but confirming its physical status needs more reliable and advanced nondestructive techniques. C-mode Scanning Acoustic Microscopy (CSAM) and Micro-Computed Tomography (μCT) scan were evaluated. Results of this paper showed that depending on the physical attribute of the bump anomaly, it could be seen either in μCT scan or CSAM. μCT scan will show those solder bumps with abnormal size or formation and CSAM using a 100 MHz transducer will show those bumps which fractured from its die pad connection. μCT scan can also be utilized for inspecting the metal traces, through hole vias and external solder balls of the PCB substrate. With these two non-destructive techniques, conventional destructive physical analysis techniques like mechanical cross-section, delayering and deprocessing are no longer required saving cycle time and cost. The samples are also saved for further electrical verification, fault isolation and destructive die-level physical analysis, if needed.
{"title":"Non-destructive techniques for internal solder bump inspection of chip scale package-ball grid array package","authors":"Jason H. Lagar, Rudolf A. Sia, Marlyn C. Grancapal","doi":"10.1109/IPFA.2014.6898178","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898178","url":null,"abstract":"Non-destructive inspection of Chip Scale Package-Ball Grid Array (CSP-BGA) package for anomalies related to continuity test failures specifically on the internal solder bumps, which connect the die to the Printed Circuit Board (PCB) substrate, is a challenge. Curve trace analysis can trace which internal solder bumps are involved but confirming its physical status needs more reliable and advanced nondestructive techniques. C-mode Scanning Acoustic Microscopy (CSAM) and Micro-Computed Tomography (μCT) scan were evaluated. Results of this paper showed that depending on the physical attribute of the bump anomaly, it could be seen either in μCT scan or CSAM. μCT scan will show those solder bumps with abnormal size or formation and CSAM using a 100 MHz transducer will show those bumps which fractured from its die pad connection. μCT scan can also be utilized for inspecting the metal traces, through hole vias and external solder balls of the PCB substrate. With these two non-destructive techniques, conventional destructive physical analysis techniques like mechanical cross-section, delayering and deprocessing are no longer required saving cycle time and cost. The samples are also saved for further electrical verification, fault isolation and destructive die-level physical analysis, if needed.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2014.6898196
E. Bury, R. Degraeve, M. Cho, B. Kaczer, W. Goes, T. Grasser, N. Horiguchi, G. Groeseneken
Recently, several experimental groups have found correlations in gate and drain current fluctuations. In this paper, by studying single trap activated leakage paths, both evidence and a refined 4-state defect model are provided, ascribing additional gate tunneling current in nm-FETs to thermally activated defect states. The model is capable of explaining both positive and negative correlations in gate and drain current RTN, but also the mostly uncorrelated nature of these drain and gate RTN signals.
{"title":"Study of (correlated) trap sites in SILC, BTI and RTN in SiON and HKMG devices","authors":"E. Bury, R. Degraeve, M. Cho, B. Kaczer, W. Goes, T. Grasser, N. Horiguchi, G. Groeseneken","doi":"10.1109/IPFA.2014.6898196","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898196","url":null,"abstract":"Recently, several experimental groups have found correlations in gate and drain current fluctuations. In this paper, by studying single trap activated leakage paths, both evidence and a refined 4-state defect model are provided, ascribing additional gate tunneling current in nm-FETs to thermally activated defect states. The model is capable of explaining both positive and negative correlations in gate and drain current RTN, but also the mostly uncorrelated nature of these drain and gate RTN signals.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"126 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IPFA.2014.6898206
Chenglin Wu, Tengfei Jiang, J. Im, K. Liechti, Rui Huang, P. Ho
In this paper, the effects of Cu microstructure on the mechanical properties of TSV and via extrusion are studied using two types of through-silicon vias (TSVs) with different grain size distributions. A direct correlation is found between the Cu grain size and the mechanical properties of the TSVs. An analytical model is used to explore the relationship between the mechanical properties and via extrusion. The results show that small and uniform grains in the Cu vias led to smaller via extrusion. Such grain structures are effective for reducing via extrusion failure to improve TSV reliability.
{"title":"Material characterization and failure analysis of through-silicon vias","authors":"Chenglin Wu, Tengfei Jiang, J. Im, K. Liechti, Rui Huang, P. Ho","doi":"10.1109/IPFA.2014.6898206","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898206","url":null,"abstract":"In this paper, the effects of Cu microstructure on the mechanical properties of TSV and via extrusion are studied using two types of through-silicon vias (TSVs) with different grain size distributions. A direct correlation is found between the Cu grain size and the mechanical properties of the TSVs. An analytical model is used to explore the relationship between the mechanical properties and via extrusion. The results show that small and uniform grains in the Cu vias led to smaller via extrusion. Such grain structures are effective for reducing via extrusion failure to improve TSV reliability.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：