Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898174
Z. Oh, F. Foo, W. Qiu
This paper describes the failure analysis approach in search of the root cause behind a series of short failures after high-temperature storage (HTS) test at 150°C. Findings revealed that UBM consumption by tin and the eventual disintegration allowed solder diffusion into the die circuitries resulting in the massive short failures.
{"title":"Detailed package failure analysis on short failures after high temperature storage","authors":"Z. Oh, F. Foo, W. Qiu","doi":"10.1109/IPFA.2014.6898174","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898174","url":null,"abstract":"This paper describes the failure analysis approach in search of the root cause behind a series of short failures after high-temperature storage (HTS) test at 150°C. Findings revealed that UBM consumption by tin and the eventual disintegration allowed solder diffusion into the die circuitries resulting in the massive short failures.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"27 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114121877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898181
W. N. Putra, A. Trigg, H. Li, C. Gan
Microstructure analysis plays an important role in the reliability study of copper Through-Silicon Vias (TSVs). While conventional 2-dimensional (2D) Electron Back-Scatter Diffraction (EBSD) is a useful technique, 3-dimensional (3D) EBSD characterization provides a more accurate picture of the TSV microstructure. Information that is missing in 2D observations, such as grain shape and volume, can be obtained from the 3D technique. In this study, we did 3D characterizations by serial sectioning of the TSV samples and mapped the microstructure on each slice. These maps were then reconstructed into 3D images. From the result, it showed that the increase in Cu grain volume after thermal annealing can be up to 99%, as compared with 55% and 67% increase in calculated grain volume as determined from single and averaged 2D EBSD maps, respectively.
{"title":"3D EBAD characterizations on copper TSV for 3D interconnections","authors":"W. N. Putra, A. Trigg, H. Li, C. Gan","doi":"10.1109/IPFA.2014.6898181","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898181","url":null,"abstract":"Microstructure analysis plays an important role in the reliability study of copper Through-Silicon Vias (TSVs). While conventional 2-dimensional (2D) Electron Back-Scatter Diffraction (EBSD) is a useful technique, 3-dimensional (3D) EBSD characterization provides a more accurate picture of the TSV microstructure. Information that is missing in 2D observations, such as grain shape and volume, can be obtained from the 3D technique. In this study, we did 3D characterizations by serial sectioning of the TSV samples and mapped the microstructure on each slice. These maps were then reconstructed into 3D images. From the result, it showed that the increase in Cu grain volume after thermal annealing can be up to 99%, as compared with 55% and 67% increase in calculated grain volume as determined from single and averaged 2D EBSD maps, respectively.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116070711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898138
L. Yeoh, Kok-Cheng Chong, Susan X. Li
Reliability of PCB is of paramount importance during high temperature application in the field. Good integration among all PCB components is essential to ensure robust PCB performance. Imperfection in the PCB assembly may activate ion diffusion and induce board level contamination, which are detrimental to the device functionality. In this paper, we show that magnesium ions can be thermal-electrically excited from a heat fin. Under the influence of electric field, these ions diffuse through thermal glue and cause fatal failure to the adjacent electronic device. The movement of the ions is governed by various diffusion mechanisms such as interstitial diffusion, grain boundary diffusion, and surface diffusion. The PCB assembly process must be properly controlled and by isolating the thermal glue from the heat fin, the failure risk can be reduced.
{"title":"Thermal ions diffusion on printed circuit board","authors":"L. Yeoh, Kok-Cheng Chong, Susan X. Li","doi":"10.1109/IPFA.2014.6898138","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898138","url":null,"abstract":"Reliability of PCB is of paramount importance during high temperature application in the field. Good integration among all PCB components is essential to ensure robust PCB performance. Imperfection in the PCB assembly may activate ion diffusion and induce board level contamination, which are detrimental to the device functionality. In this paper, we show that magnesium ions can be thermal-electrically excited from a heat fin. Under the influence of electric field, these ions diffuse through thermal glue and cause fatal failure to the adjacent electronic device. The movement of the ions is governed by various diffusion mechanisms such as interstitial diffusion, grain boundary diffusion, and surface diffusion. The PCB assembly process must be properly controlled and by isolating the thermal glue from the heat fin, the failure risk can be reduced.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115273595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898201
N. Dayanand, A. Quah, C. Q. Chen, S. Neo, G. Ang, M. Gunawardana, Z. Mai, J. Lam
This paper describes the effectiveness of using light induced Current Imaging - Atomic Force Microscopy (CI-AFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and non-gated diode, as a result enhanced localization of gate to source/drain short.
{"title":"Defect localization enhancement using light induced CI-AFP","authors":"N. Dayanand, A. Quah, C. Q. Chen, S. Neo, G. Ang, M. Gunawardana, Z. Mai, J. Lam","doi":"10.1109/IPFA.2014.6898201","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898201","url":null,"abstract":"This paper describes the effectiveness of using light induced Current Imaging - Atomic Force Microscopy (CI-AFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and non-gated diode, as a result enhanced localization of gate to source/drain short.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124623621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898207
Zhigang Song
Demand for high speed and more function microelectronic devices has driven semiconductor industry to continue developing technologies with ever-shrinking geometry. During technology development, Static Random Access Memory (SRAM) is often chosen as the process qualification and yield learning vehicle. Thus SRAM failure analysis is the major activity in any microelectronic device failure analysis lab. Conventional physical failure analysis in old technology nodes has achieved high success rate since the SRAM bitcell failures can be precisely localized by functional test and the defect causing such failures is within the failing bitcells. However, As SRAM feature size decreases with technology scaling down, the size of the defect causing SRAM failure also scales down. Some of the defects are so tiny that they are invisible in ultra-high resolution SEM. On the other hand, the SRAM bitcell number greatly increases, and thus the SRAM design, especially address decoder scheme becomes more complex. More and complicated SRAM logic type failures arise. Therefore, the conventional physical failure analysis has faced increasing challenges and encountered low success rate. This paper will talk about how SRAM failure analysis evolves to maintain high success rate.
{"title":"SRAM failure analysis evolution driven by technology scaling","authors":"Zhigang Song","doi":"10.1109/IPFA.2014.6898207","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898207","url":null,"abstract":"Demand for high speed and more function microelectronic devices has driven semiconductor industry to continue developing technologies with ever-shrinking geometry. During technology development, Static Random Access Memory (SRAM) is often chosen as the process qualification and yield learning vehicle. Thus SRAM failure analysis is the major activity in any microelectronic device failure analysis lab. Conventional physical failure analysis in old technology nodes has achieved high success rate since the SRAM bitcell failures can be precisely localized by functional test and the defect causing such failures is within the failing bitcells. However, As SRAM feature size decreases with technology scaling down, the size of the defect causing SRAM failure also scales down. Some of the defects are so tiny that they are invisible in ultra-high resolution SEM. On the other hand, the SRAM bitcell number greatly increases, and thus the SRAM design, especially address decoder scheme becomes more complex. More and complicated SRAM logic type failures arise. Therefore, the conventional physical failure analysis has faced increasing challenges and encountered low success rate. This paper will talk about how SRAM failure analysis evolves to maintain high success rate.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898132
Gaojie Wen
Microprobe analysis plays an important role in failure analysis as it could reveal the failed signal directly and help to isolate the final failed device. But when met unexpected high impedance circuit, the real signal couldn't be measured as high impedance site was sensitive to probe needle and strong light. One real Case and experiment was studied in this paper to show how high impedance circuit was sensitive and how to find the root cause of this unstable failure efficiently.
{"title":"Study on sensitive character of unexpected high impedance circuit in VLSI failure analysis","authors":"Gaojie Wen","doi":"10.1109/IPFA.2014.6898132","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898132","url":null,"abstract":"Microprobe analysis plays an important role in failure analysis as it could reveal the failed signal directly and help to isolate the final failed device. But when met unexpected high impedance circuit, the real signal couldn't be measured as high impedance site was sensitive to probe needle and strong light. One real Case and experiment was studied in this paper to show how high impedance circuit was sensitive and how to find the root cause of this unstable failure efficiently.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116692419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898169
Jinglong Li, C. Qi, Y. Che, Quande Zhang, Horse L. Ma, Jonathan Liu, M. Masuda, B. Liu
Ohmic contacts must be made in any semiconductor device or integrated circuits(IC). Contact failures usually are related to high resistance or open. However, sometimes the defective contact may be Schottky character instead of ohmic contact. In this paper, a case study on such a contact failure is discussed.
{"title":"A case study on the defective contact with Schottky junction character","authors":"Jinglong Li, C. Qi, Y. Che, Quande Zhang, Horse L. Ma, Jonathan Liu, M. Masuda, B. Liu","doi":"10.1109/IPFA.2014.6898169","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898169","url":null,"abstract":"Ohmic contacts must be made in any semiconductor device or integrated circuits(IC). Contact failures usually are related to high resistance or open. However, sometimes the defective contact may be Schottky character instead of ohmic contact. In this paper, a case study on such a contact failure is discussed.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898156
Jack Yi Jie Ng, Liew Chiun Ning, Khoo Khai Ling
This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.
本文介绍了基于28nm现场可编程逻辑阵列(FPGA)体硅技术的两个案例，重点介绍了利用本地软件(Interconnect Test Generation, ITG)调试器和Functional Interface)定位后端互连和金属化缺陷的新方法，然后进行了广泛的布局研究、可疑缺陷节点识别、并行研磨和扫描发射显微镜(SEM)检查。
{"title":"Back-end defect localization for 28nm FPGA","authors":"Jack Yi Jie Ng, Liew Chiun Ning, Khoo Khai Ling","doi":"10.1109/IPFA.2014.6898156","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898156","url":null,"abstract":"This paper presents two case studies, which are based on 28nm Field Programmable Logic Array (FPGA) bulk silicon technology, to highlight the novel approach on locating back-end interconnects and metallization defect by utilizing local software, which are Interconnect Test Generation (ITG) debugger and Functional Interface, then follow by extensive layout study, suspected defect node identification, parallel lapping and Scanning Emission Microscope (SEM) inspection.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127484465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898163
S. Hong, Z. X. Hua, Chng Kheaw Chung, A. Chin
With the presence of Buried Oxide (BOX) layer in Silicon On Insulator (SOI) wafer, local defect isolation by using Conductive Atomic Force Microscopy (C-AFM) in die-level failure analysis is not feasible as electric current is unable to pass through the BOX layer. To overcome this limitation, Scanning Capacitance Microscopy (SCM) is used to perform local defect isolation in die-level failure analysis. Investigation was performed to evaluate the type of SCM probes which gave high signal sensitivity. Case study on sample with leakage through the SOI substrate is demonstrated and presented in this paper.
{"title":"Application of scanning capacitance microscopy on SOI wafer in die-level failure analysis","authors":"S. Hong, Z. X. Hua, Chng Kheaw Chung, A. Chin","doi":"10.1109/IPFA.2014.6898163","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898163","url":null,"abstract":"With the presence of Buried Oxide (BOX) layer in Silicon On Insulator (SOI) wafer, local defect isolation by using Conductive Atomic Force Microscopy (C-AFM) in die-level failure analysis is not feasible as electric current is unable to pass through the BOX layer. To overcome this limitation, Scanning Capacitance Microscopy (SCM) is used to perform local defect isolation in die-level failure analysis. Investigation was performed to evaluate the type of SCM probes which gave high signal sensitivity. Case study on sample with leakage through the SOI substrate is demonstrated and presented in this paper.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128518623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898128
Hun-Seong Choi, Yongwoon Han, I. Chung
This paper presents MOSFET implant failure analysis using plane view scanning capacitance microscopy (PVSCM) at silicon substrate level. Failing transistors are characterized by nano-probing (NP) at contact level. The cause of failure was deduced from the combination of PVSCM, IV characteristics from NP measurement, and TEM cross-section analysis. Technology computer aided design (TCAD) simulation was implemented for failure modeling and SCM data verification. Failure analysis case studies of samples manufactured by 65 nm and 45 nm process are presented.
{"title":"MOSFET implant failure analysis using plane-view scanning capacitance microscopy coupled with nano-probing and TCAD modeling","authors":"Hun-Seong Choi, Yongwoon Han, I. Chung","doi":"10.1109/IPFA.2014.6898128","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898128","url":null,"abstract":"This paper presents MOSFET implant failure analysis using plane view scanning capacitance microscopy (PVSCM) at silicon substrate level. Failing transistors are characterized by nano-probing (NP) at contact level. The cause of failure was deduced from the combination of PVSCM, IV characteristics from NP measurement, and TEM cross-section analysis. Technology computer aided design (TCAD) simulation was implemented for failure modeling and SCM data verification. Failure analysis case studies of samples manufactured by 65 nm and 45 nm process are presented.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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