Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898209
M. Pecht, E. George, A. Vasan, P. Chauhan
The rapid evolution of electronic products has resulted in numerous choices for customers. This has made for intense competition between manufacturers to reduce costs and minimize the time to market for their products. One bottle-neck in getting products to market is the qualification process, which has traditionally been time-consuming and often inadequate to prevent failures in field. In particular, in the past decade, there have been significant numbers of microelectronic devices that have passed qualification tests but failed in the field. The resulting costs of these failures have been in the billions of dollars. Thus, there is a need to develop approaches to qualification methodologies that quicken the development time but also prevent product failures in the field. This paper discusses the current state of qualification practices in the electronics industry. Then, an alternative approach, called fusion prognostics, for qualification is presented that can make the process more efficient and cost-effective. This approach involves an in-situ qualification process that incorporates a fusion of machine learning techniques and physics-of-failure based prognostics. The machine learning techniques are used to monitor the degradation behavior during testing. On the other hand, the physics-of-failure techniques identify critical failure mechanisms and the acceleration factors.
{"title":"Fusion prognostics-based qualification of microelectronic devices","authors":"M. Pecht, E. George, A. Vasan, P. Chauhan","doi":"10.1109/IPFA.2014.6898209","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898209","url":null,"abstract":"The rapid evolution of electronic products has resulted in numerous choices for customers. This has made for intense competition between manufacturers to reduce costs and minimize the time to market for their products. One bottle-neck in getting products to market is the qualification process, which has traditionally been time-consuming and often inadequate to prevent failures in field. In particular, in the past decade, there have been significant numbers of microelectronic devices that have passed qualification tests but failed in the field. The resulting costs of these failures have been in the billions of dollars. Thus, there is a need to develop approaches to qualification methodologies that quicken the development time but also prevent product failures in the field. This paper discusses the current state of qualification practices in the electronics industry. Then, an alternative approach, called fusion prognostics, for qualification is presented that can make the process more efficient and cost-effective. This approach involves an in-situ qualification process that incorporates a fusion of machine learning techniques and physics-of-failure based prognostics. The machine learning techniques are used to monitor the degradation behavior during testing. On the other hand, the physics-of-failure techniques identify critical failure mechanisms and the acceleration factors.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898126
I. Nam, J. Lim, H. Hwang, K. Cho, J. Choi
Correctable errors, almost single bit errors, can be induced from random data transition in DRAM. In the system, most of CEs are corrected by error correction code, but there is intermittent system down. Several literatures have reported that noise generated from share circuitries is regarded as a cause of soft failure. Noisy environments are one of the unavoidable factors in the high speed, high density, and low power DRAM. For the purpose of finding out noise source, we investigated states of share circuitries with random data transition. BLSA, power transistor, power line, and common plate were also researched with DDR3 DRAMs. A simple model was proposed with the quantitative analysis. Results show that the soft failure occurs when unexpected combination of noise factors happen at once, because the revealed erratic bits have similar characteristics of normal bits, except for the influence on noise.
{"title":"Quantitative analysis for noise generated from share circuitries within DDR3 DRAM","authors":"I. Nam, J. Lim, H. Hwang, K. Cho, J. Choi","doi":"10.1109/IPFA.2014.6898126","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898126","url":null,"abstract":"Correctable errors, almost single bit errors, can be induced from random data transition in DRAM. In the system, most of CEs are corrected by error correction code, but there is intermittent system down. Several literatures have reported that noise generated from share circuitries is regarded as a cause of soft failure. Noisy environments are one of the unavoidable factors in the high speed, high density, and low power DRAM. For the purpose of finding out noise source, we investigated states of share circuitries with random data transition. BLSA, power transistor, power line, and common plate were also researched with DDR3 DRAMs. A simple model was proposed with the quantitative analysis. Results show that the soft failure occurs when unexpected combination of noise factors happen at once, because the revealed erratic bits have similar characteristics of normal bits, except for the influence on noise.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898127
Gaojie Wen
Resistor plays a key role in circuit designer's view as it was indispensable for the whole circuit function. But for integrated circuit failure analysis, the effect of resistor contained both guidance and as well as blocks to find the root cause. The obstruction effect of resistor was seldom studied in failure analysis. This paper presented how resistor to be block for failure analysis. And how to conquer the obstruction effect was also studied which will be helpful in analyzing complicated failure cases.
{"title":"Fault isolation by conquering obstruction effect of resistor in complex cases analysis","authors":"Gaojie Wen","doi":"10.1109/IPFA.2014.6898127","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898127","url":null,"abstract":"Resistor plays a key role in circuit designer's view as it was indispensable for the whole circuit function. But for integrated circuit failure analysis, the effect of resistor contained both guidance and as well as blocks to find the root cause. The obstruction effect of resistor was seldom studied in failure analysis. This paper presented how resistor to be block for failure analysis. And how to conquer the obstruction effect was also studied which will be helpful in analyzing complicated failure cases.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898195
R. Mendaros, M. Marcelo
One of the coating materials that is used to reduced electron charging effect during Scanning Electron Microscope (SEM) imaging is Platinum (Pt). Removing Pt coating for parts requiring further electrical testing or deprocessing has been a challenge in failure analysis. This paper discusses the established methodology in removing Pt coating using the ICP-RIE sputter etching technique.
{"title":"ICP-RIE Platinum (Pt) sputter etching","authors":"R. Mendaros, M. Marcelo","doi":"10.1109/IPFA.2014.6898195","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898195","url":null,"abstract":"One of the coating materials that is used to reduced electron charging effect during Scanning Electron Microscope (SEM) imaging is Platinum (Pt). Removing Pt coating for parts requiring further electrical testing or deprocessing has been a challenge in failure analysis. This paper discusses the established methodology in removing Pt coating using the ICP-RIE sputter etching technique.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898148
S. Y. Gan, Lokman Alias, W. Ng
The isolation test condition and the root cause of isolation failures are always the main concerns of the manufacturers and customers. Several of studies have been carried out to evaluate the optimize settings so that the device meets the required quality standard. The company is benefited from the isolation test activity which is also known as Dielectric Withstand Voltage test or Isolation Test, to enable the screening of the mold compound rejects electrically. The test is used to verify the insulation of the mold compound whether it is sufficient enough or not to protect the user from electric shock by measuring and checking the mold compound compactness so that any reject which lead to mold voids can be filtered out. `Mold voids' is actually referring to the air pockets trap within the mold compound itself which is generated from the incompactness of mold process. This is where failure analysis comes in to reveal the underlying root cause failure of the package insulation. Different kinds of method have been used here, for example, X-ray, SAM (Scanning Acoustic Microscopy), SEM (Scanning Electron Microscopy), electrical test verifications, cross section and etcetera.
{"title":"A study of isolation test on FullPAK device","authors":"S. Y. Gan, Lokman Alias, W. Ng","doi":"10.1109/IPFA.2014.6898148","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898148","url":null,"abstract":"The isolation test condition and the root cause of isolation failures are always the main concerns of the manufacturers and customers. Several of studies have been carried out to evaluate the optimize settings so that the device meets the required quality standard. The company is benefited from the isolation test activity which is also known as Dielectric Withstand Voltage test or Isolation Test, to enable the screening of the mold compound rejects electrically. The test is used to verify the insulation of the mold compound whether it is sufficient enough or not to protect the user from electric shock by measuring and checking the mold compound compactness so that any reject which lead to mold voids can be filtered out. `Mold voids' is actually referring to the air pockets trap within the mold compound itself which is generated from the incompactness of mold process. This is where failure analysis comes in to reveal the underlying root cause failure of the package insulation. Different kinds of method have been used here, for example, X-ray, SAM (Scanning Acoustic Microscopy), SEM (Scanning Electron Microscopy), electrical test verifications, cross section and etcetera.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114641405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898154
M. K. Dawood, T. H. Ng, P. K. Tan, H. Tan, S. James, P. S. Limin, H. H. Yap, J. Lam, Z. Mai
It is becoming increasingly challenging for conventional failure analysis methods to identify the failure mechanism at circuit level in an integrated chip. This paper demonstrates the utilization of nanoprobing for on-chip device and circuit debugging for defect localization at circuit level. FIB circuit edit was first performed to isolate the intended circuit. Next nanoprobing was performed on higher metal layer to identify the cause of failure. Nanoprobing was then performed at the contact level to verify the source of failure.
{"title":"On-chip device and circuit diagnostics on advanced technology nodes by nanoprobing","authors":"M. K. Dawood, T. H. Ng, P. K. Tan, H. Tan, S. James, P. S. Limin, H. H. Yap, J. Lam, Z. Mai","doi":"10.1109/IPFA.2014.6898154","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898154","url":null,"abstract":"It is becoming increasingly challenging for conventional failure analysis methods to identify the failure mechanism at circuit level in an integrated chip. This paper demonstrates the utilization of nanoprobing for on-chip device and circuit debugging for defect localization at circuit level. FIB circuit edit was first performed to isolate the intended circuit. Next nanoprobing was performed on higher metal layer to identify the cause of failure. Nanoprobing was then performed at the contact level to verify the source of failure.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":" 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113951304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898123
W. Yeh, W. Chang, Po-Ying Chen, Cheng-li Lin
In this work, we investigate the impact of junction dose distribution (LDD/halo) on device characteristic variation and symmetry for ultra-thin body and bulk oxide silicon on insulator (UTBB SOI) nMOSFET. The device performance and hot carrier induced degradations have also been examined. High junction doping profile will enhances the device's driving capability and sub-threshold swing, but makes the transistor forward and reverse characteristics unsymmetrical. Compared to high dose junction profile UTBB-SOI device, low dose junction profile device is less sensitive to substrate bias effect. After hot carrier stressing, low junction dose device with lower impact ionization exhibits better device reliability than high junction dose one.
{"title":"Junction induced variation and reliability for ultra-thin-body and bulk oxide MOSFETs","authors":"W. Yeh, W. Chang, Po-Ying Chen, Cheng-li Lin","doi":"10.1109/IPFA.2014.6898123","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898123","url":null,"abstract":"In this work, we investigate the impact of junction dose distribution (LDD/halo) on device characteristic variation and symmetry for ultra-thin body and bulk oxide silicon on insulator (UTBB SOI) nMOSFET. The device performance and hot carrier induced degradations have also been examined. High junction doping profile will enhances the device's driving capability and sub-threshold swing, but makes the transistor forward and reverse characteristics unsymmetrical. Compared to high dose junction profile UTBB-SOI device, low dose junction profile device is less sensitive to substrate bias effect. After hot carrier stressing, low junction dose device with lower impact ionization exhibits better device reliability than high junction dose one.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128064521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898135
Chenghui Tang, Shin Chia Lin, Yi-Chen Lin, M. Hsiao, Yau Shan Wu, Chi Lin
Embedded memory is an integrated on-chip memory that supports the logic core to accomplish intended functions. High-performance embedded memory is a key component in VLSI, because of its high-speed and wide bus-width capability, which eliminates inter-chip communication. In this paper, embedded memory device and CMOS logic is integrated on-chip and it is a more complex of process technology compared with stand-alone memory. For the process engineering, we are always confronted with many problems, especially, the dislocation that causes some failures.
{"title":"Case study of embedded memory failure analysis for dislocation issue","authors":"Chenghui Tang, Shin Chia Lin, Yi-Chen Lin, M. Hsiao, Yau Shan Wu, Chi Lin","doi":"10.1109/IPFA.2014.6898135","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898135","url":null,"abstract":"Embedded memory is an integrated on-chip memory that supports the logic core to accomplish intended functions. High-performance embedded memory is a key component in VLSI, because of its high-speed and wide bus-width capability, which eliminates inter-chip communication. In this paper, embedded memory device and CMOS logic is integrated on-chip and it is a more complex of process technology compared with stand-alone memory. For the process engineering, we are always confronted with many problems, especially, the dislocation that causes some failures.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127383122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898137
L. Filipovic, R. L. de Orio, S. Selberherr
The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and large sidewall scallops. The resulting geometries are imported into a finite element tool in order to analyze the performance and reliability of the devices. The electrical parameters of the TSVs are shown to vary when scallops are present for both types of TSVs. In addition, the maximum thermo-mechanical stress increases in the presence of scallops, while the average stress along the interfaces remains relatively unchanged. Electromigration analyses were also performed on the structures in order to determine stress development during the early stages of operation. It was found that the filled TSV with scalloped sidewalls experiences a higher current density and suffers from increased stress, while the sidewall scallops do not cause variation in the stress of open tungsten TSVs. The open tungsten TSVs experience most Electromigration-induced stress in the connecting metal layers and not along the sidewall.
{"title":"Effects of sidewall scallops on the performance and reliability of filled copper and open tungsten TSVs","authors":"L. Filipovic, R. L. de Orio, S. Selberherr","doi":"10.1109/IPFA.2014.6898137","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898137","url":null,"abstract":"The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and large sidewall scallops. The resulting geometries are imported into a finite element tool in order to analyze the performance and reliability of the devices. The electrical parameters of the TSVs are shown to vary when scallops are present for both types of TSVs. In addition, the maximum thermo-mechanical stress increases in the presence of scallops, while the average stress along the interfaces remains relatively unchanged. Electromigration analyses were also performed on the structures in order to determine stress development during the early stages of operation. It was found that the filled TSV with scalloped sidewalls experiences a higher current density and suffers from increased stress, while the sidewall scallops do not cause variation in the stress of open tungsten TSVs. The open tungsten TSVs experience most Electromigration-induced stress in the connecting metal layers and not along the sidewall.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129333089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898151
Shen Yiqiang, Chen Yixin, Lee Hwang Sheng, Chow Shue Yin, X. Z. Xiang, H. Younan, Li Xiaomin
A Sn oxide layer on the surface of Sn solder balls plays an important role in the semiconductor packaging industry. This paper shows a comprehensive analysis of the Sn oxide layer by XPS depth profiles. The distribution of Sn with different oxidation states can be derived from curves fitting Sn3d5/2 peaks. Moreover, the oxide layer thicknesses obtained from XPS demonstrate a linear correlation with the values from TEM measurements.
{"title":"XPS and TEM studies of oxidation states on Sn solder ball","authors":"Shen Yiqiang, Chen Yixin, Lee Hwang Sheng, Chow Shue Yin, X. Z. Xiang, H. Younan, Li Xiaomin","doi":"10.1109/IPFA.2014.6898151","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898151","url":null,"abstract":"A Sn oxide layer on the surface of Sn solder balls plays an important role in the semiconductor packaging industry. This paper shows a comprehensive analysis of the Sn oxide layer by XPS depth profiles. The distribution of Sn with different oxidation states can be derived from curves fitting Sn3d5/2 peaks. Moreover, the oxide layer thicknesses obtained from XPS demonstrate a linear correlation with the values from TEM measurements.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125705620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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