Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898176
S. Goh, G. F. You, B. Yeoh, H. Hao, N. Chung, C. Yap, J. Lam
Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.
{"title":"Wafer-level fault isolation approach to debug integrated circuits JTAG failures","authors":"S. Goh, G. F. You, B. Yeoh, H. Hao, N. Chung, C. Yap, J. Lam","doi":"10.1109/IPFA.2014.6898176","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898176","url":null,"abstract":"Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131160191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898161
Huang Yamin, H. Tan, D. Wang, J. Lam, Z. Mai
Time-dependent dielectric breakdown (TDDB) of ultra-low-k materials is one of the most critical reliability issues in leading edge Cu/low-k technology due to the weak intrinsic breakdown strength of ultra-low-k materials as compared to that of SiO2 dielectrics. With continuous device dimension scaling, this problem is further exacerbated for Cu/ultra-low-k interconnects. There are different TDDB models proposed to address this issue, however, there is no direct evidence to get into the failure mechanism. The key technical reason is that the damage to the dielectric material properties is not able to be monitored during the TDDB test. In this paper, we will describe the experiments and the setup used to capture the dielectric bonding damage during the reliability test. Raman and FTIR complimentary vibrational spectroscopy were used to detect the dielectric bonding on the pattern wafer, which has historically been a challenge for current leading edge Cu/low k or ultra-low-k technologies due to the influence of the metal interconnects and the thin dielectric layer. From our experiments, we successfully detected the TDDB degradation behavior of ultra-low-k dielectric in Cu/ultra-low-k interconnects and found the intrinsic degradation of the ultra-low-k dielectric. Further study on the damaged structures with TEM analysis revealed that the Ta ions migrated from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. In addition, no out-diffusion of Cu ions was observed in our TEM investigation on Cu/Ta/TaN/SiCOH structures.
{"title":"Experiments and results of Raman and FTIR complementary vibrational spectroscopy for IC reliability failure analysis","authors":"Huang Yamin, H. Tan, D. Wang, J. Lam, Z. Mai","doi":"10.1109/IPFA.2014.6898161","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898161","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) of ultra-low-k materials is one of the most critical reliability issues in leading edge Cu/low-k technology due to the weak intrinsic breakdown strength of ultra-low-k materials as compared to that of SiO2 dielectrics. With continuous device dimension scaling, this problem is further exacerbated for Cu/ultra-low-k interconnects. There are different TDDB models proposed to address this issue, however, there is no direct evidence to get into the failure mechanism. The key technical reason is that the damage to the dielectric material properties is not able to be monitored during the TDDB test. In this paper, we will describe the experiments and the setup used to capture the dielectric bonding damage during the reliability test. Raman and FTIR complimentary vibrational spectroscopy were used to detect the dielectric bonding on the pattern wafer, which has historically been a challenge for current leading edge Cu/low k or ultra-low-k technologies due to the influence of the metal interconnects and the thin dielectric layer. From our experiments, we successfully detected the TDDB degradation behavior of ultra-low-k dielectric in Cu/ultra-low-k interconnects and found the intrinsic degradation of the ultra-low-k dielectric. Further study on the damaged structures with TEM analysis revealed that the Ta ions migrated from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. In addition, no out-diffusion of Cu ions was observed in our TEM investigation on Cu/Ta/TaN/SiCOH structures.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131925338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898141
Nicolas Courjault, Fulvia Infante, V. Bley, T. Lebey, P. Perdu
Magnetic Microscopy has demonstrated all its functionality for 2D component thanks to its ability to image current density distribution from magnetic field. At the “More than Moore” age, we need to improve our capabilities to detect and localize failure in 3D components. Unfortunately, it is not possible to directly image 3D current density from a magnetic field scan. 3D conductive path information, that could come from design, and failure assumptions are also needed. In this paper, a new approach based on X-Ray Computed Tomography that bypasses the need of design information and failure site assumptions is presented and its results are discussed.
{"title":"Improvement of 3D current mapping by coupling magnetic microscopy and X-Ray computed tomography","authors":"Nicolas Courjault, Fulvia Infante, V. Bley, T. Lebey, P. Perdu","doi":"10.1109/IPFA.2014.6898141","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898141","url":null,"abstract":"Magnetic Microscopy has demonstrated all its functionality for 2D component thanks to its ability to image current density distribution from magnetic field. At the “More than Moore” age, we need to improve our capabilities to detect and localize failure in 3D components. Unfortunately, it is not possible to directly image 3D current density from a magnetic field scan. 3D conductive path information, that could come from design, and failure assumptions are also needed. In this paper, a new approach based on X-Ray Computed Tomography that bypasses the need of design information and failure site assumptions is presented and its results are discussed.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898142
P. Sharma, Tai Shan Chiu, S. Biring, T. Chang, C. Chu, Y. Hsieh
We report sample preparation and FIB-SEM investigation of polymer-microlens/CFA arrays of CMOS image sensor for investigating possible nanoscale voids. Polymer staining was employed to delineate boundaries of color filters and microlenses. Newly developed in-house auto-metrology software was used for dimension and uniformity study of SEM images of microlenses.
{"title":"FIB-SEM investigation and auto-metrology of polymer-microlens/CFA arrays of CMOS image sensor","authors":"P. Sharma, Tai Shan Chiu, S. Biring, T. Chang, C. Chu, Y. Hsieh","doi":"10.1109/IPFA.2014.6898142","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898142","url":null,"abstract":"We report sample preparation and FIB-SEM investigation of polymer-microlens/CFA arrays of CMOS image sensor for investigating possible nanoscale voids. Polymer staining was employed to delineate boundaries of color filters and microlenses. Newly developed in-house auto-metrology software was used for dimension and uniformity study of SEM images of microlenses.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898133
Hongwei Huang, Winnie Wei, J. J. Xin, Candy Liu, Luke Wu, Clieve Dai, Pinglung Liao, Wei Xu
For failure analysis, most of defects are visible to imaging tools, such as OM, SEM, FIB, TEM etc. However, there are still lots of non-visible defects which cannot be caught by these tools. As complexity for such non-visible defect failure analysis is much high, FA engineers were often puzzled where to begin from. Two such cases were presented in this paper with solutions. The systematic methods for these cases include electrical data mining, brainstorming or fish-bone diagram method to list all failure possibilities, and then proper characterization tools or methods were used to identify and verify the hypotheses. Finally DOE (design of experiments) was used to verify the root cause. As a result, phosphorus contamination was found for embedded Flash products' MOS threshold voltage shift issue, and higher substrate oxygen concentration for Power MOS products source to drain low breakdown voltage issue.
对于失效分析，大多数缺陷是可见的成像工具，如OM, SEM, FIB, TEM等。然而，仍然有许多不可见的缺陷不能被这些工具捕获。由于这种不可见缺陷失效分析的复杂性非常高，故障分析工程师常常困惑于从何入手。本文给出了两个这样的例子，并给出了解决方案。这些案例的系统方法包括电气数据挖掘，头脑风暴或鱼骨图法列出所有故障可能性，然后使用适当的表征工具或方法来识别和验证假设。最后采用DOE (design of experiments)验证了根本原因。结果发现，磷污染导致嵌入式Flash产品的MOS阈值电压偏移问题，而Power MOS产品源的衬底氧浓度较高导致击穿电压低问题。
{"title":"Systematic methods to identify and verify non-visible defects in silicon substrate","authors":"Hongwei Huang, Winnie Wei, J. J. Xin, Candy Liu, Luke Wu, Clieve Dai, Pinglung Liao, Wei Xu","doi":"10.1109/IPFA.2014.6898133","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898133","url":null,"abstract":"For failure analysis, most of defects are visible to imaging tools, such as OM, SEM, FIB, TEM etc. However, there are still lots of non-visible defects which cannot be caught by these tools. As complexity for such non-visible defect failure analysis is much high, FA engineers were often puzzled where to begin from. Two such cases were presented in this paper with solutions. The systematic methods for these cases include electrical data mining, brainstorming or fish-bone diagram method to list all failure possibilities, and then proper characterization tools or methods were used to identify and verify the hypotheses. Finally DOE (design of experiments) was used to verify the root cause. As a result, phosphorus contamination was found for embedded Flash products' MOS threshold voltage shift issue, and higher substrate oxygen concentration for Power MOS products source to drain low breakdown voltage issue.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898165
M. Rebai, F. Darracq, Jean-Paul Guillet, D. Lewis, P. Perdu, K. Sanchez
Electro-Optical Probing (EOP) has shown its efficiency in the world of failure analysis. The different external physical parameters effects, especially the temperature, on the EOP signals are not well known and not that much described in the literature. In addition to thermoreflectance, the temperature is a parameter that affects directly the free carrier's distribution and carrier mobilities inside the semiconductor. Temperature also modifies the absorption coefficient and not only the refractive index as known in the thermo-reflectance domain. All the physical and environmental parameters contribute to the modulation of the reflected laser probing beam onto structures under test. In this paper we will expose the origins of the reflected laser beam and the impact of the temperature on the EOP signal. For the first time, all the parameters, including temperature, have been taken into account. It opens the door of laser probing techniques improvements in failure analysis of submicron devices.
{"title":"Temperature effect on reflected laser probing signal of multiple elementary substructures","authors":"M. Rebai, F. Darracq, Jean-Paul Guillet, D. Lewis, P. Perdu, K. Sanchez","doi":"10.1109/IPFA.2014.6898165","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898165","url":null,"abstract":"Electro-Optical Probing (EOP) has shown its efficiency in the world of failure analysis. The different external physical parameters effects, especially the temperature, on the EOP signals are not well known and not that much described in the literature. In addition to thermoreflectance, the temperature is a parameter that affects directly the free carrier's distribution and carrier mobilities inside the semiconductor. Temperature also modifies the absorption coefficient and not only the refractive index as known in the thermo-reflectance domain. All the physical and environmental parameters contribute to the modulation of the reflected laser probing beam onto structures under test. In this paper we will expose the origins of the reflected laser beam and the impact of the temperature on the EOP signal. For the first time, all the parameters, including temperature, have been taken into account. It opens the door of laser probing techniques improvements in failure analysis of submicron devices.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898194
Tibor Grasser, K. Rott, Hans Reisinger, M. Waltl, Wolfgang Goes
Detailed time-dependent defect spectroscopy (TDDS) studies have recently demonstrated that recovery following negative bias temperature stress in MOSFETs is to good approximation consistent with a collection of independent (effective) first-order reactions. While the data are largely consistent with the first-order picture, several `anomalies' such as switching traps and disappearing/reappearing traps have already been identified and analyzed. Here, we focus on a newly made observation, namely that emission events apparently belonging to a single defect can in fact be composed of two subsequent emission events if the device is stressed for a long enough time. We analyze this peculiarity as a function of bias and temperature and conclude that it is most likely due to a pair of defects which for some reason have similar configurations and thus similar properties.
{"title":"Evidence for defect pairs in SiON pMOSFETs","authors":"Tibor Grasser, K. Rott, Hans Reisinger, M. Waltl, Wolfgang Goes","doi":"10.1109/IPFA.2014.6898194","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898194","url":null,"abstract":"Detailed time-dependent defect spectroscopy (TDDS) studies have recently demonstrated that recovery following negative bias temperature stress in MOSFETs is to good approximation consistent with a collection of independent (effective) first-order reactions. While the data are largely consistent with the first-order picture, several `anomalies' such as switching traps and disappearing/reappearing traps have already been identified and analyzed. Here, we focus on a newly made observation, namely that emission events apparently belonging to a single defect can in fact be composed of two subsequent emission events if the device is stressed for a long enough time. We analyze this peculiarity as a function of bias and temperature and conclude that it is most likely due to a pair of defects which for some reason have similar configurations and thus similar properties.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123736723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898208
C. Young, A. Neugroschel, K. Majumdar, Z. Wang, K. Matthews, C. Hobbs
Double-gate, fin-based Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers were subjected to bias temperature instability (BTI) evaluation where focus was placed on the crystallographic sidewall orientation and fin width dependence. For orientation dependence, BTI results at negative stress bias (NBTI) demonstrated that the (110) fin surface degraded more than the (100) surface, because more surface bonds are available in (110) to participate as bond-breaking trap centers during stress. For fin width dependence, positive BTI experienced no dependence on fin width; however, NBTI degradation increased as the fin width narrowed. A plausible cause is a concentration of electrons tunneled from the gate that reside in the SOI fin body. As the fin narrows, the sidewall device channel region moves in closer proximity to these concentrated electrons, which induces more band bending (i.e., increase the surface potential) at the fin/dielectricinterface resulting in a higher electric field and hole concentration in this region during stress, leading to more degradation.
{"title":"Bias temperature instability investigation of double-gate FinFETs","authors":"C. Young, A. Neugroschel, K. Majumdar, Z. Wang, K. Matthews, C. Hobbs","doi":"10.1109/IPFA.2014.6898208","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898208","url":null,"abstract":"Double-gate, fin-based Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers were subjected to bias temperature instability (BTI) evaluation where focus was placed on the crystallographic sidewall orientation and fin width dependence. For orientation dependence, BTI results at negative stress bias (NBTI) demonstrated that the (110) fin surface degraded more than the (100) surface, because more surface bonds are available in (110) to participate as bond-breaking trap centers during stress. For fin width dependence, positive BTI experienced no dependence on fin width; however, NBTI degradation increased as the fin width narrowed. A plausible cause is a concentration of electrons tunneled from the gate that reside in the SOI fin body. As the fin narrows, the sidewall device channel region moves in closer proximity to these concentrated electrons, which induces more band bending (i.e., increase the surface potential) at the fin/dielectricinterface resulting in a higher electric field and hole concentration in this region during stress, leading to more degradation.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898121
Chunlei Wu, S. Yao
There are many failure analysis cases are induced by the gate oxide rupture. It is a common and important failure mechanism in failure analysis. Photon emission microscopy with the combination of Lock-in IR-OBIRCH are very effective to localize the gate oxide rupture in MOS transistor, which can decrease analysis cycle time and improve success rates remarkably. In this paper, some different cases are presented to show how to locate the gate oxide rupture in MOS transistor accurately and quickly by photon emission microscopy with the combination of Lock-in IR-OBIRCH.
{"title":"Gate oxide rupture localization by photon emission microscopy with the combination of Lock-in IR-OBIRCH","authors":"Chunlei Wu, S. Yao","doi":"10.1109/IPFA.2014.6898121","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898121","url":null,"abstract":"There are many failure analysis cases are induced by the gate oxide rupture. It is a common and important failure mechanism in failure analysis. Photon emission microscopy with the combination of Lock-in IR-OBIRCH are very effective to localize the gate oxide rupture in MOS transistor, which can decrease analysis cycle time and improve success rates remarkably. In this paper, some different cases are presented to show how to locate the gate oxide rupture in MOS transistor accurately and quickly by photon emission microscopy with the combination of Lock-in IR-OBIRCH.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114337643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898147
K. Kitami, Masakatsu Murai, Natsuki Sugaya, O. Kikuchi, Shigeru Ohno
We have developed three new gate tracking functions to acquire dead-pixel-free and fine inspection images for advanced LSI packages with rough surface using a scanning acoustic tomo-graph. These are predicted surface gate tracking, double surface gate tracking and predicted S2-gate tracking methods. The advantages of these functions are demonstrated by using various test samples.
{"title":"New technique for acquiring dead pixel free and fine inspection image of advanced LSI package with rough surface using scanning acoustic tomograph","authors":"K. Kitami, Masakatsu Murai, Natsuki Sugaya, O. Kikuchi, Shigeru Ohno","doi":"10.1109/IPFA.2014.6898147","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898147","url":null,"abstract":"We have developed three new gate tracking functions to acquire dead-pixel-free and fine inspection images for advanced LSI packages with rough surface using a scanning acoustic tomo-graph. These are predicted surface gate tracking, double surface gate tracking and predicted S2-gate tracking methods. The advantages of these functions are demonstrated by using various test samples.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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