Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898124
Diwei Fan, Winter Wang
In mixed-signal ICs the die surface is divided between the analog circuit and the digital circuit often referred to as the logic area. Compare with the analog area, the logic area has more complex signals. The metal lines are narrower and closer together. These factors make it very hard to analyze defects such as metal bridges in the logic area. Firstly, the complicated waveform of signals and circuit loops in logic area make the schematic analysis harder. We cannot find the failed signal only through the comparison between reference unit and failed unit. The reason is that in the complicated circuit loop, one signal failure can cause many other signals in the circuit loop to fail. Secondly, if the failed signal is caused by metal bridge defect, since there are many metal lines close to the failed signal metal bridges to several of the metal lines could be the cause of failure. In this paper, we show how many FA techniques such as emission microscopy, microprobe, function, OBIRCH, FIB etc need to be used can be used to find a metal bridge defect causing a failure in the logic area.
{"title":"Failure analysis for metal bridge defect in logic area of mixed-signal IC","authors":"Diwei Fan, Winter Wang","doi":"10.1109/IPFA.2014.6898124","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898124","url":null,"abstract":"In mixed-signal ICs the die surface is divided between the analog circuit and the digital circuit often referred to as the logic area. Compare with the analog area, the logic area has more complex signals. The metal lines are narrower and closer together. These factors make it very hard to analyze defects such as metal bridges in the logic area. Firstly, the complicated waveform of signals and circuit loops in logic area make the schematic analysis harder. We cannot find the failed signal only through the comparison between reference unit and failed unit. The reason is that in the complicated circuit loop, one signal failure can cause many other signals in the circuit loop to fail. Secondly, if the failed signal is caused by metal bridge defect, since there are many metal lines close to the failed signal metal bridges to several of the metal lines could be the cause of failure. In this paper, we show how many FA techniques such as emission microscopy, microprobe, function, OBIRCH, FIB etc need to be used can be used to find a metal bridge defect causing a failure in the logic area.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898149
H. Younan, X. Z. Xiang, Li Xiaomin
In wafer fabrication, Fluorine (F) contamination may cause F-induced corrosion and defects on microchip Al bondpad, resulting in bondpad discoloration or non-stick on pad (NSOP). In the previous paper [1], the authors studied the F-induced corrosion and defects, characterized the composition of the “flower-like” defects and determined the binding energy of Al fluoride [AlF6]3- using X-ray Photoelectron Spectroscopy (XPS) and Time of Flight Secondary Ion Mass Spectrometry (TOF-SIMS) techniques. In this paper, we further studied F-induced corrosion and defects, and characterized the composition of the “crystal-like” defects using XPS. The experimental results showed that the major component of the “crystal-like” defect was Al fluoride of AlF3. The percentages of the components of the “crystal-like” defects on the affected bondpad are: Al (22.2%), Al2O3 (5.4%), AlF3(70.0%) and [AlF6]3- (2.4%). During high-resolution fitting, the binding energies of Al (72.8eV)Al2O3 (74.5eV), AlF3 (76.3eV) and [AlF6]3- (78.7eV) were used.
{"title":"Characterization studies of fluorine-induced corrosion crystal defects on microchip Al bondpads using X-ray photoelectron spectroscopy","authors":"H. Younan, X. Z. Xiang, Li Xiaomin","doi":"10.1109/IPFA.2014.6898149","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898149","url":null,"abstract":"In wafer fabrication, Fluorine (F) contamination may cause F-induced corrosion and defects on microchip Al bondpad, resulting in bondpad discoloration or non-stick on pad (NSOP). In the previous paper [1], the authors studied the F-induced corrosion and defects, characterized the composition of the “flower-like” defects and determined the binding energy of Al fluoride [AlF<sub>6</sub>]<sup>3-</sup> using X-ray Photoelectron Spectroscopy (XPS) and Time of Flight Secondary Ion Mass Spectrometry (TOF-SIMS) techniques. In this paper, we further studied F-induced corrosion and defects, and characterized the composition of the “crystal-like” defects using XPS. The experimental results showed that the major component of the “crystal-like” defect was Al fluoride of AlF<sub>3</sub>. The percentages of the components of the “crystal-like” defects on the affected bondpad are: Al (22.2%), Al<sub>2</sub>O<sub>3</sub> (5.4%), AlF<sub>3</sub>(70.0%) and [AlF<sub>6</sub>]<sup>3-</sup> (2.4%). During high-resolution fitting, the binding energies of Al (72.8eV)Al<sub>2</sub>O<sub>3</sub> (74.5eV), AlF<sub>3</sub> (76.3eV) and [AlF<sub>6</sub>]<sup>3-</sup> (78.7eV) were used.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"571 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898167
Lim Saw Sing, L. Way
The paper describes an approach to establish library for epitaxial layer monitoring using spreading resistance profiling (SRP) technique. This library can be used as complementary technique for conventional epitaxial monitoring such as inline four-point probe (FPP) or surface charge profiler (SCP).
{"title":"Library setup for epitaxial layer dopant profile using spreading resistance profiling analysis","authors":"Lim Saw Sing, L. Way","doi":"10.1109/IPFA.2014.6898167","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898167","url":null,"abstract":"The paper describes an approach to establish library for epitaxial layer monitoring using spreading resistance profiling (SRP) technique. This library can be used as complementary technique for conventional epitaxial monitoring such as inline four-point probe (FPP) or surface charge profiler (SCP).","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"59 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126078545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898204
M. Bruce, L. Ross, C. Chua
On Die Logic Analysis (ODLA) uses a scanning optical microscope (SOM) to quickly determine logic timing patterns, and then uses this information to identify logic pattern matches/mismatches on-the-fly from the backside. In this paper, the ODLA system and methodology will be described along with how, in one universal method, it can replace a slew of techniques such as Laser Timing Probe (LTP), Frequency Mapping (FM), and Phase Imaging (PI). It will be demonstrated on a chain of scan cells.
{"title":"One die logic analysis through the backside","authors":"M. Bruce, L. Ross, C. Chua","doi":"10.1109/IPFA.2014.6898204","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898204","url":null,"abstract":"On Die Logic Analysis (ODLA) uses a scanning optical microscope (SOM) to quickly determine logic timing patterns, and then uses this information to identify logic pattern matches/mismatches on-the-fly from the backside. In this paper, the ODLA system and methodology will be described along with how, in one universal method, it can replace a slew of techniques such as Laser Timing Probe (LTP), Frequency Mapping (FM), and Phase Imaging (PI). It will be demonstrated on a chain of scan cells.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124868128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898166
Li-Lung Lai, Oscar Zhang, Ling Zhu, Feng Qian, Mason Sun
Nanoprobing analysis has become standard analytical technique in the modern semiconductor FA lab. In this paper, we describe the use of nanoprobing to investigate cases of Gate-to-Source or Gate-to-Drain shorts and follow up the data generated by nanoprobing with physical analysis. The paper provide discussion of the electrical details and the physical mechanisms.
{"title":"In-depth description for the FA case with Gate-to-Source or Drain short by nanoprobing analysis","authors":"Li-Lung Lai, Oscar Zhang, Ling Zhu, Feng Qian, Mason Sun","doi":"10.1109/IPFA.2014.6898166","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898166","url":null,"abstract":"Nanoprobing analysis has become standard analytical technique in the modern semiconductor FA lab. In this paper, we describe the use of nanoprobing to investigate cases of Gate-to-Source or Gate-to-Drain shorts and follow up the data generated by nanoprobing with physical analysis. The paper provide discussion of the electrical details and the physical mechanisms.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121548029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898131
Yi-Chen Lin, Sheng-Min Chen
Ion implant is very important process in semiconductor manufacturing. In this study, we discuss a problem of low yield caused by an implant related defect on a specific location and structure in the device. The paper explains how general Failure Analysis (FA) techniques such as top view analysis by Scanning Electron Microscope (SEM), Passive Voltage Contrast (PVC) and cross section by Focused Ion Beam (FIB) coupled with Transmission Electron Microscopy (TEM) are unable to identify the defect which causes the gate driver failure which in turn leads to the implantation related low yield issue. It was found that Emission Microscopy (EMMI) analysis for global isolation, followed by nano-probing for electrical characterization of the gate driver was needed. Cross section wet chemical stain technique was then used to identify the localized implant junction failure.
{"title":"Case study of wet chemical stain to identify implant related low yield issue","authors":"Yi-Chen Lin, Sheng-Min Chen","doi":"10.1109/IPFA.2014.6898131","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898131","url":null,"abstract":"Ion implant is very important process in semiconductor manufacturing. In this study, we discuss a problem of low yield caused by an implant related defect on a specific location and structure in the device. The paper explains how general Failure Analysis (FA) techniques such as top view analysis by Scanning Electron Microscope (SEM), Passive Voltage Contrast (PVC) and cross section by Focused Ion Beam (FIB) coupled with Transmission Electron Microscopy (TEM) are unable to identify the defect which causes the gate driver failure which in turn leads to the implantation related low yield issue. It was found that Emission Microscopy (EMMI) analysis for global isolation, followed by nano-probing for electrical characterization of the gate driver was needed. Cross section wet chemical stain technique was then used to identify the localized implant junction failure.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122597645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898152
E. J. de La Cruz, Sheenel Karl De La Rea, Stephen McDonough, S. F. Chai
Acoustic Scanning for IGBT modules is a critical process to find anomalies that could lead to field failures. However, the cost to build this capability for failure analysis use is relatively expensive. This paper aims at evaluating a cost effective acoustic scanning technique for IGBT modules suitable for failure.
{"title":"Inverted scan transducer mount technique: A cost effective acoustic scanning of IGBT modules for failure analysis","authors":"E. J. de La Cruz, Sheenel Karl De La Rea, Stephen McDonough, S. F. Chai","doi":"10.1109/IPFA.2014.6898152","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898152","url":null,"abstract":"Acoustic Scanning for IGBT modules is a critical process to find anomalies that could lead to field failures. However, the cost to build this capability for failure analysis use is relatively expensive. This paper aims at evaluating a cost effective acoustic scanning technique for IGBT modules suitable for failure.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"710 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122989208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898120
Chunlei Wu, G. Song, S. Yao
There are some recovered cases during failure analysis (FA) process, although every FA step is performed right and very carefully. Sometimes the failure root cause still need to be identified after recovering, because the failed IC is unique and the failure root cause is very important to improve the products' quality. Sometimes the defect could be localized by Lock-in IR-OBIRCH, although the failure has disappeared. In this paper, two cases are demonstrated to show how to locate defects by Lock-in IR-OBIRCH after the failed ICs have recovered.
{"title":"Defect localization by Lock-in IR-OBIRCH on some recovered cases","authors":"Chunlei Wu, G. Song, S. Yao","doi":"10.1109/IPFA.2014.6898120","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898120","url":null,"abstract":"There are some recovered cases during failure analysis (FA) process, although every FA step is performed right and very carefully. Sometimes the failure root cause still need to be identified after recovering, because the failed IC is unique and the failure root cause is very important to improve the products' quality. Sometimes the defect could be localized by Lock-in IR-OBIRCH, although the failure has disappeared. In this paper, two cases are demonstrated to show how to locate defects by Lock-in IR-OBIRCH after the failed ICs have recovered.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131641584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898129
L. Nan
Curtaining effect and sample thickness constraints are always the key factors of limiting the use of ex-situ lift-out technique in advanced semiconductor device analysis. Over the years, in-situ lift-out technique has gradually replaced ex-situ lift-out because it offers greater advantages that can overcome the mentioned problems. A novel technique has been developed to prepare ultra-thin TEM specimens by inverted FIB thinning without the need of installing FIB chamber-mounted probe.
{"title":"Novel inverted sample thinning method by ex-situ lift-out","authors":"L. Nan","doi":"10.1109/IPFA.2014.6898129","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898129","url":null,"abstract":"Curtaining effect and sample thickness constraints are always the key factors of limiting the use of ex-situ lift-out technique in advanced semiconductor device analysis. Over the years, in-situ lift-out technique has gradually replaced ex-situ lift-out because it offers greater advantages that can overcome the mentioned problems. A novel technique has been developed to prepare ultra-thin TEM specimens by inverted FIB thinning without the need of installing FIB chamber-mounted probe.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"25 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125674982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898146
K. Wadhwa, R. Schlangen, J. Liao, T. Ton, H. Marks
This paper will present the non-destructive Lock-in thermography (LIT) technique and its application in detecting low-ohmic power shorts in 28 nm GPU (Graphics processing units). LIT was successful in detecting power shorts within die and package down to 5 Ohms within seconds, leading to accurate and efficient root cause analysis.
{"title":"Failure analysis of low-ohmic shorts using lock-in thermography","authors":"K. Wadhwa, R. Schlangen, J. Liao, T. Ton, H. Marks","doi":"10.1109/IPFA.2014.6898146","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898146","url":null,"abstract":"This paper will present the non-destructive Lock-in thermography (LIT) technique and its application in detecting low-ohmic power shorts in 28 nm GPU (Graphics processing units). LIT was successful in detecting power shorts within die and package down to 5 Ohms within seconds, leading to accurate and efficient root cause analysis.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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