1997 Symposium on VLSI Technology最新文献_第2页

Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/) N/sup +/-和P/sup +/-多晶硅门控超薄氧化物(21-26 /spl Aring/)的建模与表征

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623742

Lo, Buchanan, Taur, Han, Wu

引用次数: 41

A Highly Reliable 0.35/spl mu/m Field-shield Body-tied SOI Gate Array For Substrate-bias-effect Free Operation 用于无衬底偏置效应工作的高可靠0.35/spl mu/m场屏蔽体系SOI门阵列

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623711

Maeda, Yamaguchi, Kim, Iwamatsu, Ipposhi, Miyamoto, Hirano, Ueda, Nii, Mashiko, Maegawa, Inoue, Nishimura

A Highly Reliable 0.35pm Field-Shield Body-Tied SO1 Gate Array for Substrate-Bias-Effect Free Operation S. Maeda, Y. Yamaguchi, I.-J. Kim, 7: Iwamatsu, 7: Ipposhi, S. Miyamoto, Y. Hirano, K.Ueda*, K. Nii*, K. Mashiko*, S . Maegawa, Y. Inoue andT Nishimura ULSI Laboratory and *System LSI Laboratory, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664, JAPAN, TEL:+81-727-84-7324, FAX:+81-727-80-2693

张建军，张建军，张建军，等。一种高可靠性的0.35pm场屏蔽体系SO1栅极阵列，用于无衬底偏置效应。Kim, 7: iposhi, S. Miyamoto, Y. Hirano, K. ueda *， K. Nii*， K. Mashiko*， S。Maegawa, Y. Inoue和t Nishimura ULSI实验室和*系统LSI实验室，三菱电机公司，4-1 Mizuhara，伊丹，兵库县664，日本，电话:+81-727-84-7324，传真:+81-727-80-2693

引用次数: 4

Transient-enhanced Diffusion Of Iridium And Its Eflects On Electrical Characteristics Of Deep Sub-micron nMOSFETs 铱的瞬态增强扩散及其对深亚微米nmosfet电特性的影响

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623707

Cao, Griffin, Vande Voorde, Diaz, Greene

ABSTRACT RESULTS and DISCUSSION Accurate 2D doping profiles are needed to simulate shortFig. 2 shows measured C-V curves and simulations fits for channel nMOSFETs with indium channel. BY combining a lOOpm x 100pm nMOSFET. Excellent fit was established indium transient-enhanced diffusion (TED), segregation, and thoughout the C v curves for the 1D case. The kink near quantum mechanical (OM) effects, c V curves measured on the flat-band part of the C-V curve is due to the high nMOSFETs with various gate lengths can be simulated ionization energy (0.16 eV) of indium [5], and is confirmed accurately. Although indium exhibits severe TED, the by measuring C-V curves at various temperatures (Fig. 3). reverse-short-channel effect (RSCE) is reduced due to the for an indium-doped 0.2 strong segregation of indium into the gate oxide. In addition, gate n ~ ~ ~ ~ ~ ~ . B~ combining the effect of TED diffusion experiments using a buried indium marker layer on indium with the experimentally observed strong confirms that indium has severe TED, similar to boron, segregation into the gate oxide [6 ] , the 2D indium profile can which can be reduced by using an RTA after an implant. be accurately captured and the fit of the C-V curves is excellent. Fig. 5 shows the change in doping contours with candidate for achieving a retrograde and without considering indium TED and segregation effects. profile (RCP) in deep sub-micron ~ O S F E T ~ [I] , TED pushes indium towards the surface because of point H ~ ~ ~ ~ ~ ~ , transient-edanced difhsion (TED) due to ion defect gradients and reduces the peak indium concentration. implantation damage can excessive dopant diffusion In addition, the TED of indium allows indium to reach the which severely affects MOSFET~ characteristics [21, Until heavily doped source/drain regions by electric field assisted now, little has been reported on how the TED of indium dif is ion where indium is trapped in the highly doped n-type affects redistribution of the channel dopant profile. In this region. Due to the strong segregation of indium into the gate work, a C-V technique was used to obtain detailed 213 indium oxide, the amount of indium pileup near the surface is channel profiles, and a TED model for indium was extracted reduced, and consequently, the RSCE in an indium channel [3]. Diffusion experiments based on buried indium marker device is smaller compared to a boron channel device as layer were used to monitor the TED of indium due to ion shown in Fig. 6. implantation damage. ~ i ~ . 4 shows the C-V

摘要:结果与讨论为了模拟短图，需要精确的二维掺杂分布。2给出了测量的C-V曲线，并模拟了具有铟沟道的沟道nmosfet。通过结合一个环路× 100pm nMOSFET。在一维情况下，铟瞬态增强扩散(TED)、偏析和整个cv曲线都建立了良好的拟合。在近量子力学(OM)效应下，测得的c -V曲线平带部分的c -V曲线是由于不同栅极长度的高nmosfet可以模拟出铟[5]的电离能(0.16 eV)，并得到了准确的证实。虽然铟表现出严重的TED，但通过测量不同温度下的C-V曲线(图3)，由于掺杂铟的0.2强铟偏析到栅氧化物中，反向短通道效应(RSCE)减少了。另外，门n ~ ~ ~ ~ ~ ~。B~结合在铟上埋入铟标记层的TED扩散实验的效果和实验观察到的强烈证实了铟具有严重的TED，类似于硼，偏析到栅极氧化物[6]中，在植入后使用RTA可以降低铟的二维轮廓。C-V曲线拟合良好。图5显示了在不考虑铟TED和分离效应的情况下，实现逆行的候选掺杂轮廓的变化。在深亚微米~ O S F E T ~ [I]中，TED由于H点~ ~ ~ ~ ~ ~将铟推向表面，离子缺陷梯度引起的瞬态推进扩散(TED)降低了铟的峰值浓度。此外，铟的TED可以使铟达到严重影响MOSFET~特性的高度[21]，直到电场辅助的重掺杂源/漏区，铟被困在高掺杂n型的铟分散离子的TED如何影响通道掺杂物分布的再分布，目前还很少有报道。在这个地区。由于栅极工作中铟的强烈偏析，采用C-V技术获得了详细的213氧化铟，表面附近的铟堆积量为通道轮廓，并减少了铟的TED模型，从而得到了铟通道[3]中的RSCE。基于埋入式铟标记装置的扩散实验比硼通道装置要小，因为采用层来监测铟因离子引起的TED，如图6所示。植入损伤。~我~。C-V为4

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引用次数: 9

Charging And Intrinsic-leakage Current Peaks In Thin Silicon-dioxide Films 二氧化硅薄膜中的充电和本征泄漏电流峰值

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623741

Yamada, Yugami, Ohkura

A new leakage mode in thin SiO, films which may affect the retention characteristics of flash memories is examined. To improve the reliability of flash memories, electrical properties of the gate oxide were studied by using MOS capacitors. Since a transient current as well as a steady current is observed in a MOS capacitor under a constant gate bias, the time dependence of the current was measured to separate these currents. Through this operation, current peaks were found in both the transient and the steady current dependences on the gate bias. The peak for the transient current can be explained by resonant tunneling through traps near the oxide interface, and that for the steady current can be attributed to resonant tunneling leakage through traps distributed in the bulk oxide. The latter mechanism is a form of intrinsic leakage that affects the retention characteristics, and thus it should be considered in designing flash memories.

研究了一种影响闪存保留特性的新型SiO薄膜泄漏模式。为了提高闪存的可靠性，采用MOS电容对栅极氧化物的电学性能进行了研究。由于在恒定栅极偏压下的MOS电容器中观察到瞬态电流和稳态电流，因此测量了电流的时间依赖性以分离这些电流。通过这种操作，在瞬态和稳态电流中都发现了依赖于栅极偏置的电流峰值。瞬态电流的峰值可以解释为通过氧化物界面附近的陷阱的谐振隧穿，而稳态电流的峰值可以解释为通过分布在大块氧化物中的陷阱的谐振隧穿泄漏。后一种机制是一种影响保留特性的内禀泄漏，因此在设计快闪存储器时应予以考虑。

引用次数: 7

New Insight On Electromigration Failure Mechanism And Its Impact On Design Guidelines 电迁移失效机制的新认识及其对设计准则的影响

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623684

Jawarani, Gall, Hernández, Capasso, Kawasaki

INTRODUCTION A fundamental understanding of electromigration (EM) failures at W plug contact / via areas is essential in formulating design guidelines for VLSI interconnects. EM at the W plug areas has been found to occur through two stages, namely an incubation stage (consisting of A1,Cu precipitate dissolution followed by Cu diffusion beyond a critical length) and an A1 drift stage, which leads to increase in resistance. In this paper, it is first shown that the use of incubation time as the electromigration failure criterion enables realistic lifetime prediction of VLSI interconnects. Furthermore, we have studied electromigration in a temperature regime where precipitate dissolution and subsequent diffusion of Cu is dominant. The results yield markedly different activation energies which have an enormous impact on electromigration design guidelines for these interconnects. It is also shown how some accelerated EM tests can lead to erroneous conclusions and thereby mask the physical processes operative at use conditions.

在制定VLSI互连的设计指南时，对W插头接触/通孔区域的电迁移(EM)故障的基本理解是必不可少的。发现W塞区域的电磁效应经过两个阶段发生，即孵育阶段(由A1组成，Cu沉淀溶解，然后Cu扩散超过临界长度)和A1漂移阶段，导致电阻增加。在本文中，首次证明了使用潜伏期作为电迁移失效准则可以实现VLSI互连寿命预测。此外，我们还研究了在Cu的析出溶解和随后的扩散占主导地位的温度下的电迁移。结果产生了显著不同的活化能，这对这些互连的电迁移设计准则产生了巨大的影响。它还显示了一些加速的电磁测试如何导致错误的结论，从而掩盖了在使用条件下操作的物理过程。

引用次数: 2

Gate Electrode Engineering By Control Of Grain Growth For High Performance And High Reliable 0.18/spl mu/m Dual Gate CMOS 高性能高可靠0.18/spl mu/m双栅CMOS的晶粒生长控制栅电极工程

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623718

Shimizu, Kuroi, Sayama, Furukawa, Nishida, Inoue, Inuishi, Nishimura

Advanced gate electrode engineering is demonstrated to overcome the key issues of dual gate CMOS with thin gate oxide film. Using the small-grain-size polysilicon for the gate electrode, not only the suppression of gate depletion but also the stability of threshold voltage can be achieved as well as the improvement of the gate oxide integrity. Furthermore this successful implementation into 0.18pm CMOS is demonstrated with high performance and high reliability.

先进的栅极工程技术克服了薄栅氧化膜双栅CMOS的关键问题。采用小晶粒多晶硅作为栅极电极，不仅可以抑制栅极损耗，还可以实现阈值电压的稳定性，提高栅极氧化物的完整性。此外，在0.18pm CMOS中成功实现具有高性能和高可靠性。

引用次数: 8

Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs 超薄Ta/sub 2/O/sub 5/SiO/sub 2/栅极绝缘子，采用TiN栅极技术，用于0.1/spl mu/m mosfet

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623735

Momiyama, Minakata, Sugii

We have developed a new Ta205/Si02 gate insulator with a TIN gate electrode technology to break through the limitation of a thin SiOz gate insulator with a poly-Si electrode. We successfully fabricated nMOSFETs with stable operation and high drive current for the first time. Ultra thin chemically oxidized SiOz (less than 2 nm) combined with Ta205 provides a stable interface which improves Gm and reliability of transistor. High drive current (Idmax = 0.74 mA/pm at Vg = Vd = 3.0V) and good sub-threshold slope (S-factor = 76 mV/dec.) were obtained with Teq of 2.8nm and gate length of 0.35 Hm nMOSFETs. Introduction Deep sub-micron devices of less than 0.1 pm encounter a scaling limit of the Si02 gate insulator because of its high leakage current due to direct tunneling effects. The gate depletion effect is also serious issue for such devices. In order to break through these problems, we have to develop a new high Er gate insulator material having thick physical thickness and metal-gate technology. TazO5 (Er = 25 in bulk) and TiN are most promising candidates for future gate insulator and gate electrode materials respectively'). Though intensive investigations about Ta205 have been done for storage capacitors in future G-bit scale DRAMsZ4), there are no reports on Ta205 used for gate insulator for deep sub-micron devices. In view of mobility and reliability, we have developed Ta205/Si02 system for gate insulator with an equivalent Si02 thickness of less than 5 nm and TIN gate technology, and fabricated 0.35 pm nMOSFETs. One concern with the use of Si02 as an interlayer is its thickness and controllability. Since an insulator film thickness of less than 3 nm is required for 0.1 pm transistors, the SiOz interlayer should be very thin (less than 2 nm) so as not to suppress the advantage of utilizing high Er material. We have grown an ultra thin S O z interlayer by HNO, boiling and Nz annealing at temperatures of 700°C or 800°C for 30 min. Fabrication Process Figure 1 shows a process flow and schematic cross section of a Taz05/Si02 gate insulator nMOSFET. Following the conventional LOCOS isolation, the Si active region was oxidized by various methods as listed in Table 1 . Si02 thicknesses are calculated from Si 2p X P S spectra. We also prepared the non-oxidation sample by dipping HF solution before the TazO5 CVD as a control. TazO5 films were deposited by LPCVD at 410°C using Ta(OC2H5)5 and O2 gases. These films were annealed in O2 ambient at 800°C for 60 sec TIN was sputtered on Ta205 films as the gate electrode. After the gate definition, the source and drain were formed by ion implantation of As' to fabricate single-drain nMOSFETs. Impurity activation was done by RTA at 800°C for 60 sec. Other process and device parameters are also listed in Table 1. Teq are calculated from capacitance data under the accumulation condition using large MOS diodes Results and Discussion Figure 2 and Figure 3 show typical I-V and sub-threshold characteristics for a samp

认为由于产生了大量的界面陷阱，栅极电极的电场被它们屏蔽，从而削弱了栅极的可控性。上述结果表明，超薄(小于2 nm)夹层sio2对Ta205/SiOz栅极绝缘子晶体管的工作具有非常重要的作用，可以提高晶体管的通用性和可靠性。图10显示了掺磷多晶硅栅极情况下栅极沟道电容与累积栅极电容之比随等效氧化物厚度的变化。虽然由于反演层厚度有限，栅极通道电容没有达到最大值，但与多晶硅栅极相比，栅极通道电容比有所提高。在本文中，我们首次展示了TazOs/Si02栅极绝缘体和TiN栅极电极nmosfet。我们实现了高驱动电流(在Vg = Vd = 3.0V, Teq = 2.8nm, Lg = 0.35 pm时Idmax = 0.74 mA/pm)和良好的亚阈值斜率(s因子= 76 mV/ 12)。我们还报道了放置在Ta205/ si界面上的高质量超薄化学氧化Si02(在N2中退火至800°C)提供了具有较大Gm和高可靠性的稳定界面。因此，我们证明了一种具有TIN栅极系统的Ta2O5/SiO2栅极绝缘子突破了传统的具有多晶硅电极的SiO2栅极绝缘子的局限性。注射量为0.01 N c m Y。引用文献[1]。j:。理论物理。， vol . 33 (1994)， p . 6747。[10]王晓明，王晓明，等。社会科学，第140卷(1993)，p.1617。[10]高石英等，电学学报(1994)，p 839。[10] [T. Kaga等，IEDM技术。](1994)， p.927 [SI K F.Schuegraf等，IEDM technology . Dig (1994)， p.609]。135 4-93081 3-75-1 I97 1997 VLSl技术研讨会技术论文文摘

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引用次数: 20

A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor 一种用于高性能处理器的简单的0.3/spl μ m以下5级互连al插头和低k HSQ的CMOS技术

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623692

Yoshiyama, Okada, Igarashi, Yamada, Shimizu, Takata, Osaki, Higashitani, Asai

A simple sub-0.3ym CMOS technology has been developed with high performance transistors and five level interconnects. Using aluminum plug and HSQ (Hydrogen Silsesquioxane) film of low-k, the total process time is reduced by about 20% as compared with the conventional process with tungsten plug. The multimedia processor of 250MHz operation has been built on this technology. INTRODUCTION It is well known that faster transistors and multi-level interconnects will be required to maintain historic density and performance trends for high performance processor. Process steps of interconnects for total process steps are increase as generation of process technology is run. In generally, a tungsten plug(W-plug) for hole filling and AlCu materials for interconnect layer are used. Wplug is formed by blanket tungsten deposition followed by chemical mechanical polishing or etch back. This paper describes a simple logic process that meets the density and performance. This process is based on three key technologies such as faster transistor with CO salicide, aluminum plug (Al-plug), HSQ film of low-k. RESULTS AND DISCUSSION Interconnect Figure 1 shows the cross sectional view of this CMOS structure with five level interconnect. The pitches and sheet resistances of the interconnect layers are summarized in table 1. M1, M2 and M3 use a fine pitch to optimize density and capacitance for short distance interconnect. M4 and M5 use a course with thick metal to reduce parasitic resistance for long distance interconnect. In order to achieve low via resistance, good electromigration and reduction of the process time, Al-plug using high pressure[ 1][2] is adopted instead of W-plug for contact and via hole.Figure 2 shows the resistance of 3000 via chains for Al-plug and W-plug, respectively. Hole size is 0.35 x 0.35 ym2. The resistance of Al-plug is smaller by 45% than that of W-plug. Figure 3 shows comparison of the process time between Wplug and Al-plug. The process time reduction of 30% for interconnect process and 20% reduction for total process can be achieved in this Al-plug interconnect compared to the conventional W-plug interconnect. Because, aluminum PVD process using high pressure can form plug and wire at the same time. Figure 4 shows interconnect capacitances as a function of the device feature size. As the dimension shrink, the ratio of coupling capacitance to the total interconnect capacitance is increase. In this work, HSQ with low dielectric constant (k=3.6) was adopted to reduce the coupling capacitance.The inter-level dielectric was formed as follows; After the metal layer patterning, thin plasma TEOS was deposited by plasma CVD method. HSQ was applied as a spin-on layer on the plasma TEOS film. It is easy to fill gaps because HSQ has low viscosity resistance. After deposition of thick plasma TEOS, the TEOS film was planarized by CMP. Then, thin plasma TEOS was deposited to adjust the dielectric thickness. Via holes were pattemed using attenuated phase s

一种简单的低于0.3ym的CMOS技术已经开发出来，具有高性能晶体管和五电平互连。采用铝塞和低k的HSQ(氢硅氧烷)膜，与常规的钨塞工艺相比，总工艺时间缩短了约20%。在此基础上研制了250兆赫的多媒体处理器。众所周知，为了保持高性能处理器的历史密度和性能趋势，将需要更快的晶体管和多级互连。随着工艺技术的生成，总工艺步骤中互连的工艺步骤增加。一般采用钨塞(W-plug)填充孔，采用AlCu材料作互连层。钨塞是由钨毡沉积形成，然后进行化学机械抛光或蚀刻回来。本文描述了一种满足密度和性能要求的简单逻辑过程。该工艺是基于三种关键技术，即快速晶体管与CO盐化物，铝插头(Al-plug)，低k HSQ薄膜。图1显示了这种具有五电平互连的CMOS结构的横截面图。表1总结了互连层的节距和片电阻。M1, M2和M3使用精细的间距来优化密度和电容，以实现短距离互连。M4和M5采用厚金属层，减少寄生电阻，实现长距离互连。为了实现低通孔电阻、良好的电迁移和缩短工艺时间，接触孔和通孔采用高压[1]的al塞代替w塞。图2分别显示了al插头和w插头的3000通孔链的电阻。孔尺寸为0.35 x 0.35 ym2。al插头的电阻比w插头小45%。图3显示了Wplug和Al-plug处理时间的比较。与传统的w插头互连相比，该al插头互连可将互连过程的工艺时间减少30%，总工艺时间减少20%。因为，铝材PVD工艺采用高压可以同时形成插头和导线。图4显示了互连电容与器件特征尺寸的关系。随着尺寸的缩小，耦合电容占总互连电容的比例增大。本文采用低介电常数(k=3.6)的HSQ来减小耦合电容。层间介电层形成如下;在金属层图案化后，用等离子体CVD法沉积薄等离子体TEOS。将HSQ作为自旋层应用于等离子体TEOS薄膜上。由于HSQ具有较低的抗粘性，因此易于填充间隙。厚等离子体TEOS沉积后，用CMP将TEOS膜平面化。然后，沉积薄等离子体TEOS来调节介质厚度。通孔采用衰减相移i线光刻技术进行图案化，并使用ECR等离子体氧化物蚀刻进行蚀刻。在溅射沉积ti屏障金属后，在高压溅射系统中沉积了AlCu薄膜。结果如图5所示。如图6所示，采用HSQ自旋工艺后，金属空间为0.4pm的寄生耦合电容提高了10%。晶体管和性能栅极氧化物厚度为5.7 nm。采用掺磷多晶硅制备表面沟道NMOS和埋道PMOS。CoSi2在多晶硅和源/漏区形成，以减少寄生电阻。NMOS和PMOS的直流特性如图7所示。饱和驱动电流为0.47" pm @Vg=Vds=2.0V, NMOS为0.63mNpm @2SV, PMOS为0.22" pm @2.0V, 0.32mNym @2SV。图8显示了栅极长度为0.27pm的NMOS和PMOS的热柱降解情况。在栅极区和源漏区注入氮气可获得最高的热载流子免疫。卸载的560级CMOS逆变器链在2.5V Vcc下的级延迟为32ps。图9显示了在0.35p的前一个过程中传播延迟时间和有源电流等性能的比较。m CMOS (3.3V Vcc)和这个过程。结果表明，tpd提高了约30%，功耗降低了59%。这些性能以实际产品电路为特征。图10显示了一个多媒体处理器，它将用于处理器核心的300K晶体管集成在一个8mm2的区域中，并在6.0“x 6.2”芯片上实现了32k字节指令和32k字节数据RAM，运行在2.0V 250MHz下。结论提出了具有AI-Plug、HSQ、高驱动电流的简单sub-0.3ym CMOS技术。与传统的w插头/氧化物介电系统相比，这种工艺集成提供了工艺时间优势和相当大的性能优势。在此工艺基础上，实现了2V 250MHz操作的多媒体处理器。 [l] G.A.引用Dixit等人，IEDM技术。， p105, 1994。[2] K。Maekawa etal .，先进的金属化技术[j] . kuroi etal .， IEDM technology . [j]。， 1993年第325页。[4]。清水出版社。， IEDM技术。，第859页，1995。用于ULSI应用，P134, 1996。图5扫描电镜横截面照片Al-Plug和HSQ。

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引用次数: 1

Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness Si/SiO/ sub2 /界面粗糙度建模与表征

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623686

Heng-Chih Lin, Kan, Yamanaka, Helms

Effects of Si/SiO2 interface roughness are no longer negligible in device behavior for ULSI technology. This paper presents a comprehensive analysis of its influence on channel mobility, Fowler-Nordheim tunneling, quantum oscillation, hot carrier population, and oxide reliability. Implications of enhancement and degradation to MOS device performance and reliability are also summarized. Introduction With the advent of ULSI age, Si/SiO2 interface roughness becomes non-negligible. By analyzing the interface AFM image and electrical behavior of MOS devices, this paper presents a comprehensive modeling and characterization of interface roughness. We have found that it will fluctuate the local surface electric field [l], reduce the channel mobility [2], enhance the Fowler-Nordheim tunneling current, modify the quantum oscillation pattern, diminish the hot carrier population and slightly degrade the oxide strength. Both experimental and simulation results will be shown. Experiment The initial wafers are p-type, (100) CZ with substrate doping at 4 x 1015cm-3. LOCOS-structure MOS capacitors and MOSFETs with n+ in-situ doped poly gate and about 6 nm gate oxide were made with various deliberately roughened interfaces whose RMS roughness ranges from 0.2 nm to 4.3 nm. Hot water or BOE was used to roughen the sample either on the initial substrate or right before the gate oxidation. Interface roughness was measured by AFM on dummy wafers with oxide removed immediately after gate oxidation. Fig. 1 shows the 3D AFM images of 4 samples in this paper. MOSFET Channel Mobility We have reported that the channel mobility degradation due to interface roughness is much less severe than theoretically predicted [2]. A model is proposed here to explain this discrepancy. Fig. 2(a) shows the electron distribution and the average distance from the interface (Zezp) for various vertical E,ff by solving the 1-D Schroedinger equation and Poisson equation self-consistently. Since electrons are strongly confined to the interface for E , f f larger than 0.5 MV/cm, the perturbation theory for interface roughness scattering is not applicable for surface roughness comparable to, or larger than, Zezp. Electrons can not f ee l the full RMS roughness if the interface is very rough, but will travel conformably along the interface. Fig. 2(b) illustrates this behavior with a 2-D driftdiffusion simulation. A modification factor to channel length can be defined similar to the area factor due to interface roughness [ 11. As E, f f becomes weaker, the mobility degradation predicted by the perturbation theory is more consistent with the experimental result (Fig. 2(c)). MOS Fowler-Nordheim Tunneling Fig. 3 shows the gate oxide tunneling currents for different samples operated in the accumulation region. The current density of the roughest sample is about two orders of magnitude higher than that of the reference one. The fluctuation of the local electric field due to surface curvature is most likel

界面粗糙度越大，电子隧穿距离越短，但整体压降不变，隧穿后的平均电场越小。因此，界面粗糙度可以提高qbd。然而，粗糙度也会引入额外的界面缺陷，从而降低氧化物质量。总体的智商是由这两个相互竞争的因素决定的。我们已经确定并模拟了栅极氧化物界面粗糙度的几个重要影响，包括MOSFET沟道迁移率、氧化物隧道电流、量子振荡模式、热载子效应和氧化物质量(qbd)。器件应用如EEPROM是有前途的。这项工作是在SRC、ARPA和日本日立有限公司的财政支持下完成的。作者要感谢Simon J. Fang在AFM测量方面的帮助。[1]林洪成，应建峰，方世杰，王志军，“基于AFM图像的MOS隧道行为分析”，机械工程学报。[2]方世杰，林洪春，李建平，“反流层迁移率与表面粗糙度的关系研究”。IEEE EDL vol .17, no. 174，第178-80页，1996。[3]刘强，刘志强，刘志强，“Si/SiOz界面上sio2厚度和Si粗糙度对隧道电流振荡的影响研究”。JVST-A, vo1.13, no。1995年，第47-53页。141陈天义，p.k.。胡志强，“一种简单的mosfet衬底电流表征方法”，电子工程学报，第12期，p.505-507, 1984。[5]方勇。吴、胡，“在单晶硅上生长的氧化物对eeprom工艺和应用的依赖”，电子工程学报，vol .37, no. 5。3，第1页，第583-90页，1990。[6]王培文，顾廷坤;Su - p, Hong G.， Cheng H-C，“用超薄硅薄膜形成的隧道氧化物的优异发射特性”。JJAP, vol . 1.35, no. 1。6A, p. 369-73, 1996。[7]刘志强，李志强，“表面微粗糙度对氧化膜质量的影响”。1991电脑。在VLSI Tech，东京，日本。p.45-6。图1:样品a - d的AFM图像三维视图(a)-(d)。扫描大小为1pm × 1pm。这里显示了一个lOOnm x lOOnm的区域，以便更好地查看精细特征。RMS粗糙度范围为0.2nm (d) ~ 4.3nm (b)。

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引用次数: 3

A very simple trench isolation (VSTI) technology with chemo-mechanically polished (CMP) substrate Si 一个非常简单的沟槽隔离(VSTI)技术与化学机械抛光(CMP)衬底Si

1997 Symposium on VLSI Technology

Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623728

Park, Lee, Shin, Hong, Kang, Koh

A Very Simple Trench isolation (VSTI) technology with CMPed substrate-Si has been developed. VSTI has photo resist masked trench etching on a virgin Si wafer, filling with a highly conformal CVD oxide, and a CMP step down to the upper position of the Sub-Si. It shows low junction leakage current, high breakdown voltage and long TDDB characteristic on gate oxide, and perfectly flat surface. By optimizing the process, VSTI is expected to substitute the conventional isolation technology.

提出了一种基于cmp衬底的极简沟槽隔离(VSTI)技术。VSTI在未加工的硅晶片上进行光阻掩膜沟槽蚀刻，填充高度共形的CVD氧化物，并将CMP降压到Sub-Si的上部位置。具有结漏电流小、击穿电压高、栅极氧化物TDDB长、表面平整等特点。通过优化工艺，VSTI有望取代传统的隔离技术。

引用次数: 1