Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623745
Mukai, Hayashi, Komatsu
A new structured cell is proposed for the logic compatible Merged DRAM gain cell capable of reducing the cell size to almost one transistor area and with small increase in process steps. It can drastically improve “1” and “0” states separation due to the JFET effect of n channel region between two p+ gate regions. This new cell does not require new materials nor new equipments. Non-destructive read-out (NDRO) is possible resulting in higher speed read cycle.
{"title":"A Novel Merged Gain Cell For Logic Compatible High Density DRAMs","authors":"Mukai, Hayashi, Komatsu","doi":"10.1109/VLSIT.1997.623745","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623745","url":null,"abstract":"A new structured cell is proposed for the logic compatible Merged DRAM gain cell capable of reducing the cell size to almost one transistor area and with small increase in process steps. It can drastically improve “1” and “0” states separation due to the JFET effect of n channel region between two p+ gate regions. This new cell does not require new materials nor new equipments. Non-destructive read-out (NDRO) is possible resulting in higher speed read cycle.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623739
Okada
A new dielectric breakdown mechanism is proposed on the basis of the profile of stress-induced defect sites in the oxide. This model well explains the oxide thickness dependence of “B mode” stress-induced leakage current(B-SILC) and is valid for thicker oxides where the B-SILC is not observed. The model indicates that the stress relaxation of oxide and the smoothening of the SiO,/Si interface roughness are key issues to realize future ultrathin gate oxidcs ( d n m ) with high reliability. Introduction Highly reliable ultrathin gate oxide plays an important rolein achieving advanced MOS LSIs. It is strongly required to reveal the oxide breakdown mechanism, in particular, in the ultrathin oxides. Recently, Degraeve et al. proposed a model to link two generally-accepted models[l][2] in the ultrathin oxides[3][4]. In their model, breakdown is defined as the conduction via electron traps from one interface to the other. However the conduction mechanism has not been clarified. In the ultrathin oxides, we have reported the “B mode” stressinduced leakage current (B-SILC)[S] and clarified to be the variable range hopping (VRH) conduction[6][7], which is mediated by the defect sites, including various trap sites and interface states. The breakdown process is divided into the “partial breakdown” which induces the B-SILC, and the “complete breakdown”[8][9]. These are invaluable information to clarify the oxide breakdown mechanism. In this paper, we propose a new dielectric breakdown mechanism which is valid for the whole oxide thickness range. Experimental 4nm and 6.5nmthick oxides were grown in 0, atmosphere at 800°C on CZ-p type Si (100) substrates The electrical characteristics were measured using conventional MOS capacitors or mercury probing method. Electrons were injected from the gate electrode to the oxide. Results and Discussions A . In Figs. 1 and 2, curves from a to e show typical degradation behavior of 4nm-thick oxides by electrical stress plotted in semi-log and linear scale, respectively. After the “A mode” SILC[10] (curve b), the B-SILC appears at a local spot (curve c). By calculating d 3 x c, we can find in Fig.2 thc linear relationship between gate current and voltage as shown in line d’ which indicates the ohmic conduction. Since the plural B-SILC appears at different local spots@], curve d is found to be just a sum of three B-SILCs and ohmic conduction at different local spots as shown in the inset of Fig. 2. By further stress, the ohmic current increases since the resistance decreases (curve e). The B-SILC implies the intermediate state in the oxide breakdown sequence. B. Clarification of Defect Site Profile expressed as a function of temperature T[6] ; Denradation Behavior of Ultrathin Oxides In the VRH conduction of the B-SILC, the current I is I ( r ) = A exp(-B T (1) B = 2.06 (a’ N ) (2) where k, is the Boltzmann’s constant a and N is the decay length and density of the defect sites available for carrier conduction, respectively. Ac
基于应力缺陷部位的分布，提出了一种新的介质击穿机理。该模型很好地解释了“B模式”应力诱发泄漏电流(B- silc)对氧化物厚度的依赖关系，并且适用于未观察到B- silc的较厚的氧化物。该模型表明，氧化物的应力松弛和SiO /Si界面粗糙度的平滑是实现未来超薄栅极氧化物(dnm)高可靠性的关键问题。高可靠的超薄栅极氧化物在实现先进的MOS lsi中起着重要作用。迫切需要揭示氧化物的分解机制，特别是在超薄氧化物中。最近，Degraeve等人提出了一个模型，将超薄氧化物[3][4]中两个被普遍接受的模型[1][2]联系起来。在他们的模型中，击穿被定义为通过电子陷阱从一个界面传导到另一个界面。然而，其传导机制尚未明确。在超薄氧化物中，我们报道了“B模式”应力诱导泄漏电流(B- silc)[S]，并澄清为变范围跳变(VRH)导通[6][7]，该导通是由缺陷位点介导的，包括各种陷阱位点和界面态。击穿过程分为诱发B-SILC的“部分击穿”和“完全击穿”[8][9]。这些都是澄清氧化物分解机制的宝贵信息。本文提出了一种适用于整个氧化层厚度范围的新型介质击穿机理。在800℃、0℃气氛下，在CZ-p型Si(100)衬底上生长4nm和6.5nm厚的氧化物，采用传统的MOS电容器或汞探针法测量电学特性。电子从栅电极注入氧化物。结果与讨论在图1和图2中，从a到e的曲线分别以半对数和线性尺度表示了4nm厚的氧化物在电应力作用下的典型降解行为。在“A模式”SILC[10](曲线b)之后，b -SILC出现在一个局部点(曲线c)。通过计算d3 × c，我们可以在图2中发现栅极电流与电压的线性关系如图d′线所示，d′线表示欧姆导通。由于复数的B-SILC出现在不同的局部点@]，我们发现曲线d只是三个B-SILC和不同局部点的欧姆导率的总和，如图2插图所示。通过进一步的应力，欧姆电流增加，因为电阻减小(曲线e)。B-SILC表示氧化物击穿序列中的中间状态。B.以温度T为函数表示的缺陷部位轮廓的澄清[6];在B- silc的VRH导电过程中，电流I为I (r) = A exp(-B T (1) B = 2.06 (A ' N)(2)，其中k为玻尔兹曼常数A, N为载流子导电缺陷位的衰减长度和密度。根据(1)和(2)，BSILC不依赖于氧化物厚度Tox，而只依赖于(2)中的a3N。图3中绘制了B-SILC作为Tox的函数。虽然B-SILC不依赖于Tox，但当Tox厚度超过-4.8nm时，它会略有下降。当Tox>-5.5 nm时，未观察到B-SILC。因此，氧化物中的缺陷位置应考虑为与SiO，/Si界面距离的函数。6.用稀释的HF溶液在不同的电应力作用下蚀刻出不同厚度的snm -厚氧化物。图4显示了蚀刻到4.4nm之前(曲线a)和之后(曲线B, C)的典型电流-电压特性。虽然蚀刻前没有观察到B-SILC(曲线A)，但蚀刻后B-SILC明显出现(曲线C)，即使蚀刻到3.1 nm后，B-SILC仍然存在。这表明:(i) B-SILC的来源与氧化物击穿的来源相同;(ii)在较厚的氧化物中没有观察到BSILC，因为在远离SiO，/Si界面的氧化物中很难产生缺陷位点。C.由(1)(2)可知，B-SILC受传导路径上最小a3N的限制，a3N越大对应的B-SILC越大。a3N与SiOJSi界面距离的函数模型如图S所示，其中L为B-S IT的最小阈值，C为观察到的最小阈值。关键点是:(i) a3N随着距离的增大而逐渐减小，(ii) d N在SiO，/Si界面附近变小(ToxD，)。在图3所示情况下，Do < 2.5 nm, D， = 4.8 nm, D?= 5.5 nm。图6为四步氧化击穿序列模型，即;(i)产生如图5所示轮廓的缺陷位点，(ii) a3N达到临界值时出现VRH导通，(ii ii)缺陷位点进一步产生，(iv)形成欧姆导通路径，随后电阻进一步降低。
{"title":"A New Dielectric Breakdown Mechanism In Silicon Dioxides","authors":"Okada","doi":"10.1109/VLSIT.1997.623739","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623739","url":null,"abstract":"A new dielectric breakdown mechanism is proposed on the basis of the profile of stress-induced defect sites in the oxide. This model well explains the oxide thickness dependence of “B mode” stress-induced leakage current(B-SILC) and is valid for thicker oxides where the B-SILC is not observed. The model indicates that the stress relaxation of oxide and the smoothening of the SiO,/Si interface roughness are key issues to realize future ultrathin gate oxidcs ( d n m ) with high reliability. Introduction Highly reliable ultrathin gate oxide plays an important rolein achieving advanced MOS LSIs. It is strongly required to reveal the oxide breakdown mechanism, in particular, in the ultrathin oxides. Recently, Degraeve et al. proposed a model to link two generally-accepted models[l][2] in the ultrathin oxides[3][4]. In their model, breakdown is defined as the conduction via electron traps from one interface to the other. However the conduction mechanism has not been clarified. In the ultrathin oxides, we have reported the “B mode” stressinduced leakage current (B-SILC)[S] and clarified to be the variable range hopping (VRH) conduction[6][7], which is mediated by the defect sites, including various trap sites and interface states. The breakdown process is divided into the “partial breakdown” which induces the B-SILC, and the “complete breakdown”[8][9]. These are invaluable information to clarify the oxide breakdown mechanism. In this paper, we propose a new dielectric breakdown mechanism which is valid for the whole oxide thickness range. Experimental 4nm and 6.5nmthick oxides were grown in 0, atmosphere at 800°C on CZ-p type Si (100) substrates The electrical characteristics were measured using conventional MOS capacitors or mercury probing method. Electrons were injected from the gate electrode to the oxide. Results and Discussions A . In Figs. 1 and 2, curves from a to e show typical degradation behavior of 4nm-thick oxides by electrical stress plotted in semi-log and linear scale, respectively. After the “A mode” SILC[10] (curve b), the B-SILC appears at a local spot (curve c). By calculating d 3 x c, we can find in Fig.2 thc linear relationship between gate current and voltage as shown in line d’ which indicates the ohmic conduction. Since the plural B-SILC appears at different local spots@], curve d is found to be just a sum of three B-SILCs and ohmic conduction at different local spots as shown in the inset of Fig. 2. By further stress, the ohmic current increases since the resistance decreases (curve e). The B-SILC implies the intermediate state in the oxide breakdown sequence. B. Clarification of Defect Site Profile expressed as a function of temperature T[6] ; Denradation Behavior of Ultrathin Oxides In the VRH conduction of the B-SILC, the current I is I ( r ) = A exp(-B T (1) B = 2.06 (a’ N ) (2) where k, is the Boltzmann’s constant a and N is the decay length and density of the defect sites available for carrier conduction, respectively. Ac","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131046817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A methodology of direct characterization of interface traps in trench sidewall in STI structure is presented for the first time. It is demonstrated that n+/p-well diode in STI structure, which has large perimeter component of junction leakage, shows high D,t(-5X10" cm.' eV1 near midgap) in trench sidewall. Successful reduction of junction leakage current is achieved by further hydrogen passivation of interface traps. Residual bulk traps are distributed within 25 nm from the surface. However, they would not contribute to junction leakage current because of smaller capture cross section.
{"title":"Impact Of Trench Sidewall Interface Trap In Shallow Trench Isolation On Junction Leakage Current Characteristics For Sub-0.25 /spl mu/m CMOS Devices","authors":"Inaba, Takahashi, Okayama, Yagishita, Matsuoka, Ishiuchi","doi":"10.1109/VLSIT.1997.623727","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623727","url":null,"abstract":"A methodology of direct characterization of interface traps in trench sidewall in STI structure is presented for the first time. It is demonstrated that n+/p-well diode in STI structure, which has large perimeter component of junction leakage, shows high D,t(-5X10\" cm.' eV1 near midgap) in trench sidewall. Successful reduction of junction leakage current is achieved by further hydrogen passivation of interface traps. Residual bulk traps are distributed within 25 nm from the surface. However, they would not contribute to junction leakage current because of smaller capture cross section.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114468393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200" wafers.
{"title":"Copper Integration In Self Aligned Dual Damascene Architecture","authors":"Morand, Lermé, Palleau, Torres, Vinet, Demolliens, Ulmer, Gobil, Fayolle, Romagna, Le Bihan","doi":"10.1109/VLSIT.1997.623680","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623680","url":null,"abstract":"In this paper, we will demonstrate the compatibility of copper metallization in a Self Aligned Dual Damascene architecture with 0.18pm CMOS technology requirements. This Cu metallization has also been used, for the first time, as the fifth level of metal of a 2cm2 0.35pm microprocessor for integrability demonstration on 200\" wafers.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125198098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623725
Yugami, Mine
Using nm-thick a-Si film, we developed a novel nm-grain poly-Si gate structure for reduction of cell to cell write/erase tunnel current deviation in quarter micron FLASH memories. This gate structure is beneficial to increase tunnel current and Q,,without any degradation of the tunnel oxide reliability. These phenomena are explained by local field enhancement caused by nm-grain poly-Si interface structure. INTRODUCTION In quarter micron FLASH memories, the one of the main concerns is the way to reduce cell to cell tunnel current deviation in write or erase operation. The tunnel current locally increase at grain boundary where phosphorous concentration is locally high[l]. In accordance with scaling of FLASH memories, the grain size of poly-Si has become to be comparable to the size of tunnel area of memory cell. This situation increases the tunnel current deviation among the cells because of the decreasing number of grain boundary contained in tunnel area. To avoid this problem, minimizing the poly-Si grain size is most efficacious[2]. Fortunately, it was found that nm grain size poly-Si can be formed by annealing the nm-thick a-Si films[3]. In this case the grain size decreases with reducing a-Si film thickness. Thus, we propose a new gate structure which consist of two kinds of poly-Si layers. The lower layer is nm-grain poly-Si using ultra thin(2-l0nm) a-Si film. The upper portion poly-Si is formedwith thick a-Si film, leads to micron size grains. In this paper, we describe the electrical characteristics of tunnel oxide with nm-grain poly-Si /tunnel oxide interface. PROCESS SEQUENCE After tunnel oxide formation, ultra thin, 2-10nm thick, a-Si film was depositedat 425°C using LPCVD technique. Next, in order to form alarge grain poly-Si, 200nm thick a-Si film was deposited at 525°C. To crystallize these Si films, 900°C annealing in N2 ambient was performed for 20min., as shown in Fig.2. From the TEM observation, we found that the crystallization in lower layer begin at 800°C while upper layer crystallize easily at 600°C. As the results, nm-graidmicron grain double layer poly-Si gate structure was formedas shown in TEM results at Fig. 3. Additionally, this large grain size and flat surface of upper portion of this gate structure can provide the high reliable inter-poly dielectric films. ELECTRIC CHARACTERISTICS From the C-V measurement also from elipsometry, we found the effective tunnel oxide thickness increases with decreasing nm-grain poly-Si layer thickness(Fig.4). On the other hand, the tunneling current under same electric field increase in thinner nm-grain layer as shown in Fig.5 when the gate was negatively biased. This increase of tunnel current occurs when the nm-grain layer thickness is less than 8nm. The stress inducedleakage current(S1LC) after 8C/cmZ injection does not dependon the thickness of nm-grain layer(Fig.6,Fig.7). Thus, that this gate structure is promising in FLASH memories to increase write/erase speed without concem of re
1997 VLSl技术研讨会(技术论文文摘
{"title":"A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories","authors":"Yugami, Mine","doi":"10.1109/VLSIT.1997.623725","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623725","url":null,"abstract":"Using nm-thick a-Si film, we developed a novel nm-grain poly-Si gate structure for reduction of cell to cell write/erase tunnel current deviation in quarter micron FLASH memories. This gate structure is beneficial to increase tunnel current and Q,,without any degradation of the tunnel oxide reliability. These phenomena are explained by local field enhancement caused by nm-grain poly-Si interface structure. INTRODUCTION In quarter micron FLASH memories, the one of the main concerns is the way to reduce cell to cell tunnel current deviation in write or erase operation. The tunnel current locally increase at grain boundary where phosphorous concentration is locally high[l]. In accordance with scaling of FLASH memories, the grain size of poly-Si has become to be comparable to the size of tunnel area of memory cell. This situation increases the tunnel current deviation among the cells because of the decreasing number of grain boundary contained in tunnel area. To avoid this problem, minimizing the poly-Si grain size is most efficacious[2]. Fortunately, it was found that nm grain size poly-Si can be formed by annealing the nm-thick a-Si films[3]. In this case the grain size decreases with reducing a-Si film thickness. Thus, we propose a new gate structure which consist of two kinds of poly-Si layers. The lower layer is nm-grain poly-Si using ultra thin(2-l0nm) a-Si film. The upper portion poly-Si is formedwith thick a-Si film, leads to micron size grains. In this paper, we describe the electrical characteristics of tunnel oxide with nm-grain poly-Si /tunnel oxide interface. PROCESS SEQUENCE After tunnel oxide formation, ultra thin, 2-10nm thick, a-Si film was depositedat 425°C using LPCVD technique. Next, in order to form alarge grain poly-Si, 200nm thick a-Si film was deposited at 525°C. To crystallize these Si films, 900°C annealing in N2 ambient was performed for 20min., as shown in Fig.2. From the TEM observation, we found that the crystallization in lower layer begin at 800°C while upper layer crystallize easily at 600°C. As the results, nm-graidmicron grain double layer poly-Si gate structure was formedas shown in TEM results at Fig. 3. Additionally, this large grain size and flat surface of upper portion of this gate structure can provide the high reliable inter-poly dielectric films. ELECTRIC CHARACTERISTICS From the C-V measurement also from elipsometry, we found the effective tunnel oxide thickness increases with decreasing nm-grain poly-Si layer thickness(Fig.4). On the other hand, the tunneling current under same electric field increase in thinner nm-grain layer as shown in Fig.5 when the gate was negatively biased. This increase of tunnel current occurs when the nm-grain layer thickness is less than 8nm. The stress inducedleakage current(S1LC) after 8C/cmZ injection does not dependon the thickness of nm-grain layer(Fig.6,Fig.7). Thus, that this gate structure is promising in FLASH memories to increase write/erase speed without concem of re","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132183287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623724
Reisinger, Franosch, Bohm
A SONOS structure with a p+ doped silicon gate instead of the commonly used n+ gate is proposed and investigated. In the erase mode the p+ gate prevents the Fowler Nordheim (FN) tunneling of electrons from the conduction band of the gate into the Si3N4. This improves either the erase speed or with a thicker tunnel oxide the data retention time by several orders of magnitude without deteriorating the other properties. Introduction SONOS memories have advantages over the FLOTOX type memories due to the superior defect density of ONO gate dielectrics compared to Si02 and due to a simpler cell structure. FLOTOX memories, however, have no problems to reach data retention times of 150 years as demanded by civil users while SONOS memories hardly reach a data retention of 10 years (see fig. 1). This is why the actual use of SONOS memories is limited to military applications needing a high radiation hardness /U. The purpose of this work is to introduce for the first time a SONOS structure with write and erase times as short as for conventional SONOS memories but with a more than 8 orders of magnitude improvement in data retention time. This is achieved with only two minor modifications of the conventional SONOS EEPROM manufacturing process. Sample Preparation Our samples were prepared by implementing an ONO storage layer (shown in the inset of fig. 3) into a standard CMOS process. The two differences to conventional SONOS memories are a 308, G e l oxide (instead of 2 0 4 and a p'-doped (with Boron) polysilicon gate instead of the standard n'-doped gate. For reference purposes the same samples with n+-gates were also prepared. For the measurements n-channel FETs as well as large area MOS diodes were used. Basic Idea The idea is explained in fig. 2: The dominant charge loss mechanism is tunneling of charge from the nitride across the tunnel oxide to the substrate / 2 / . An increase in tunnel oxide thickness from 20A to 30A will increase the data retention time by several orders of magnitude. However, inreasing the tunnel oxide thickness increases the erase time because the tunneling probability for holes from the substrate into the nitride decreases also. Increasing the field to speed up the erasing does not help because the competing process Fowler Nordheim injection of electrons from the gate prevents a total discharge of trapped negative charge (see the erase-characteristics for n' gates in fig.5). A conventional SONOS EEPROM needs, as a built-in assymetry, the tunnel oxide to be thinner than the blocking oxide in order to keep the FN current smaller than the dwect tunneling current of holes. Note that this works at low fields only. In contrast our approach makes the tunnel oxide thick and suppresses the FN current from the conduction band of the gate by instead reducing the electron density in the gate. A precondition for this concept to work is an acceptor concentration of more than 1020cm'3 in order to prevent any n-inversion or band bending due to d
对于两种不同的写擦条件，持久特性绘制在图8中。对于大的4V初始存储窗口，续航时间约为10个周期，与其他文献数据相当。对于较小的内存窗口，续航时间接近lo7个周期，这与最好的FLOTOX内存的续航时间相同。由于优良的电荷保持也较小的记忆窗口将适用。这有望进一步提高续航能力。这项工作得到了Bayesische Forschungs-Stiftung的支持。参考文献:1 H.E. Maes, J. Witters和G. Groeseneken, Proc. 17 European 2 F.R. Libsch和M.H. White，固态电子学Vol. 33, 3 T. Bohm, A. Nakamura, H. Aosaza, M. Yamagishi和4 Y. Hsia, IEEE Trans。电子器件Vol. 24, No. 5, 5 E.P. Jacobs和U. Schwabe，固态电子学Vol. 24 P. Olivo, Z.A. Weinberg, K.J. Stein和D.S. Wen，固态7 d.a Adams, Proc.第13届IEEE非易失性半导体。8 M.L. French，陈正明，h.s ath"than a. M.H. White, lee Trans。哟,
{"title":"A Novel SONOS Structure For Nonvolatile Memories With Improved Data Retention","authors":"Reisinger, Franosch, Bohm","doi":"10.1109/VLSIT.1997.623724","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623724","url":null,"abstract":"A SONOS structure with a p+ doped silicon gate instead of the commonly used n+ gate is proposed and investigated. In the erase mode the p+ gate prevents the Fowler Nordheim (FN) tunneling of electrons from the conduction band of the gate into the Si3N4. This improves either the erase speed or with a thicker tunnel oxide the data retention time by several orders of magnitude without deteriorating the other properties. Introduction SONOS memories have advantages over the FLOTOX type memories due to the superior defect density of ONO gate dielectrics compared to Si02 and due to a simpler cell structure. FLOTOX memories, however, have no problems to reach data retention times of 150 years as demanded by civil users while SONOS memories hardly reach a data retention of 10 years (see fig. 1). This is why the actual use of SONOS memories is limited to military applications needing a high radiation hardness /U. The purpose of this work is to introduce for the first time a SONOS structure with write and erase times as short as for conventional SONOS memories but with a more than 8 orders of magnitude improvement in data retention time. This is achieved with only two minor modifications of the conventional SONOS EEPROM manufacturing process. Sample Preparation Our samples were prepared by implementing an ONO storage layer (shown in the inset of fig. 3) into a standard CMOS process. The two differences to conventional SONOS memories are a 308, G e l oxide (instead of 2 0 4 and a p'-doped (with Boron) polysilicon gate instead of the standard n'-doped gate. For reference purposes the same samples with n+-gates were also prepared. For the measurements n-channel FETs as well as large area MOS diodes were used. Basic Idea The idea is explained in fig. 2: The dominant charge loss mechanism is tunneling of charge from the nitride across the tunnel oxide to the substrate / 2 / . An increase in tunnel oxide thickness from 20A to 30A will increase the data retention time by several orders of magnitude. However, inreasing the tunnel oxide thickness increases the erase time because the tunneling probability for holes from the substrate into the nitride decreases also. Increasing the field to speed up the erasing does not help because the competing process Fowler Nordheim injection of electrons from the gate prevents a total discharge of trapped negative charge (see the erase-characteristics for n' gates in fig.5). A conventional SONOS EEPROM needs, as a built-in assymetry, the tunnel oxide to be thinner than the blocking oxide in order to keep the FN current smaller than the dwect tunneling current of holes. Note that this works at low fields only. In contrast our approach makes the tunnel oxide thick and suppresses the FN current from the conduction band of the gate by instead reducing the electron density in the gate. A precondition for this concept to work is an acceptor concentration of more than 1020cm'3 in order to prevent any n-inversion or band bending due to d","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623668
Maydan
Global demand for semiconductor IC solutions has kept both semiconductor manufacturers and wafer fabrication equipment suppliers in a state of rapid growth since the 1970's. As the next century approaches, new manufacturing challenges arise due to decreasing feature sizes, increasing metal layers, and the transition to 300" wafer size. Technology and productivity shifts such as these represent tremendous economic risks for both semiconductor manufacturers and equipment suppliers. This paper will briefly discuss historical drivers of growth for both semiconductor manufacturers and equipment suppliers, examine semiconductor manufacturers' priorities for the year 2000 and beyond, discuss equipment trends for the 2lSt century, and highlight winning strategies for the next century for wafer processing.
{"title":"Keeping Both Sides Winning: Wafer Fabrication Equipment Suppliers And Semiconductor Manufacturers In The Year 2000 And Beyond","authors":"Maydan","doi":"10.1109/VLSIT.1997.623668","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623668","url":null,"abstract":"Global demand for semiconductor IC solutions has kept both semiconductor manufacturers and wafer fabrication equipment suppliers in a state of rapid growth since the 1970's. As the next century approaches, new manufacturing challenges arise due to decreasing feature sizes, increasing metal layers, and the transition to 300\" wafer size. Technology and productivity shifts such as these represent tremendous economic risks for both semiconductor manufacturers and equipment suppliers. This paper will briefly discuss historical drivers of growth for both semiconductor manufacturers and equipment suppliers, examine semiconductor manufacturers' priorities for the year 2000 and beyond, discuss equipment trends for the 2lSt century, and highlight winning strategies for the next century for wafer processing.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high performance robust 0.1 Spm CMOS technology is reported. This technology integrates two key processes including (1) a CoSi2 salicide process that realizes higher driving current than TiSi2 process and (2) a newly developed shallow trench isolation (STI) process with suppressed reverse narrow channel effect. The excellent thermal stability of sheet resistance is provided using high temperature sputtered and in-situ annealed CoSi2 salicide. In this process, 12%(PMOS) and 4%(NMOS) higher driving current have been achieved, and the VT has not been lowered down to 0.2pm channel width. The 1 8 . 5 ~ ~ Tpd has been obtained for an inverter at V ~ o = l . 8 V . Introduction Salicide and STI technologies are indispensable to 0.1.5pm CMOS and beyond. However, there are serious problems for low power application described as follows: 1) In TiSi, salicide CMOS, the driving current of PMOS is degraded by the high contact resistance on p+ diffusion layer caused by large bamer height at the silicide/Si interface. The driving current of NMOS is also degraded because of the thick gate depletion layer in nf gate poly Si caused by relatively low arsenic concentration for stable TiSi2 formation. Some techniques, for example, the elevated S/D [ l ] or the high gate doping prior gate patterning [2] can overcome these problems, but these techniques result in the increase of process steps or complexity. 2) In STI, the reverse narrow channel effect [3] increases a standby power dissipation and results in difficulties for design of embedded memory devices, regardless of its advantages for scaled isolation and low parasitic capacitance. In this paper we have demonstrated the advantage of CoSi2 on driving current of MOSFET and a newly developed STI process featuring by boron implantation into trench side wall for the suppression of reverse narrow channel effect. Design Concept 1) Improvement in driving current in a simple process CoSi2 is promising material to overcome the abovementioned TiSi2 issues, because it has a lower bamer height for p' diffusion and stable sheet resistance at high arsenic concentration compared with TiSi2 [4]. Therefore CoSi2 can allow simultaneous high dose ion implantation for gate and S D doping. 2) Shallow trench isolation The reverse narrow channel effect of NMOS with STI may be caused by boron depletion at the trench edge, which would be caused during the following process such as S/D annealing. Therefore, oblique angle boron ion implantation into the trench side wall of NMOS is used before trench filling as shown in Fig. 1. Experiment A 300nm Trench was formed with rounded corners. Boron was implanted into the trench side wall at 30 degree angle at 20keV, 2 E 1 3 ~ m ~ . STI was completed by CVD oxide filling and CMP planarization. Tub, channel, 4nm gate oxide, gate electrode were formed, followed by drain extension and pocket ion implantation for NMOS. After 50nm side wall spacer formation, ion im lantation (As: 3 E 1 5 ~ m . ~ at 5Oke
{"title":"A Robust 0.15/spl mu/m CMOS Technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation","authors":"Kawaguchi, Abiko, Inoue, Saito, Yamamoto, Hayashi, Masuoka, Tamura, Tokunaga, Yamada, Yoshida, Sakai","doi":"10.1109/VLSIT.1997.623730","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623730","url":null,"abstract":"A high performance robust 0.1 Spm CMOS technology is reported. This technology integrates two key processes including (1) a CoSi2 salicide process that realizes higher driving current than TiSi2 process and (2) a newly developed shallow trench isolation (STI) process with suppressed reverse narrow channel effect. The excellent thermal stability of sheet resistance is provided using high temperature sputtered and in-situ annealed CoSi2 salicide. In this process, 12%(PMOS) and 4%(NMOS) higher driving current have been achieved, and the VT has not been lowered down to 0.2pm channel width. The 1 8 . 5 ~ ~ Tpd has been obtained for an inverter at V ~ o = l . 8 V . Introduction Salicide and STI technologies are indispensable to 0.1.5pm CMOS and beyond. However, there are serious problems for low power application described as follows: 1) In TiSi, salicide CMOS, the driving current of PMOS is degraded by the high contact resistance on p+ diffusion layer caused by large bamer height at the silicide/Si interface. The driving current of NMOS is also degraded because of the thick gate depletion layer in nf gate poly Si caused by relatively low arsenic concentration for stable TiSi2 formation. Some techniques, for example, the elevated S/D [ l ] or the high gate doping prior gate patterning [2] can overcome these problems, but these techniques result in the increase of process steps or complexity. 2) In STI, the reverse narrow channel effect [3] increases a standby power dissipation and results in difficulties for design of embedded memory devices, regardless of its advantages for scaled isolation and low parasitic capacitance. In this paper we have demonstrated the advantage of CoSi2 on driving current of MOSFET and a newly developed STI process featuring by boron implantation into trench side wall for the suppression of reverse narrow channel effect. Design Concept 1) Improvement in driving current in a simple process CoSi2 is promising material to overcome the abovementioned TiSi2 issues, because it has a lower bamer height for p' diffusion and stable sheet resistance at high arsenic concentration compared with TiSi2 [4]. Therefore CoSi2 can allow simultaneous high dose ion implantation for gate and S D doping. 2) Shallow trench isolation The reverse narrow channel effect of NMOS with STI may be caused by boron depletion at the trench edge, which would be caused during the following process such as S/D annealing. Therefore, oblique angle boron ion implantation into the trench side wall of NMOS is used before trench filling as shown in Fig. 1. Experiment A 300nm Trench was formed with rounded corners. Boron was implanted into the trench side wall at 30 degree angle at 20keV, 2 E 1 3 ~ m ~ . STI was completed by CVD oxide filling and CMP planarization. Tub, channel, 4nm gate oxide, gate electrode were formed, followed by drain extension and pocket ion implantation for NMOS. After 50nm side wall spacer formation, ion im lantation (As: 3 E 1 5 ~ m . ~ at 5Oke","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123164714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623702
Mabuchi, Sasaki, Miyagawa
A CMOS image sensor cell suitable for miniaturization is proposed. The number of gate polysilicons in a cell was reduced from 3 to 1 by utilizing a stacked capacitor and a buried reset channel. A cell of 5.5x5.5ym2 applicable to 1/4 inch VGA device was produced with 23% of photodiode area using 0.7pm design rule. Fabrication processes are compatible with stacked capacitor DRAM. Saturation signal amplitude of 1.OV and conversion gain of 9uVlelectron were obtained with 5V power Introduction The CMOS image sensor has advantages of low driving voltage and low consumption electric power compared with the CCD image sensor. It also has the possibility of integrating driving circuitry and adding functionality on the same chip[l]. The problem of fixed pattem nose, which previously had prevented utilization of the CMOS image sensor, was resolved by integrating noise canceling circuits[2]. Consequently, the CMOS image sensor has become the focus of mounting interest in recent years. The important problem which still remains is the difficulty of manufacturing a small cell array since each cell contains three transistors for address, reset and amplify other than a photodiode. In particular, the arrangement of 3 gate polysilicons restricts the cell size. In this paper, we report a miniaturized cell which contains only 1 gate and has a simple layout. Circuit The cell circuit composition is shown in Fig.1 where the conventional transistor address cell is also shown for purposes of comparison. Photodiode (PD) converts photons into electrons, which lowers detection node (DN) voltage. Then gate voltage of the amplification transistor (Amp) is modulated, and a signal is read out to the signal line (Sig) by the source follower which consists of the load transistor (Load) fabricated in the upper part of cell array. Whereas a conventional cell has an address transistor (Ad) for selecting a row, the proposed cell has a stacked capacitor (Ad) which controls the detection node potential. Whereas a conventional cell has a reset transistor (R) for discharging photoelectrons, the proposed cell has a buried reset channel (R) without a gate polysilicon. Structure and Operation Shown in Fig.2 are the structure and potential diagrams along with the cross section from detection node to drain. Drain and detection node are formed by the conventional n-type diffusion layer, while reset channel is formed by thin n-type ionimplantation which sets channel depletion voltage (Vr) higher than OV and lower than drain voltage (Vdd). The cell is operated by 3-level driving pulse[3]. During the integration period, address line keeps a middle level (‘M’) and detection node holds photoelectrons (Signal). Photoelectrons can be contained until detection node potential becomes equal to Vr. Photoelectrons beyond it are discharged to drain through the reset channel. When the address line is first set to a high voltage (‘H’) so that detection node potential is made higher than that in other rows, sig
{"title":"A 5.5/spl mu/m CMOS Image Sensor Cell Utilizing A Buried Reset Channel","authors":"Mabuchi, Sasaki, Miyagawa","doi":"10.1109/VLSIT.1997.623702","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623702","url":null,"abstract":"A CMOS image sensor cell suitable for miniaturization is proposed. The number of gate polysilicons in a cell was reduced from 3 to 1 by utilizing a stacked capacitor and a buried reset channel. A cell of 5.5x5.5ym2 applicable to 1/4 inch VGA device was produced with 23% of photodiode area using 0.7pm design rule. Fabrication processes are compatible with stacked capacitor DRAM. Saturation signal amplitude of 1.OV and conversion gain of 9uVlelectron were obtained with 5V power Introduction The CMOS image sensor has advantages of low driving voltage and low consumption electric power compared with the CCD image sensor. It also has the possibility of integrating driving circuitry and adding functionality on the same chip[l]. The problem of fixed pattem nose, which previously had prevented utilization of the CMOS image sensor, was resolved by integrating noise canceling circuits[2]. Consequently, the CMOS image sensor has become the focus of mounting interest in recent years. The important problem which still remains is the difficulty of manufacturing a small cell array since each cell contains three transistors for address, reset and amplify other than a photodiode. In particular, the arrangement of 3 gate polysilicons restricts the cell size. In this paper, we report a miniaturized cell which contains only 1 gate and has a simple layout. Circuit The cell circuit composition is shown in Fig.1 where the conventional transistor address cell is also shown for purposes of comparison. Photodiode (PD) converts photons into electrons, which lowers detection node (DN) voltage. Then gate voltage of the amplification transistor (Amp) is modulated, and a signal is read out to the signal line (Sig) by the source follower which consists of the load transistor (Load) fabricated in the upper part of cell array. Whereas a conventional cell has an address transistor (Ad) for selecting a row, the proposed cell has a stacked capacitor (Ad) which controls the detection node potential. Whereas a conventional cell has a reset transistor (R) for discharging photoelectrons, the proposed cell has a buried reset channel (R) without a gate polysilicon. Structure and Operation Shown in Fig.2 are the structure and potential diagrams along with the cross section from detection node to drain. Drain and detection node are formed by the conventional n-type diffusion layer, while reset channel is formed by thin n-type ionimplantation which sets channel depletion voltage (Vr) higher than OV and lower than drain voltage (Vdd). The cell is operated by 3-level driving pulse[3]. During the integration period, address line keeps a middle level (‘M’) and detection node holds photoelectrons (Signal). Photoelectrons can be contained until detection node potential becomes equal to Vr. Photoelectrons beyond it are discharged to drain through the reset channel. When the address line is first set to a high voltage (‘H’) so that detection node potential is made higher than that in other rows, sig","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128796745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623723
Chung, Yih, Cheng, Liang
Interface state generation and oxide trap charge creation have been recognized as a major reliability issue for Flash memory cells [l-21. In a certain design of Flash cells, programming of the cell is achieved by hot-carrier programming near the drain, while erase is performed by F-N tunneling near the source. Both will generate the so-called oxide damages, which include the interface state Nit and the oxide trap charge Q,,. They will cause serious reliability problem such as programming delay, window closure, and gate disturb etc. So far, these characteristics can only be observed from measurement. Their correlation with oxide damages has not been clear since the profiling of these damages are rather difficult and not available. In this paper, a new and simple technique which allows the profiling of both interface states (Nit) and oxide charge (Qox) generated during either programming or erase will be presented. The effects of these damages on the flash cell performance and reliabilities will then be identified.
{"title":"A New Oxide Damage Characterization Technique For Evaluating Hot Carrier Reliability Of Flash Memory Cell After P/E Cycles","authors":"Chung, Yih, Cheng, Liang","doi":"10.1109/VLSIT.1997.623723","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623723","url":null,"abstract":"Interface state generation and oxide trap charge creation have been recognized as a major reliability issue for Flash memory cells [l-21. In a certain design of Flash cells, programming of the cell is achieved by hot-carrier programming near the drain, while erase is performed by F-N tunneling near the source. Both will generate the so-called oxide damages, which include the interface state Nit and the oxide trap charge Q,,. They will cause serious reliability problem such as programming delay, window closure, and gate disturb etc. So far, these characteristics can only be observed from measurement. Their correlation with oxide damages has not been clear since the profiling of these damages are rather difficult and not available. In this paper, a new and simple technique which allows the profiling of both interface states (Nit) and oxide charge (Qox) generated during either programming or erase will be presented. The effects of these damages on the flash cell performance and reliabilities will then be identified.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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