The lowest contact resistivity, 5.8-6.8~10-lQcm (0.038Wvia for 0.44ym@), was obtained with a Cu doublelevel interconnection with via plug connected without barrier metal. The double-level interconnect was fabricated by a dual damascene process using Cu-CVD. In order to achieve ultra-low resistivity, we have developed a cleaning procedure [lst: Os plasma, 2nd: Mute H F solution, 3rd: insitu hexafluoroacetylacetone (Hbfac)) vapor cleaning] after via etching. This technology reahze one order lower via resistance than conventional one.
{"title":"Ultra-low Resistance Diret~ Contact Cu Via technology Using In-situ Chemical Vapor Cleamng","authors":"Tsuchiya, Ueno, Donnelly, Kikkawa, Hayashi, Kobayashi, Sekiguchi","doi":"10.1109/VLSIT.1997.623694","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623694","url":null,"abstract":"The lowest contact resistivity, 5.8-6.8~10-lQcm (0.038Wvia for 0.44ym@), was obtained with a Cu doublelevel interconnection with via plug connected without barrier metal. The double-level interconnect was fabricated by a dual damascene process using Cu-CVD. In order to achieve ultra-low resistivity, we have developed a cleaning procedure [lst: Os plasma, 2nd: Mute H F solution, 3rd: insitu hexafluoroacetylacetone (Hbfac)) vapor cleaning] after via etching. This technology reahze one order lower via resistance than conventional one.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126805643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623714
Tseng, Huang, Babcock, Ford, Woo
In this paper, a new mechanism is proposed to explain the well-known kink-related noise overshoot in SO1 MOSFETs. We found that there is a correlation between the frequency dependence of the kink’s onset voltage and the characteristic frequency (ao) dependence on drain bias of Lorentzian-like noise overshoot. It was concluded that the noise overshoot is due to the frequency dependence of floating body effect, which amplifies the noise arising from electronic tunneling transitions ( zT = 2n/w,) between front interfacial oxide traps and the channel. Introduction Recently SO1 MOSFEiTs have been proposed as a candidate for high speed communication applications. Low-frequency noise is an important consideration for these analog circuits. For example, low-frequency noise can be up-converted in RF mixers and oscillators, resulting in phase noise [ l ] . Due to the floating body, SO1 MOSFETs exhibit a low frequency kink-related noise overshoot, which has a Lorentzian spectrum: a flat low-frequency plateau, with constant amplitude, followed by a l’ roll-off, illustrated in Fig. 1. Different mechanisms were proposed to explain this excess noise, such as the trap-assisted generation-recombination noise model [2] and the G-R noise induced by back interface state [3]. However, these models cannot completely explain the characteristic frequency (wo) dependence on drain bias of overshoot noise, as shown in Fig. 4. In this paper we propose another mechanism to explain the above noise overshoct phenomenon. A similar noise behavior was also found in bodytied devices, but the amplitude is significantly reduced. Experimental Result A. Device description and low-frequency noise measurements Near fully depleted thin film SO1 nMOSFETs were used in the study [4]. An extra p+ implant step is applied on the source to form sourcebody-tied (SB-tied) SO1 nMOSFETs. SB-tied devices eliminate the kink at the output characteristics as shown in Fig. 2. Low-frequency noise measurements were made using an HP 3561A Dynamic Signal Analyzer with the gate electrode of the MOSFET ac shorted to ground by a capacitor. The output noise power is then transferred to inputreferred gate noise power. B. Drain bias dependence of noise overshoot in the kink region The devices were biased in the saturation region with low VGT, where the flicker noise is dominated by the number fluctuation model [5]. The Lorentzian spectrum noise overshoot was observed in the floating body SO1 nMOSFET (Fig. 4.a). As bias voltage increases, 0, increases and the noise level of the plateau decreases. Plotting the frequency times S,, versus frequency (Fig. 4.b), the characteristic frequency (w,) on drain bias could be determined and listed in Table 1. It is important to note that such noise overshoot behavior exists even for body-tied devices. The same drain bias dependence phenomena were observed (Fig. 5 ) with smaller overshoot amplitude and weaker drain bias dependence of a,,. Discussion C. Frequency dependence offl
{"title":"Correlation Between Low-frequency Noise Overshoot In SOI MOSFETs And Frequency Dependence Of Floating Body Effect","authors":"Tseng, Huang, Babcock, Ford, Woo","doi":"10.1109/VLSIT.1997.623714","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623714","url":null,"abstract":"In this paper, a new mechanism is proposed to explain the well-known kink-related noise overshoot in SO1 MOSFETs. We found that there is a correlation between the frequency dependence of the kink’s onset voltage and the characteristic frequency (ao) dependence on drain bias of Lorentzian-like noise overshoot. It was concluded that the noise overshoot is due to the frequency dependence of floating body effect, which amplifies the noise arising from electronic tunneling transitions ( zT = 2n/w,) between front interfacial oxide traps and the channel. Introduction Recently SO1 MOSFEiTs have been proposed as a candidate for high speed communication applications. Low-frequency noise is an important consideration for these analog circuits. For example, low-frequency noise can be up-converted in RF mixers and oscillators, resulting in phase noise [ l ] . Due to the floating body, SO1 MOSFETs exhibit a low frequency kink-related noise overshoot, which has a Lorentzian spectrum: a flat low-frequency plateau, with constant amplitude, followed by a l’ roll-off, illustrated in Fig. 1. Different mechanisms were proposed to explain this excess noise, such as the trap-assisted generation-recombination noise model [2] and the G-R noise induced by back interface state [3]. However, these models cannot completely explain the characteristic frequency (wo) dependence on drain bias of overshoot noise, as shown in Fig. 4. In this paper we propose another mechanism to explain the above noise overshoct phenomenon. A similar noise behavior was also found in bodytied devices, but the amplitude is significantly reduced. Experimental Result A. Device description and low-frequency noise measurements Near fully depleted thin film SO1 nMOSFETs were used in the study [4]. An extra p+ implant step is applied on the source to form sourcebody-tied (SB-tied) SO1 nMOSFETs. SB-tied devices eliminate the kink at the output characteristics as shown in Fig. 2. Low-frequency noise measurements were made using an HP 3561A Dynamic Signal Analyzer with the gate electrode of the MOSFET ac shorted to ground by a capacitor. The output noise power is then transferred to inputreferred gate noise power. B. Drain bias dependence of noise overshoot in the kink region The devices were biased in the saturation region with low VGT, where the flicker noise is dominated by the number fluctuation model [5]. The Lorentzian spectrum noise overshoot was observed in the floating body SO1 nMOSFET (Fig. 4.a). As bias voltage increases, 0, increases and the noise level of the plateau decreases. Plotting the frequency times S,, versus frequency (Fig. 4.b), the characteristic frequency (w,) on drain bias could be determined and listed in Table 1. It is important to note that such noise overshoot behavior exists even for body-tied devices. The same drain bias dependence phenomena were observed (Fig. 5 ) with smaller overshoot amplitude and weaker drain bias dependence of a,,. Discussion C. Frequency dependence offl","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126862075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new-low temperature gate oxynitride has been developed for sub-0.25 pm CMOS technologies. In this process, nitrous oxide is cracked in a pre-furnace at high tem- perature to generate nitric oxide that flows into the main fur- nace where the gate oxidation is carried out at low tempera- ture. Physical analysis and gate oxide integrity data are used to demonstrate effective nitridation of the gate oxides grown in this fashion. The process was successfully integrated into a 0.15 pm, 1.5 V CMOS technology with 25 A physical gate oxide to minimize short channel effects and improve device performance and hot carrier reliability.
针对低于0.25 pm的CMOS技术，开发了一种新型低温栅氮化氧。在这个过程中，氧化亚氮在预炉中高温裂解，生成一氧化氮，一氧化氮流入主炉，主炉在低温下进行栅氧化。物理分析和栅极氧化物完整性数据被用来证明在这种方式生长的栅极氧化物的有效氮化。该工艺已成功集成到具有25 a物理栅氧化物的0.15 pm, 1.5 V CMOS技术中，以最大限度地减少短通道效应，并提高器件性能和热载流子可靠性。
{"title":"A Novel Low-temperature Gate Oxynitride For CMOS Technologies","authors":"Diaz, Cox, Greene, Perlaki, Carr, Manna, Bayoumi, Cao, Shamma, Tavassoli, Chi, Farrar, Lefforge, Chang, Langley, Marcoux","doi":"10.1109/VLSIT.1997.623689","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623689","url":null,"abstract":"A new-low temperature gate oxynitride has been developed for sub-0.25 pm CMOS technologies. In this process, nitrous oxide is cracked in a pre-furnace at high tem- perature to generate nitric oxide that flows into the main fur- nace where the gate oxidation is carried out at low tempera- ture. Physical analysis and gate oxide integrity data are used to demonstrate effective nitridation of the gate oxides grown in this fashion. The process was successfully integrated into a 0.15 pm, 1.5 V CMOS technology with 25 A physical gate oxide to minimize short channel effects and improve device performance and hot carrier reliability.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132829230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623732
Wilder, Atalar, Quate
Introduction Scanning probe lithography (SPL) is an emerging area of research in which the scanning tunneling microscope (STM) or atomic force microscope (AFM) is used to pattern nanometer-scale features. Four factors will dictate the viability of SPL as a patterning technology for the semiconductor industry: 1) resolution, 2) alignment accuracy, 3) reliability, and 4) throughput. We present a new SPL technique-a hybrid between the AFM and STMto address these issues. We demonstrate its capabilities and its compatibility with semiconductor processing by fabricating a pMOSFET with an effective channel length (L,ff) of 100 nm and report the device characteristics.
{"title":"Fabrication Of 100 nm pMOSFETS With Hybrid AFW / STM Lithography","authors":"Wilder, Atalar, Quate","doi":"10.1109/VLSIT.1997.623732","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623732","url":null,"abstract":"Introduction Scanning probe lithography (SPL) is an emerging area of research in which the scanning tunneling microscope (STM) or atomic force microscope (AFM) is used to pattern nanometer-scale features. Four factors will dictate the viability of SPL as a patterning technology for the semiconductor industry: 1) resolution, 2) alignment accuracy, 3) reliability, and 4) throughput. We present a new SPL technique-a hybrid between the AFM and STMto address these issues. We demonstrate its capabilities and its compatibility with semiconductor processing by fabricating a pMOSFET with an effective channel length (L,ff) of 100 nm and report the device characteristics.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
INTRODUCTION CoSi2 salicide technology is going to be used for 0.25 pm CMOS not only for the high speed digital application, but also for RF analog application, because of its low sheet resistance of the gate electrode without no 'narrow line effect'. Low gate resistance less than 5 QiU is indispensable for realizinglow noisefigureofless than 1dB ofanalogMOSFET [I]. IJsuaUy, the highest heat process after the CoSi2 salidde process has been less than 800 "C. However, from the view point of future merged process with RF analog, logic and memory devices, it has been some times requested to use even higher temperature process to anneal capacitor dielectrics or to activate impurities after the salicide process. Thus, it is important to know the thermal stability of the CoSi2 resistance and TDDB reliability of the gate oxide with higher process temperature, for the CoSi2 process to be used in wide range of applications.
{"title":"0.25 /spl mu/m salicide CMOS Technology Thermally Stable Up To 1,000/spl deg/C With High TDDB Reliability","authors":"Ohguro, Yoshitomi, Morimoto, Harakawa, Momose, Katsumata, Iwai","doi":"10.1109/VLSIT.1997.623715","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623715","url":null,"abstract":"INTRODUCTION CoSi2 salicide technology is going to be used for 0.25 pm CMOS not only for the high speed digital application, but also for RF analog application, because of its low sheet resistance of the gate electrode without no 'narrow line effect'. Low gate resistance less than 5 QiU is indispensable for realizinglow noisefigureofless than 1dB ofanalogMOSFET [I]. IJsuaUy, the highest heat process after the CoSi2 salidde process has been less than 800 \"C. However, from the view point of future merged process with RF analog, logic and memory devices, it has been some times requested to use even higher temperature process to anneal capacitor dielectrics or to activate impurities after the salicide process. Thus, it is important to know the thermal stability of the CoSi2 resistance and TDDB reliability of the gate oxide with higher process temperature, for the CoSi2 process to be used in wide range of applications.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Introduction Shallow trench isolation (STI) is the key technology for deep submicron devices and begins to be used practically for advanced logic and memory LSIs. With down-scaling of device dimensions, the aspect ratio of trench increases and trench filling becomes severe even in STI structures. Therefore, choice of filling material for high aspect ratio trench is one of the important issues for deep submicron STI devices. Although the TEOS-Q film shows good refilling characteristics, it requires high temperature annealing in order to minimize HF etch-rate and this high temperature process results in large volume change with high mechanical stress [I] . However, the impact of this stress on device functionality and process optimization have not been investigated. In this paper, mechanical stress induced defect generation accompanying the MOSFET punch-through in TEOS-Q filled STI structure is reported for the first time. This defect is located only in channel region beneath the gate oxide and causes enhanced diffusion of sourceidrain impurity. The residual mechanical stress of filling material and the gate electrode cause this phenomenon. Suppression of the defect generation by optimizing high temperature annealing process is also described and is verified by SRAM test vehicle. Mechanical Stress-induced MOSFET Punch-through The fabrication process of MOSFET with STI structure was based on 0.35pm technology [2]. The trench depth was 0.7pm to achieve 0.4pm n+ip+ spacing. The channel width of each transistor used in memory cell was 0.35pm and the isolation width was 0.4pm. The TEOS-Q film was used as a filling material to fill such high aspect ratio trenches. After CMP planarization, high temperature (>lOOOT) annealing was carried out to minimize HF etch-rate similar to thermal oxide. The gate electrode was consist of poly-Si(200nm)~WSi(100nm)/SiN(200nm) stacked structure and lOOnm thick SiN sidewall was applied. In order to verify the manufacturability of this process, thousands of SRAM test vehicles (256kbit) were fabricated. As a result, it was found that some SRAM chips suffer from specific functional failure with large stand-by current more than 10pAifail-bit. The leakage current level was higher four order of magnitude than that of junction leakage current of total active region. Moreover, the leakage current had negative temperature dependence and was same as the nMOS inverter's. These results suggest that some access transistor in cell array did not cut-off with very small probability. In fact, it was verified that an access transistor in the fail chip had large sourceidrain punch-through current. Therefore, it was concluded that the leakage current flew from bit-line to Vss-line through nMOS inverter consisted of access transistor and latch nMOS as shown in Fig.1. The I-V characteristic of access transistor in cell array which accompanies source/drain punchthrough characteristic is also shown in Fig.2. It should be noted that this current i
综上所述，该缺陷是由填充材料产生的机械应力和栅极材料产生的附加应力引起的。工艺优化研究了避免机械应力引起的源雨冲孔的工艺集成。残余应力的松弛是解决这一问题的根本途径。由于STI形成后的工艺温度为80 - 850℃，因此降低该温度附近的机械应力非常重要。为了减小填充材料的残余应力，研究了槽型填充后的高温退火工艺。图5显示了TEOS-03薄膜应力随退火温度的温度依赖性。1200℃退火后，薄膜在850℃时的应力降至=OMPa，而1000℃退火样品的应力大于1GPa。退火温度对缺陷密度的依赖关系如图6所示。如图所示，120°C退火样品显示出无缺陷的特征。1200℃退火对抑制缺陷诱导MOSFET穿通的影响如图7所示。通过引入优化的高温退火，证实了TEOS-03填充STI可以应用于0.35pm 6T电池，而不会降低器件的产率。此外，模拟的机械应力表明，通道宽度减小10%，机械应力增加约5%，如图8所示。这一结果意味着未来lsi中STI器件尺寸的缩小将需要如上所述的精心工艺材料设计，以实现更低的机械应力和更高的可制造性。结论首次在TEoS-03填充STI结构中发现了通道缺陷导致的源流穿孔。这种缺陷的产生是由于填充材料的残余应力和栅极材料的应力共同作用的结果。优化后的高温退火实现了无缺陷特性，使TEOS-03作为STI结构的填充材料而不降低器件良率。未来STI设备的工艺集成应该从可制造性的角度仔细考虑这一现象。参考文献[I 1 S]Nag等人，IEDM科技公司。[21]陈国强。Ishimam et al.， Symp。VLSI技术，p97, 1994[31]。Ikeda et al.， IEDM Tech. Dig。， 1996年，第77页
{"title":"Mechanical Stress Induced MOSFET Punch-through And Process Optimization For Deep Submicron TEOS-O/sub 3/ Filled STI Device","authors":"Ishimaru, Matsuoka, Takahashi, Nishigohri, Okayama, Unno, Yabuki, Umezawa, Tsuchiya, Fujii, Kinugawa","doi":"10.1109/VLSIT.1997.623729","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623729","url":null,"abstract":"Introduction Shallow trench isolation (STI) is the key technology for deep submicron devices and begins to be used practically for advanced logic and memory LSIs. With down-scaling of device dimensions, the aspect ratio of trench increases and trench filling becomes severe even in STI structures. Therefore, choice of filling material for high aspect ratio trench is one of the important issues for deep submicron STI devices. Although the TEOS-Q film shows good refilling characteristics, it requires high temperature annealing in order to minimize HF etch-rate and this high temperature process results in large volume change with high mechanical stress [I] . However, the impact of this stress on device functionality and process optimization have not been investigated. In this paper, mechanical stress induced defect generation accompanying the MOSFET punch-through in TEOS-Q filled STI structure is reported for the first time. This defect is located only in channel region beneath the gate oxide and causes enhanced diffusion of sourceidrain impurity. The residual mechanical stress of filling material and the gate electrode cause this phenomenon. Suppression of the defect generation by optimizing high temperature annealing process is also described and is verified by SRAM test vehicle. Mechanical Stress-induced MOSFET Punch-through The fabrication process of MOSFET with STI structure was based on 0.35pm technology [2]. The trench depth was 0.7pm to achieve 0.4pm n+ip+ spacing. The channel width of each transistor used in memory cell was 0.35pm and the isolation width was 0.4pm. The TEOS-Q film was used as a filling material to fill such high aspect ratio trenches. After CMP planarization, high temperature (>lOOOT) annealing was carried out to minimize HF etch-rate similar to thermal oxide. The gate electrode was consist of poly-Si(200nm)~WSi(100nm)/SiN(200nm) stacked structure and lOOnm thick SiN sidewall was applied. In order to verify the manufacturability of this process, thousands of SRAM test vehicles (256kbit) were fabricated. As a result, it was found that some SRAM chips suffer from specific functional failure with large stand-by current more than 10pAifail-bit. The leakage current level was higher four order of magnitude than that of junction leakage current of total active region. Moreover, the leakage current had negative temperature dependence and was same as the nMOS inverter's. These results suggest that some access transistor in cell array did not cut-off with very small probability. In fact, it was verified that an access transistor in the fail chip had large sourceidrain punch-through current. Therefore, it was concluded that the leakage current flew from bit-line to Vss-line through nMOS inverter consisted of access transistor and latch nMOS as shown in Fig.1. The I-V characteristic of access transistor in cell array which accompanies source/drain punchthrough characteristic is also shown in Fig.2. It should be noted that this current i","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623676
Tsukamoto, Kuroda, Okamoto
A 0.25pm logic process technology, which is suitable for high-speed, low-voltage operation, logic and DRAM integration in one chip, has been developed. For fabrication of an embedded DRAM, a high-thermal-stability W-polycide dual gate process was realized using intentional chemical oxide formation for large-grain poly-Si growth. Lateral dopant diffusion and boron penetration through a 5-nm-thick gate oxide are prevented with being annealed at 1000°C for 10 s and then 850°C for 30 min. Furthermore, we have utilized a buried metal on diffusion layer (BMD) structure, and the parasitic resistance has been equal to that of a TiSi, structure.
{"title":"0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices","authors":"Tsukamoto, Kuroda, Okamoto","doi":"10.1109/VLSIT.1997.623676","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623676","url":null,"abstract":"A 0.25pm logic process technology, which is suitable for high-speed, low-voltage operation, logic and DRAM integration in one chip, has been developed. For fabrication of an embedded DRAM, a high-thermal-stability W-polycide dual gate process was realized using intentional chemical oxide formation for large-grain poly-Si growth. Lateral dopant diffusion and boron penetration through a 5-nm-thick gate oxide are prevented with being annealed at 1000°C for 10 s and then 850°C for 30 min. Furthermore, we have utilized a buried metal on diffusion layer (BMD) structure, and the parasitic resistance has been equal to that of a TiSi, structure.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623746
Horiuchi, Sakata, Kimura
The disturbance of stored charges in SO1 memory cells, which is caused by floating body effects, is fully suppressed by using an access transistor with a bipolar embedded source structure just beneath the n'junction. This structure is free from the subthreshold leakage current and degradation caused by high source resistance. Introduction The use of SO1 in future-generation DRAM technology promises to facilitate the wide spread of SO1 CMOS as the main technology for ULSI systems. The greatestbarrier that stands in the way of this is the notorious floating body effects which cause bit-line-induced disturbances in memory cells [l]. In Sol, minority carriers generated in the body forward bias the body-bit-line diode when the bit-line potential falls to a low level. This forward junction injects minority caniers across the channel into the storage node, upsetting the stored charge even if the word line is deactivated This type of disturbance seriously shortens the dynamic retention characteristicsor, in other words degrade the refresh time properties. This paper presents a possible solution that fully suppresses the floating body effects and bit-line-induced disturbances in SOICMOSFETs without sacrificing their excellent performance. Device Outline A schematic cross-section of a bipolar embedded source structure (BESS) device [2] is shown in Fig. 1. In an nchannel access transistor, p-type recombination centers are embedded in the nsourcddrain regions adpen t to the SOUburied oxide interface. A generated hole in the p-type body can easily diffuse to a source recombination center through the nsource bypass which has a low built-in potential barrier. Thus, hole recombination in the source prevents the floating body problems. /cmZ) with a projection range to the SOI/buried oxide interface followed by recrystallization annealing creates the recombination centers, leading to the formation of a small grain poly-Si region. This structure is independent of the source /drain profile near the gate edges, and there is no degradation of device properties. The bit-line induced disturbance in the SO1 DRAM cells can be evaluated with the simple test circuit shown in Fig. 2. In the test circuit, the storagecapacitor (Cpad=0.75 pF)) was made by connecting two bonding pads of the accessand sense-transistors with a conductive paste. The on-wafer measurements were carried out with an external load resistor connected to the sense transistor. High-dose Si implanted amorphization Simulated Results The forward hole current properties at the source diode are directly related to the floating-body-immune properties. A numerical simulation of a fonvard-biased (0.5 V) potential contour in a BESS diode is shown in Fig. 3. The simulated profile shows that the potential falls near the buried oxide interface due to the dielectric discontinuity. The hole current density vector simulated in Fig. 4(a) also shows that a higher current flow can be observedjust above the buriedoxideinterf
{"title":"Suppression Of Bit-line-induced Disturbance In SOI DRAM/SRAM Cells By Bipolar Embedded Source Structure (BESS)","authors":"Horiuchi, Sakata, Kimura","doi":"10.1109/VLSIT.1997.623746","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623746","url":null,"abstract":"The disturbance of stored charges in SO1 memory cells, which is caused by floating body effects, is fully suppressed by using an access transistor with a bipolar embedded source structure just beneath the n'junction. This structure is free from the subthreshold leakage current and degradation caused by high source resistance. Introduction The use of SO1 in future-generation DRAM technology promises to facilitate the wide spread of SO1 CMOS as the main technology for ULSI systems. The greatestbarrier that stands in the way of this is the notorious floating body effects which cause bit-line-induced disturbances in memory cells [l]. In Sol, minority carriers generated in the body forward bias the body-bit-line diode when the bit-line potential falls to a low level. This forward junction injects minority caniers across the channel into the storage node, upsetting the stored charge even if the word line is deactivated This type of disturbance seriously shortens the dynamic retention characteristicsor, in other words degrade the refresh time properties. This paper presents a possible solution that fully suppresses the floating body effects and bit-line-induced disturbances in SOICMOSFETs without sacrificing their excellent performance. Device Outline A schematic cross-section of a bipolar embedded source structure (BESS) device [2] is shown in Fig. 1. In an nchannel access transistor, p-type recombination centers are embedded in the nsourcddrain regions adpen t to the SOUburied oxide interface. A generated hole in the p-type body can easily diffuse to a source recombination center through the nsource bypass which has a low built-in potential barrier. Thus, hole recombination in the source prevents the floating body problems. /cmZ) with a projection range to the SOI/buried oxide interface followed by recrystallization annealing creates the recombination centers, leading to the formation of a small grain poly-Si region. This structure is independent of the source /drain profile near the gate edges, and there is no degradation of device properties. The bit-line induced disturbance in the SO1 DRAM cells can be evaluated with the simple test circuit shown in Fig. 2. In the test circuit, the storagecapacitor (Cpad=0.75 pF)) was made by connecting two bonding pads of the accessand sense-transistors with a conductive paste. The on-wafer measurements were carried out with an external load resistor connected to the sense transistor. High-dose Si implanted amorphization Simulated Results The forward hole current properties at the source diode are directly related to the floating-body-immune properties. A numerical simulation of a fonvard-biased (0.5 V) potential contour in a BESS diode is shown in Fig. 3. The simulated profile shows that the potential falls near the buried oxide interface due to the dielectric discontinuity. The hole current density vector simulated in Fig. 4(a) also shows that a higher current flow can be observedjust above the buriedoxideinterf","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130104948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623687
Yamamoto, Ogura, Saito, Uwasawa, Tatsumi, Mogami
Ultrathin gate dielectrics are important to realize high performance and low-voltage operation CMOS devices. An advanced ultrathin gate dielectric formation process, that is, direct nitridation of silicon and sequential oxidation, is proposed and evaluated to suppress boron penetration and to improve hot-carrier reliability. No boron penetration, longer hot-carrier lifetime and high drain current are achieved in MOSFETs with 2.5nm oxidized nitride gate dielectric.
{"title":"An Advanced 2.5nm Oxidized Nitride Gate Dielectric For Highly Reliable 0.25/spl mu/m MOSFETs","authors":"Yamamoto, Ogura, Saito, Uwasawa, Tatsumi, Mogami","doi":"10.1109/VLSIT.1997.623687","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623687","url":null,"abstract":"Ultrathin gate dielectrics are important to realize high performance and low-voltage operation CMOS devices. An advanced ultrathin gate dielectric formation process, that is, direct nitridation of silicon and sequential oxidation, is proposed and evaluated to suppress boron penetration and to improve hot-carrier reliability. No boron penetration, longer hot-carrier lifetime and high drain current are achieved in MOSFETs with 2.5nm oxidized nitride gate dielectric.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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