Introduction In order to achieve <400mm2 chip size for lGDRAM production, 0.3um pitch fine patterning must be needed. Lithographic printability will be one of serious problems in this generation. In COB type DRAM cell, active area pattem is a kind of problem for both of bitline (BL) and storage node (SN) connections. Simple mask pattem is first key to get a large exposure defocus window. Cell size is represented as a proportion to minimum feature size (F) square. Several studies about 13F2 cell size have been reported for 0.4um pitch devices [ 1,2,3]. Based on historical trends, -8F2 technology will be needed in 0.3um pitch generation. SN contact self-aligned to BL is also second key to realize 8F2 cell. It has been pointed out that wafer planarity throughout the process is third key to achieve a large process window [4]. Especially, this issue is more severe in COB cell. In this paper, relaxed 0.44um pitch memory cell array is demonstrated and three key technologies are adopted such as self-aligned poly plug technology using printable mask pattem, cross point contact technology for SN contact selfaligned to BL, and plariarized concave capacitor technology. Self-aligned Poly Plug Figures 1 and 2 show schematic top view and cross sections to explain self-aligned poly plug technology, respectively. Following simple pattemed active area formation using nomial STI process, straight gate was pattemed, which was (composed of WSi polycide with SiN hard mask. Barrier Sip? and reflowed BPSG interlayer were deposited. BPSG was planarized using CMP stopped by barrier SiN (Fig.2a). SAC was opened by BPSG etching selectively to SIN using Gate SAC mask shown in Fig.1. Gate SAC pattem is t h e same as active area and is shifted by a half pitch to gate direction. Cross sectional SEM photograph after SAC opening is shown in Fig.3. Phosphorous-doped polysilicon was deposited and planarized down to Gate SiN by CMP (Fig.2b), resulting in dense poly plugs self-aligned to gate. Poly plug top view SEM photograph is shown in Fig. 4. Cross Point Contact BL and SN contact formation are explained with Fig.5. After interlayer deposition, straight BL was pattemed and spacer SIN was formed on side walls. BL wiring was fabricated using damaxene tungsten (FigSa). Then, tungsten was etched back and capped with SIN hard mask (FigSb). SiN capping was performed by SiN CMP etching selectively to SiOz. Interlayer was etched selectively to cap SiN using straight SN contact mask perpendicular to BL. Therefore, SN contact was opened at cross point of two levels. Cross point contact with cross sectional SEM photograph is shown in Fig.6. After contact SiN liners were formed as contact inner walls (Fig.%), phosphorous-doped polysilicon was deposited and planarized down to cap SiN by CMP (FigSd). Etched back tungsten sheet resistance distribution is acceptable for BL as shown in Fig.7. Concave Capacitor Figure 8 shows process steps forming planarized concave capacitor, After interlayer depo
{"title":"A Fully Printable, Self-aligned And Planarized Stacked Capacitor DRAM Cell Technology For 1Gbit DRAM And Beyond","authors":"Kohyama, Ozaki, Yoshida, Ishibashi, Nitta, Inoue, Nakamura, Aoyama, Imai, Hayasaka","doi":"10.1109/VLSIT.1997.623673","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623673","url":null,"abstract":"Introduction In order to achieve <400mm2 chip size for lGDRAM production, 0.3um pitch fine patterning must be needed. Lithographic printability will be one of serious problems in this generation. In COB type DRAM cell, active area pattem is a kind of problem for both of bitline (BL) and storage node (SN) connections. Simple mask pattem is first key to get a large exposure defocus window. Cell size is represented as a proportion to minimum feature size (F) square. Several studies about 13F2 cell size have been reported for 0.4um pitch devices [ 1,2,3]. Based on historical trends, -8F2 technology will be needed in 0.3um pitch generation. SN contact self-aligned to BL is also second key to realize 8F2 cell. It has been pointed out that wafer planarity throughout the process is third key to achieve a large process window [4]. Especially, this issue is more severe in COB cell. In this paper, relaxed 0.44um pitch memory cell array is demonstrated and three key technologies are adopted such as self-aligned poly plug technology using printable mask pattem, cross point contact technology for SN contact selfaligned to BL, and plariarized concave capacitor technology. Self-aligned Poly Plug Figures 1 and 2 show schematic top view and cross sections to explain self-aligned poly plug technology, respectively. Following simple pattemed active area formation using nomial STI process, straight gate was pattemed, which was (composed of WSi polycide with SiN hard mask. Barrier Sip? and reflowed BPSG interlayer were deposited. BPSG was planarized using CMP stopped by barrier SiN (Fig.2a). SAC was opened by BPSG etching selectively to SIN using Gate SAC mask shown in Fig.1. Gate SAC pattem is t h e same as active area and is shifted by a half pitch to gate direction. Cross sectional SEM photograph after SAC opening is shown in Fig.3. Phosphorous-doped polysilicon was deposited and planarized down to Gate SiN by CMP (Fig.2b), resulting in dense poly plugs self-aligned to gate. Poly plug top view SEM photograph is shown in Fig. 4. Cross Point Contact BL and SN contact formation are explained with Fig.5. After interlayer deposition, straight BL was pattemed and spacer SIN was formed on side walls. BL wiring was fabricated using damaxene tungsten (FigSa). Then, tungsten was etched back and capped with SIN hard mask (FigSb). SiN capping was performed by SiN CMP etching selectively to SiOz. Interlayer was etched selectively to cap SiN using straight SN contact mask perpendicular to BL. Therefore, SN contact was opened at cross point of two levels. Cross point contact with cross sectional SEM photograph is shown in Fig.6. After contact SiN liners were formed as contact inner walls (Fig.%), phosphorous-doped polysilicon was deposited and planarized down to cap SiN by CMP (FigSd). Etched back tungsten sheet resistance distribution is acceptable for BL as shown in Fig.7. Concave Capacitor Figure 8 shows process steps forming planarized concave capacitor, After interlayer depo","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126198518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623712
Hsiao, Ping Liu, Woo
A novel salicide technology for ultra-thin SO1 films is proposed. Ge pre-amorphization is used to facilitate the silicide formation at low tcmperaturc (- 400°C) and effectively control the silicide depth without void formation. Sub-0.25 pm SO1 CMOS devices fabricated using this advanced technology have shown substantially reduced source/drain resistance as well as good electrical results.
{"title":"An Advanced Ge Pre-amorphization Salicide Technology For Sub-quarter-micrometer SOI CMOS Devices","authors":"Hsiao, Ping Liu, Woo","doi":"10.1109/VLSIT.1997.623712","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623712","url":null,"abstract":"A novel salicide technology for ultra-thin SO1 films is proposed. Ge pre-amorphization is used to facilitate the silicide formation at low tcmperaturc (- 400°C) and effectively control the silicide depth without void formation. Sub-0.25 pm SO1 CMOS devices fabricated using this advanced technology have shown substantially reduced source/drain resistance as well as good electrical results.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115859165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 0.6 p pitch highly reliable multilevel interconnection technology using low-k Hydrogen Silicate Based Inorganic Spinon Glass (HSI-!SOG) is demonstrated for 0.15 p CMOS devices. A stable HSI-SOG interlayer dielectric (ILD) with low leakage current is realized in the metallization process with above 400 “c. The reliability of wiring and MOSFET is superior to that of the conventional high-density plasma CVD Si02 (HDP S i 0 4 ILD. A new via formation process using an NH3 plasma treatment achieves low via resistance of 4 Cl at 0.28 pm in diameter. In addition, the device performance is also improved by the 25 % reduction in wiring capacitance. Introduction Low-k ILD is indispensable to high performance W I such as high-end process,ors and “System on a chip”, because it can reduce not only the wiring delay but also power dissipation [l]. Though organic polymers [2] have very low dielectric constants (~=2.0-2.5), they have some problems such as the thermal instability or the difficulty of via formation. HSI-SOG is very attractive because of its low dielectric constant and high thermal stability which t a maintain compatibility with conventional metallization process. There are several reports that have investigated the performance of inorganic SOG in 0.35 pm technology[3, 41. However, the integration issues such as via resistance, wiring reliability and transistor reliability have not been evaluated falr sub-quarter-micron CMOS. In this paper, integration of HSI-SOG into total CMOS process in 0.15 p generation is examined. An NH3 plasma treatment technology is proposed to avoid poisoned vias. The reliability of wining and hot-carrier immunity of MOSFET, as well as the device performance, are also evaluated. Experimental A 0.6 pm pitclh multilevel metallization using HSI-SOG was constructed on 0.15 pm CMOS. In ILD process, plasma-TEOS Si02 was deposited on HSI-SOG, followed by planarization using CMP. The via formation process is shown in Fig. 1. After resist stripping, ithe NH3 plasma treatment was performed to passivate the sidewalls of the vias. The maximum process temperature was 420 “c at the W CVD step. Evaluated feature sizes are from 0.3/0.3 to 0.5/0.5 pm for wiring line/space and from 0.28 to 0.5 pm for vias. Results and Discussion An SEM cross-sectional view of the multilevel metallization is shown in Fig. 2. A good gap-filling capability is observed in spaces down to 0.3 pm. No crack is observed after the metallization process. Measured adjacent wiring capacitance is shown in Fig. :3. Wiring capacitance is reduced by 25 % compared with the HDP Si02. The estimated dielectric constant of HSI-SOG is 3.0. Simulated Tpd for 0.15 pm CMOS 2NAND with wiring is shown in Fig. 4. The HSI-SOG ILD achieves 18 % reduction in Tpd for the typical global wiring length of 10 mm, compared with the HDP-Si02 LLD. The leakage current between the adjacent metals is shown in Fig. 5. The leakage current is stable and comparable to HDPSi02 ILD even at 0.3 pm wiring s
{"title":"0.6 /spl mu/m Pitlch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG For Sub-quarter Micron CMOS Technology","authors":"Oda, Usami, Kishimoto, Matsumoto, Mikagi, Kikuta, Gomi, Sakai","doi":"10.1109/VLSIT.1997.623704","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623704","url":null,"abstract":"A 0.6 p pitch highly reliable multilevel interconnection technology using low-k Hydrogen Silicate Based Inorganic Spinon Glass (HSI-!SOG) is demonstrated for 0.15 p CMOS devices. A stable HSI-SOG interlayer dielectric (ILD) with low leakage current is realized in the metallization process with above 400 “c. The reliability of wiring and MOSFET is superior to that of the conventional high-density plasma CVD Si02 (HDP S i 0 4 ILD. A new via formation process using an NH3 plasma treatment achieves low via resistance of 4 Cl at 0.28 pm in diameter. In addition, the device performance is also improved by the 25 % reduction in wiring capacitance. Introduction Low-k ILD is indispensable to high performance W I such as high-end process,ors and “System on a chip”, because it can reduce not only the wiring delay but also power dissipation [l]. Though organic polymers [2] have very low dielectric constants (~=2.0-2.5), they have some problems such as the thermal instability or the difficulty of via formation. HSI-SOG is very attractive because of its low dielectric constant and high thermal stability which t a maintain compatibility with conventional metallization process. There are several reports that have investigated the performance of inorganic SOG in 0.35 pm technology[3, 41. However, the integration issues such as via resistance, wiring reliability and transistor reliability have not been evaluated falr sub-quarter-micron CMOS. In this paper, integration of HSI-SOG into total CMOS process in 0.15 p generation is examined. An NH3 plasma treatment technology is proposed to avoid poisoned vias. The reliability of wining and hot-carrier immunity of MOSFET, as well as the device performance, are also evaluated. Experimental A 0.6 pm pitclh multilevel metallization using HSI-SOG was constructed on 0.15 pm CMOS. In ILD process, plasma-TEOS Si02 was deposited on HSI-SOG, followed by planarization using CMP. The via formation process is shown in Fig. 1. After resist stripping, ithe NH3 plasma treatment was performed to passivate the sidewalls of the vias. The maximum process temperature was 420 “c at the W CVD step. Evaluated feature sizes are from 0.3/0.3 to 0.5/0.5 pm for wiring line/space and from 0.28 to 0.5 pm for vias. Results and Discussion An SEM cross-sectional view of the multilevel metallization is shown in Fig. 2. A good gap-filling capability is observed in spaces down to 0.3 pm. No crack is observed after the metallization process. Measured adjacent wiring capacitance is shown in Fig. :3. Wiring capacitance is reduced by 25 % compared with the HDP Si02. The estimated dielectric constant of HSI-SOG is 3.0. Simulated Tpd for 0.15 pm CMOS 2NAND with wiring is shown in Fig. 4. The HSI-SOG ILD achieves 18 % reduction in Tpd for the typical global wiring length of 10 mm, compared with the HDP-Si02 LLD. The leakage current between the adjacent metals is shown in Fig. 5. The leakage current is stable and comparable to HDPSi02 ILD even at 0.3 pm wiring s","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121856501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623695
Mansfield, Bude, Cerullo, Klemens, Mastrapasqua, Weber, Woon Wal Tal
A TiN gate cladding layer, an integral part of an advanced ASIC CMOS process for resistance and Vth control, is selectively insulated from the underlying polysilicon gate by a thin dielectric to form a CMOS compatible floating gate transistor. The resulting stacked gate device is formed concurrent to the CMOS devices having essentially the same vertical profile. Device measurements indicate the new structure behaves electrically the same as conventional stacked double-polysilicon floating gate devices.
{"title":"A Novel CMOS Compatible Stacked Floating Gate Device Using TiN As A Control Gate","authors":"Mansfield, Bude, Cerullo, Klemens, Mastrapasqua, Weber, Woon Wal Tal","doi":"10.1109/VLSIT.1997.623695","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623695","url":null,"abstract":"A TiN gate cladding layer, an integral part of an advanced ASIC CMOS process for resistance and Vth control, is selectively insulated from the underlying polysilicon gate by a thin dielectric to form a CMOS compatible floating gate transistor. The resulting stacked gate device is formed concurrent to the CMOS devices having essentially the same vertical profile. Device measurements indicate the new structure behaves electrically the same as conventional stacked double-polysilicon floating gate devices.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116860756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623682
Chyan, Chaudhry, Ma, Chen, Carroll, Nagy, Becerro, Lee, Iannuzzi
In this paper, an epi-free, manufacturable, and high performance 3.3 V 0.35 pm High-Energy Implanted BiCMOS (HEIBiC) technology will be presented. The developed HEIBiC process includes a single-polysilicon NPN bipolar transistor with product of 138 GHzV is shown to be one of the best results for silicon BiCMOS without an epitaxial buried collector.
本文将介绍一种无外源性、可制造、高性能的3.3 V 0.35 pm高能植入BiCMOS (HEIBiC)技术。所开发的HEIBiC工艺包括单多晶硅NPN双极晶体管，其积为138 GHzV，是无外延埋式集电极的硅BiCMOS的最佳结果之一。
{"title":"A Very High Performance, Epi-free, And Manufacturable 3.3 V 0.35 /spl mu/m BiCMOS Technology For Wireless Applications","authors":"Chyan, Chaudhry, Ma, Chen, Carroll, Nagy, Becerro, Lee, Iannuzzi","doi":"10.1109/VLSIT.1997.623682","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623682","url":null,"abstract":"In this paper, an epi-free, manufacturable, and high performance 3.3 V 0.35 pm High-Energy Implanted BiCMOS (HEIBiC) technology will be presented. The developed HEIBiC process includes a single-polysilicon NPN bipolar transistor with product of 138 GHzV is shown to be one of the best results for silicon BiCMOS without an epitaxial buried collector.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have introduced a new flash array architecture called AMG a t e r n a t e Metal virtual Ground) to address the high density and low voltage (3V only) applications. A 2.lpm2 cell size is demonstrated with 0.6pm design rules. A low current programming technique has been developed to enable low voltage operation. A segmented array architecture is introduced t,o eliminat,e cycling induced program-erase disturbs. An innovative planarized array DPCC (Double Poly Contact Circuit) process is developed to reahze the AMG architecture. INTRODUCTION In recent years, the feature size h is being scaled to realize the flash memory products [I] [ 2 ] . We'have realized a new flash virtual ground architecture [3] t,o provide a scaling pa th for high density and low voltage products. The cell size (5.8h2) scaling is obtained without the aggressive metallcontact design rules of the standard NOR (10h2) or the high voltage and access speed penalty of the NAND approach (6.5h2) [4]. Alternate Metal Virlual Ground (AMG) EPROM array concept [5] has been demonstrated in production as . a viable scaling concept with a poly pitch limited cell size (4x2) and one metal line for two diffusion bitlines. The AMG flash architecture is a scalable concept where the AMG cell can be scaled to 0.7pm2 with 0.35pm design rules. The array is a segmented virtual ground array with dedicated buried diffusion bitlines for program and erase operations. The programming and erase operations in the array are based on the well characterized standard NOR channel hot electron programming and negative gate source erase. Electron injection efficiency of the flash cell has been enhanced 161 in order to provide low current programming. AMG FLASH ARRAY The AMG flash array s c h e m h c is shown in fig.1 There are two h n d s of junctions for the diffusion lines in the flash cell area. The flash cell is programmed using channel hot electron programming a t the abrupt junction and erased with Fowler Nordheim tunneling a t the graded junction. The array is segmented with Block select BL SEL n and accomodates 128 WLs leading to the select area overhead of approximately 10%. The truth table for the array operational modes is summarized in fig.:!. The indlvidual cells are accessed by choosing the Block The select transistors are n-channel transistors with gate oxide of 200A . The integration in the array is made possible by utilizing the DPCC process 171. The select channel length tracks the flash cell poly length variations. This array architecture configures very naturally to wordhne block oriented sectorization for erase. The block selection feature offers advantages for disturb immunity, bitline capacitance reduction and sector erase, utilizing only single level metal in the array. AMG PROCESS FLOW The AMG flash process incorporates definition of minimum polyl pitch and minimum poly2 spacing. The process flow is summarized in fig. 3. In order to achieve minimum cell size a 3kA LOCOS field oxide is empl
{"title":"A New Flash Architecture With A 5.8/spl lambda//sup 2/ Scalable AMG Flash Cell","authors":"Roy, Kazerounian, Irani, Prabhakar, Nguyen, Slezak, Trinh, Kauk, Agarwal, Eitan, Annunziata, Camerlenghi, Campisi, Cappelletti, Colabella, Crisenza, Dallabora, Fontana, Tosi","doi":"10.1109/VLSIT.1997.623698","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623698","url":null,"abstract":"We have introduced a new flash array architecture called AMG a t e r n a t e Metal virtual Ground) to address the high density and low voltage (3V only) applications. A 2.lpm2 cell size is demonstrated with 0.6pm design rules. A low current programming technique has been developed to enable low voltage operation. A segmented array architecture is introduced t,o eliminat,e cycling induced program-erase disturbs. An innovative planarized array DPCC (Double Poly Contact Circuit) process is developed to reahze the AMG architecture. INTRODUCTION In recent years, the feature size h is being scaled to realize the flash memory products [I] [ 2 ] . We'have realized a new flash virtual ground architecture [3] t,o provide a scaling pa th for high density and low voltage products. The cell size (5.8h2) scaling is obtained without the aggressive metallcontact design rules of the standard NOR (10h2) or the high voltage and access speed penalty of the NAND approach (6.5h2) [4]. Alternate Metal Virlual Ground (AMG) EPROM array concept [5] has been demonstrated in production as . a viable scaling concept with a poly pitch limited cell size (4x2) and one metal line for two diffusion bitlines. The AMG flash architecture is a scalable concept where the AMG cell can be scaled to 0.7pm2 with 0.35pm design rules. The array is a segmented virtual ground array with dedicated buried diffusion bitlines for program and erase operations. The programming and erase operations in the array are based on the well characterized standard NOR channel hot electron programming and negative gate source erase. Electron injection efficiency of the flash cell has been enhanced 161 in order to provide low current programming. AMG FLASH ARRAY The AMG flash array s c h e m h c is shown in fig.1 There are two h n d s of junctions for the diffusion lines in the flash cell area. The flash cell is programmed using channel hot electron programming a t the abrupt junction and erased with Fowler Nordheim tunneling a t the graded junction. The array is segmented with Block select BL SEL n and accomodates 128 WLs leading to the select area overhead of approximately 10%. The truth table for the array operational modes is summarized in fig.:!. The indlvidual cells are accessed by choosing the Block The select transistors are n-channel transistors with gate oxide of 200A . The integration in the array is made possible by utilizing the DPCC process 171. The select channel length tracks the flash cell poly length variations. This array architecture configures very naturally to wordhne block oriented sectorization for erase. The block selection feature offers advantages for disturb immunity, bitline capacitance reduction and sector erase, utilizing only single level metal in the array. AMG PROCESS FLOW The AMG flash process incorporates definition of minimum polyl pitch and minimum poly2 spacing. The process flow is summarized in fig. 3. In order to achieve minimum cell size a 3kA LOCOS field oxide is empl","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121942679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623736
Maejima, Saitoh, Hayashi
SrBi2Ta20p (SBT) film is patterned by ECR plasma etching, and the effects of plasma gas species on the ferroelectric properties are investigated. A non-reductive C12/Ar gas, instead of a reductive BClJAr gas, suppresses the etching damage drastically, lowering the annealing temperature to release the damage after etching. A SBT capacitor with a remnant polarization of 15&/cm2 and a low leakage current ( < l f l c m 2 ) is successfully obtained.
采用ECR等离子体刻蚀法制备了SrBi2Ta20p (SBT)薄膜，研究了等离子体气体种类对薄膜铁电性能的影响。非还原性的C12/Ar气体代替还原性的BClJAr气体，显著抑制了蚀刻损伤，降低了退火温度以释放蚀刻后的损伤。成功地获得了残余极化为15&/cm2和低漏电流(< 1 f 1 cm2)的SBT电容器。
{"title":"Low-damage ECR-plasma-etching technique for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) capacitor for FeRAM devices","authors":"Maejima, Saitoh, Hayashi","doi":"10.1109/VLSIT.1997.623736","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623736","url":null,"abstract":"SrBi2Ta20p (SBT) film is patterned by ECR plasma etching, and the effects of plasma gas species on the ferroelectric properties are investigated. A non-reductive C12/Ar gas, instead of a reductive BClJAr gas, suppresses the etching damage drastically, lowering the annealing temperature to release the damage after etching. A SBT capacitor with a remnant polarization of 15&/cm2 and a low leakage current ( < l f l c m 2 ) is successfully obtained.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623708
Furukawa, Teramoto, Shimizu, Abe, Tokuda
Significant effects of rapid thermal annealing treatment, which was inserted before the gate oxidation, on MOSFETs characteristics have been studied in detail. The reduction of the threshold voltage and the enhancement of the transconductance were achieved for NMOSFETs, whereas a shallow and high channel doping profile was obtained for PMOSFETs. These results, which are promising for constructing high-performance single gate CMOS devices, were interpreted in terms of the suppression of transient diffusion such as B outside diffusion and B segregation into thc gatc oxide, which were enhanced by residual damage induced by high energy ion implantation.
{"title":"Channel Profile Control Based On Transient-enhanced-diffusion Suppression By RTA For 0.18 /spl mu/m Single Gate CMOS","authors":"Furukawa, Teramoto, Shimizu, Abe, Tokuda","doi":"10.1109/VLSIT.1997.623708","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623708","url":null,"abstract":"Significant effects of rapid thermal annealing treatment, which was inserted before the gate oxidation, on MOSFETs characteristics have been studied in detail. The reduction of the threshold voltage and the enhancement of the transconductance were achieved for NMOSFETs, whereas a shallow and high channel doping profile was obtained for PMOSFETs. These results, which are promising for constructing high-performance single gate CMOS devices, were interpreted in terms of the suppression of transient diffusion such as B outside diffusion and B segregation into thc gatc oxide, which were enhanced by residual damage induced by high energy ion implantation.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116543487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623731
Wong, Farrell, Ferguson, Mansfield, Molless, Neisser, Nunes, Samuels, Thomas
Introduction Phase-shifting masks (PSMs) [1][2] and modified illumination techniques [3] have shown promise in improving the resolution and process latitude of lithography. For 1 Gb-DRAM application, these techniques are essential because printing 175 nm features is pushing the limits of even high numerical aperture (NA) deep-UV exposure systems, and wavelength reduction is not an alternative until the availability of 193 nm exposure systems around the turn of the century. This paper explores the application of attenuated PSM [2] and alternating PSM [l], as well as annular illumination [3] in the optimization of lithographic performance at the 175 nm groundrule. Lithographic simulation including the effects of photoresist processing [4] was used to identify optimal conditions for critical levels of a 1 Gb-DRAM cell design [5], and improvement in performance was quantified experimentally. Process Optimization To ensure reliability of the 1 Gb cell requires the control of feature edge placement to within 17.5nm (&lo%). Based on this criterion, exposure-defocus analyses [6] were performed on the viable resolution enhancement techniques, and their relative merits are quantified in terms of depth-of-focus (DOF) with 10% exposure dose variation. Simulation is performed using SPLAT [7] and an internal IBM program LEOPOLD which models the important effects of photoresist processing. Fig. 1 shows the mask and illumination techniques examined. For each critical level, the three approaches which give the largest DOF (at 10% exposure latitude) are listed in Table 1 together with the design layout. The latitude obtained with conventional chromium (COG) mask and standard illumination is also included for reference. In general, annular illumination and alternating PSM are strong candidates for grating-like levels, while attenuated PSM provides the most benefit for contact levels. It is of interest to note the use of negative resist for the active area (AA) level. Fig. 2 illustrates the improvement in image integrity with resolution enhancement techniques for the AA level. The contours represent aerial image intensity in steps of 0.1 normalized to the clear field intensity. For a COG mask with standard illumination, the intensity contours are sparse in both the width (horizontal) and length (vertical) directions, indicating poor image quality and resulting in a DOF of only 0.4 pm. For an attenuated PSM with annular illumination, the intensity contours are denser, resulting in an improved DOF of 1.2 pm. With an alternating PSM at a reduced partial coherence factor of 0.3, the intensity gradient is especially steep at the ends of the feature due to the effects of phase-shifting. This manifests as a better DOF of 1.4 pm and improved line-end shortening behavior: the length is only biased at lOOnm as opposed to 150nm on the COG and attenuated PSM. Mask imperfection limits and in some cases obliterates the benefits of PSMs. Fig. 3 shows the DOF for a 225nm bitline co
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Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623738
Bo Jiang, Zurcher, Jones, Gillespie, Lee
A new computationally efficient and accurate model for ferroelectric capacitors is presented. This model uses a unique algorithm to account for the history dependence of ferroelectric capacitors, and the charge-voltage relationship, Q(v is described by a set of analytical functions with few parameters that can be easily extracted from electrical measurements of test capacitors. This model has been successfully implemented into SABER. Comparisons of simulation results with measurements show an outstanding predictive ability for arbitra voltage inputs. INTRODUCTI~N The growing interests in using ferroelectric materials in integrated circuits, especially in memory applications require accurate models for ferroelectric capacitors for circuit simulation and optimization. However, the Q-V (or C-v) relationships of ferroelectric capacitors are nonlinear and have nonlocal memories [1,2], i.e., the state of a capacitor is not uniquely determined by its present position on the Q-V plane, but also depends on voltage experienced at previous times. Most of the previous circuit models either do not [3,4] or incorrectly account for the history dependence [ 5 ] . Others require detailed information of microscopic material structure and complicated numerical analysis which is difficult to implement into a circuit simulator [6]. In this work, we found that the complex behavior of a ferroelectric capacitor is similar to that of Preisach hysteresis, widely used in the area of ferromagnetics [ 2 ] . We present a computationally efficient model that incorporates all of the major properties of Preisach hysteresis and correctly accounts for the history dependence of ferroelectric capacitor. For simplicity, time dependent effects such as polarization relaxation are neglected. THE MODEL A Preisach hysteresis is a macroscopic system that can be represented as a superposition of simple hysteresis units, and each unit has a rectangular hysteresis loop [2]. In the case of a ferroelectric thin film capacitor, it can be represented as a system of parallelly connected, non-interacting units as shown in Fig. 1. The switching charge 0, and the coercive voltages a and , B for each unit can be different, Let p(a ,B) describe the coercive voltage distribution, and D,p is the direction operator such that DCpV(t) = 1(-1) if the unit with coercive voltages (a,p) is switched to the positive (negative) polarity at time t . The total charge can then be written as Q ( t ) = Aa>P)fiapJ’(t)da@‘ (1) The Preisach type model can be numerically implemented by using Eq. 1. Although this approach is straightforward, it requires the numerical evaluation of double integrals in Eq. 1, which is a time-consuming procedure. In addition, the determination of the coercive voltage distribution p(a,,B) requires differentiations of experimentally obtained data. These differentiations may strongly amplify errors or noise inherently present in any experimental data. In this work, we present a method that incorp
提出了一种新的计算效率高、精度高的铁电电容器模型。该模型采用了一种独特的算法来考虑铁电电容器的历史依赖性，并且电荷电压关系Q(v)由一组具有很少参数的解析函数描述，可以很容易地从测试电容器的电测量中提取。该模型已成功应用于SABER。仿真结果与实测结果的比较表明，对任意电压输入具有出色的预测能力。在集成电路中使用铁电材料的兴趣日益增长，特别是在存储应用中，需要精确的铁电电容器模型来进行电路仿真和优化。然而，铁电电容器的Q-V(或C-v)关系是非线性的，并且具有非局部记忆[1,2]，即电容器的状态不仅取决于其在Q-V平面上的当前位置，还取决于以前时间所经历的电压。大多数以前的电路模型要么没有[3,4]，要么不正确地考虑历史依赖[5]。另一些需要详细的微观材料结构信息和复杂的数值分析，难以在电路模拟器[6]中实现。在这项工作中，我们发现铁电电容器的复杂行为与广泛应用于铁磁领域的Preisach滞回相似。我们提出了一个计算效率高的模型，该模型包含了Preisach迟滞的所有主要特性，并正确地考虑了铁电电容器的历史依赖性。为简单起见，忽略了极化弛豫等时间相关效应。Preisach迟滞是一个宏观系统，可以表示为简单迟滞单元的叠加，每个单元都有一个矩形迟滞回路[2]。在铁电薄膜电容器的情况下，它可以表示为如图1所示的并联、非相互作用单元的系统。每个单元的开关电荷0和矫顽力电压a、B可以不同，设p(a,B)描述矫顽力电压分布，D,p为方向算子，当具有矫顽力电压(a,p)的单元在时间t切换到正(负)极性时，使DCpV(t) = 1(-1)。总电荷可以写成Q (t) = Aa>P)fiapJ ' (t)da@ ' (1) Preisach类型模型可以通过使用Eq. 1在数值上实现。虽然这种方法很简单，但它需要对Eq. 1中的二重积分进行数值计算，这是一个耗时的过程。此外，确定矫顽力电压分布p(a，，B)需要对实验得到的数据进行微分。这些差异可能会强烈放大任何实验数据中固有的误差或噪声。在这项工作中，我们提出了一种方法，结合了Preisach滞后的特殊性质，同时完全绕过了上述困难。Preisach类型模型的详细研究和这些性质的严格证明可以在[2]中找到。为清楚起见，在下面的讨论中省略了对净电荷的线性贡献。它可以很容易地包括以后通过添加一个线性电容器C1与铁电元件并联。A.饱和曲线-预紧磁滞和铁电磁滞的一个重要特性是定义良好的饱和回路。无论电容器以前的历史如何，QV点必须始终位于饱和回路上或在饱和回路内;在任意给定的Q-V点上，dQ/dV的大小必须不大于同一V点上相同方向的饱和曲线的大小。设F (V)和F & (V)分别表示饱和回路的上升支路和下降支路。只要符合实验回路，它们可以采用任何功能形式。这里选择双曲正切，因为它简单，具有正确的物理性质，并且对大多数铁电薄膜电容器提供了合理的适用性，即，其中Qs为铁电开关的最大电荷贡献，Vc+， (Vc)为上升曲线(下降曲线)的转换电压，参数a描述了双曲正切接近Q,s的速度(见图2)。B.记忆形成-通过跟踪Q- v平面上以前的转折点，“记住”电容器的以前的历史。转折点是Q-V曲线改变方向或dV/dt改变符号的地方(见图3)。用+(-)符号来区分V (t)是局部最大值(最小值)的点。虽然Preisach迟滞具有非局部记忆，但并非所有先前的历史都需要被“记住”。 例如，由于饱和回路定义良好，如果在电容器上施加一个大电压，使其Q-V点在饱和曲线上，其未来的行为不再取决于其过去的历史。更具体地说，只有主导输入电压极值的交变序列是重要的(见图4)。表1显示了存储器中的转折点如何不断被清除和更新的一些示例。由于这种内存清除特性，需要存储的点的数量通常不会随时间连续增长。默认情况下，饱和回路的终点(m,QLy)和(-m，-Q&)，分别用S和-S表示，始终是存储在内存中的前两个转折点，永远不会被清除。C.饱和环路内-一旦Q-V点在饱和环路内，随着电压的升高(降低)，QV曲线总是经过存储在内存中的先前的+(-)转折点(见图5)。连接任意两个相邻转折点(vi, q，)和(~ ~ + ~，q)的q - v曲线;+ ~)，用f I ?(V)或f, J (V)由m和b给出，其中m和b是需要为每对转折点确定的系数，使得qi = m, f $ (V，) + b和q，+1 = mjf2 (V，+l) + b保持不变。可以证明，F 1 (VI) = qstanh [a(V, V，， I] (2) F， $ (V) = m I F $ (V + b / (3) 4;- qi + 1f1 (v, f1 (vi+， m) =总是在0和1之间。这意味着df, 1 idV I df $ idV，或饱和环路内任何一点的dQ/dV的大小总是相同v下饱和环路的一小部分。模拟结果和讨论将模型模拟与经历复杂输入电压序列的2000A SrBi,Ta,O薄膜电容器的实验数据进行比较(图6-8)。模型参数QS, Vc。+、Vr-、U和C/由饱和回路的实验测量得到。除非另有说明，否则该模型假定初始Q-V点位于饱和回路上，因此开始时内存中的唯一转折点是S和-S。对于所有情况，该模型正确地描述了SBT电容器的历史依赖性和记忆形成。预测的QV曲线与实验数据吻合较好。[14]张斌，等。集成电极技术的研究进展[j]。， 1997年出版。[2] 1。11. 迟滞的数学模型，斯普林格出版社，纽约，1991。[4] A. K. Kulkarni等，铁选择性。， 116(1-2)，第95页，1991。电极2 b[4] D. E. Dunn, IEEE译。超音波学，铁电学，[j]。物理学报，30 (5)，p. 391 - 397。，61 p，赵志强等，，C与频率控制，41 (3)，p.3, 1994。(4 p.205, 1995。图1所示。(a)应用于铁电薄膜电容器的Preisach模型。(b)每个单元的Q-V曲线必须位于矩形回路上。随着电压的增加，上升支路如图2。仅包括铁电偶极子开关贡献的饱和曲线由式2描述。Abcde紧随其后;当电压降低时，跟踪下降支路edfba。这个循环不必是关于OV对称的。总电荷是所有单位的总和。图3。0-V电压转折点。极值存储在内存中。所有其他输入极值的例子表明，电容%的输出都被消灭了。对于所示的特定脉冲序列，在_，_ %饱和回路并通过a, b, C, d时间为，存储在存储器中的电压极值为:!a, 6, c, d点。到达d点后，随着volt@e的减小，q曲线再次经过?然后是a，然后是表1。说明内存清除属性的示例。-'所经历的电压极值。从上到下依次列出了铁电电容器的Q值。存储在模型中的电压是成对擦除的。每一个新的局部最大值都会擦除之前等于或小于它的局部最大值及其后面的局部最小值;每一个新的局部最小值都会擦除之前等于或大于一天的局部最小值，a-S由式3给出。图6 (d)测量值与(t，)模型预测值在施加脉冲序列为SV， -5V， (0 SV， -0 SV)xn， -5V和5V时的比较q -V曲线跟踪a, b， (c, dxn, 6, a值和i t s在low和maxima之后。删除先前记忆的分录2 1 I
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