Inter-poly connections are a central consideration in scaling multi-poly technologies used for memory IC fabrication. The need to simultaneously provide minimum contact resistance (R,) and low diode leakage, while maintaining isolation from surrounding poly features makes the task of scaling interpoly connections challenging. This paper discusses a newly developed WSi, polishing technology which enables scaling 3-way shared contacts (SC) down to 0.1 pm2 and below, as well as key considerations for shrinking self-aligned poly/n+ contacts (SAC). The 0.25 p SRAM triple poly technology used here is more fully described elsewhere'.
在存储器集成电路制造中，多晶间连接是扩展多晶技术的核心考虑因素。需要同时提供最小的接触电阻(R，)和低二极管泄漏，同时保持与周围聚特征的隔离，这使得缩放内插连接的任务具有挑战性。本文讨论了一种新开发的WSi抛光技术，该技术可以将3路共享触点(SC)缩放到0.1 pm2及以下，以及缩小自对齐poly/n+触点(SAC)的关键考虑因素。这里使用的0.25 p SRAM三聚技术在其他地方有更全面的描述。
{"title":"Scaling Inter-poly Contacts For 0.25 /spl mu/m And Below With WSI/sub x/ Polishing","authors":"Perera, Lii, Bajaj, Pfiester, Fengs, Thuy Dao, O'Meara, Adetutu, McGuffin, Larson, BIackwell","doi":"10.1109/VLSIT.1997.623679","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623679","url":null,"abstract":"Inter-poly connections are a central consideration in scaling multi-poly technologies used for memory IC fabrication. The need to simultaneously provide minimum contact resistance (R,) and low diode leakage, while maintaining isolation from surrounding poly features makes the task of scaling interpoly connections challenging. This paper discusses a newly developed WSi, polishing technology which enables scaling 3-way shared contacts (SC) down to 0.1 pm2 and below, as well as key considerations for shrinking self-aligned poly/n+ contacts (SAC). The 0.25 p SRAM triple poly technology used here is more fully described elsewhere'.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126703490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623726
Lee, Clemens, Keller, Manchanda
We propose a novel high K dielectric, A1203 for low voltage/ high speed flash memory without built-in charge pumps. From the analytical modeling, we have quantified the impact of high K IPD and we have verified the feasibility of 10-11 nm A1203 IPD with K-10 for msecs erasing at k3.3V. We have also developed lOnm A1203 films which show the lowest leakage current ever reported for the dielectrics with K>5 [ 131. For the first time, high K dielectric has been demonstrated for high retention f i s h technology. INTRODUCTION In the recent flash memory technologies, short prograderase times and operating voltage reductions are most important issues to realize high speed/low power operation [l-31. In order to accomplish these without a trade-off between low power and high speed operations, high coupling ratio should be achieved by increasing the floating gate capacitance[2,3]. However, decreasing the thickness of IPD to increase the floating gate capacitance may cause serious leakage and reliability problems which are fatal in the retention time of flash memories. Therefore, we focused on the application of high K IPD materials to increase the coupling ratio without cell area increase and complexity of fabrication[6]. In this paper, we present the detail quantification of the impact of IPD dielectric constant on the erasing characteristics of flash memories and A1203 IPD for msecs erasing at 3.3V. We also demonstrate the leakage current characteristics of lOnm A1203 films comparable to those of 20nm ONO and also having the excellent high temperature endurance necessary for flash memory applications [ 1,5]. SIMULATION STRUCTURE To examine the impact of high K IPD, simulations were carried out using the conventional stacked-gate flash cell shown in Fig.1. Gate widthAength was 0.8pm/0.25pm, gate oxide thickness was 5.5nm which was used for low voltage programing and reading[2]. The drain coupling ratio(CFD/COX) was 0.45 and source coupling ratio (CFS/Cox) was 0.05. Fowler-Nordheim (F-N) erasing through the drain and 2volts of threshold voltage shift were assumed. ELECTRIC FIELD ENHANCEMENT BY HIGH R IPD Fig.2 shows the electric fields across gate oxide and IPD as a function of the dielectric constant of IPD layer(K) at the onset of erasing. The gate oxide electric field tends to increase rapidly as K increases and to be saturated after that due to floating gate voltage convergency. In contrast, PPD electric field decreases initially and increases again as K increases due to the positive drain bias and the floating gate charge. This means that, by adopting proper high K IPD materials, the prograderase time can be reduced even at the scaled voltage by maintaininghcreasing the gate oxide ellectric field without poly-poly charge loss. ERASING VOLTAGE AND TIME REDUCTION Fig. 3 shows the control gate voltage reduction ratio to maintain lmsec of erasing time for two different IPD thicknesses as K varies up to 25. About 40% of voltage reduction can be achieved by
结论我们已经量化了高K IPD对低电压/高速闪存擦除特性的影响。与15nm ONO IPD(K-5)相比，具有M-10的lOnm A1203 IPD的擦除时间缩短了3个数量级，与相同厚度的sio2相比，擦除电压减少了40%，与ONO相比减少了27%。*演示了一种带有K-10的lOnm A1203用于闪光IPD。它显示出最低的泄漏电流，可与20nm的ONO相媲美，可以保证长时间保持。作者希望感谢E. J. Bower, J. D. Bude, C. Case, S. -e。陈，E. 9。拉斯科夫斯基，M. Y. Lau, C. C. - y。林，M. A.马库斯和J. R.斯威尼的支持和富有成果的讨论。希莱纽斯先生和平托先生的支持和鼓励。[17]张晓明，张晓明，张晓明，等。VLSl技术研讨会[j] .计算机工程学报，第1卷第1期。[2]李建军，李建军，李建军，等。[3]上野生等，超大规模集成电路技术研究，1996,p.54[4]高志勇等，技术研究。[5]李志强，陈志强，陈志强，等。[6]李晓明，李晓明，李晓明。电子器件，Vol. 38, No. 2，1995年第653页。1991年第270页。
{"title":"A Novel High K Inter-poly Dielectric(IPD), A1/sub 2/O/sub 3/ For Low Voltage/high Speed Flash memories: erasing in msecs at 3.3V","authors":"Lee, Clemens, Keller, Manchanda","doi":"10.1109/VLSIT.1997.623726","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623726","url":null,"abstract":"We propose a novel high K dielectric, A1203 for low voltage/ high speed flash memory without built-in charge pumps. From the analytical modeling, we have quantified the impact of high K IPD and we have verified the feasibility of 10-11 nm A1203 IPD with K-10 for msecs erasing at k3.3V. We have also developed lOnm A1203 films which show the lowest leakage current ever reported for the dielectrics with K>5 [ 131. For the first time, high K dielectric has been demonstrated for high retention f i s h technology. INTRODUCTION In the recent flash memory technologies, short prograderase times and operating voltage reductions are most important issues to realize high speed/low power operation [l-31. In order to accomplish these without a trade-off between low power and high speed operations, high coupling ratio should be achieved by increasing the floating gate capacitance[2,3]. However, decreasing the thickness of IPD to increase the floating gate capacitance may cause serious leakage and reliability problems which are fatal in the retention time of flash memories. Therefore, we focused on the application of high K IPD materials to increase the coupling ratio without cell area increase and complexity of fabrication[6]. In this paper, we present the detail quantification of the impact of IPD dielectric constant on the erasing characteristics of flash memories and A1203 IPD for msecs erasing at 3.3V. We also demonstrate the leakage current characteristics of lOnm A1203 films comparable to those of 20nm ONO and also having the excellent high temperature endurance necessary for flash memory applications [ 1,5]. SIMULATION STRUCTURE To examine the impact of high K IPD, simulations were carried out using the conventional stacked-gate flash cell shown in Fig.1. Gate widthAength was 0.8pm/0.25pm, gate oxide thickness was 5.5nm which was used for low voltage programing and reading[2]. The drain coupling ratio(CFD/COX) was 0.45 and source coupling ratio (CFS/Cox) was 0.05. Fowler-Nordheim (F-N) erasing through the drain and 2volts of threshold voltage shift were assumed. ELECTRIC FIELD ENHANCEMENT BY HIGH R IPD Fig.2 shows the electric fields across gate oxide and IPD as a function of the dielectric constant of IPD layer(K) at the onset of erasing. The gate oxide electric field tends to increase rapidly as K increases and to be saturated after that due to floating gate voltage convergency. In contrast, PPD electric field decreases initially and increases again as K increases due to the positive drain bias and the floating gate charge. This means that, by adopting proper high K IPD materials, the prograderase time can be reduced even at the scaled voltage by maintaininghcreasing the gate oxide ellectric field without poly-poly charge loss. ERASING VOLTAGE AND TIME REDUCTION Fig. 3 shows the control gate voltage reduction ratio to maintain lmsec of erasing time for two different IPD thicknesses as K varies up to 25. About 40% of voltage reduction can be achieved by","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623677
Takahashi, Tokunaga, Kasuga, Suzuki
A new model of chemical mechanical polishing (CMP) planarization is proposed. Machine time for actual calculation can be estimated less than U100 of Finite Element Method and the simulation is in excellent agreement with experimental results. This model provides a physical image of planarization for three-dimensional surface profile during CMP. Furthermore an optimized LSI chip layout or an appropriate processing condition can be estimated.
{"title":"Modeling Of Chemical Mechanical Polishing Process For Three-dimensional Simulation","authors":"Takahashi, Tokunaga, Kasuga, Suzuki","doi":"10.1109/VLSIT.1997.623677","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623677","url":null,"abstract":"A new model of chemical mechanical polishing (CMP) planarization is proposed. Machine time for actual calculation can be estimated less than U100 of Finite Element Method and the simulation is in excellent agreement with experimental results. This model provides a physical image of planarization for three-dimensional surface profile during CMP. Furthermore an optimized LSI chip layout or an appropriate processing condition can be estimated.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131795193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623733
Wei W. Lee, Qizhi He, Hanratty, Rogers, Chatterjee, Kraft, Chapman
We report fabrication of sub-0.1 pm poly-Si gates using conventional DUV lithography with an optimized Si,O,N, film. This film has dual functions: reducing substrate reflectivit to <1%, and serving as a hardmask for the pol Si etch. &ith an aggressive etch bias process, linewidtxs down to 0.06ym are achieved with good linewidth control ( 3 ~ 1 2 n m ) and a near erfect lineari . Excellent optical manufacturable PECVD deposition process. uniformity of the n a n t k of the AR z is obtained with a Introduction Advances in microlithography have enab!ed si nificant success in VLSI and ULSI technolog While suk0. lpm resist patterning awaits e-beam and %-ray lithography to become widely available, we show that existin DUV using an optimized Si,O,N ARC (anti-reflective coating) and hardmask layer. LPeVD SIN, as an ARC for patterning sub-0.5ym oly gates is reported in 11 and poly reported in [2]. However, these techni ues cannot be used nonuniform gas &strigution causes unacce table optical linewidths 2 0.12pm. DUV or anic ARC has several substrate reflectivity R) and &e infamous undercut resist reduction and etch of the relatively thick ARC layer leaves less resist available to mask the pol Si etch. In contrast, use of Si,O N, results in less resist 7;s~. Moreover, unlike organic ARE, Si,O,N has high selectivity during the polySi overetch. This hardmask roperty is critical in patterning marginal. SixO$J D%6 ARC on metal substrates was initially reported by Ogawa [3], but not used as an etch hardmask. Here we show that an o timized Si,OyN, for reflectance is more severe. Sup ression of substrate obtain sub-0.1 pm poly-Si gates with excelfent CD control. DUV ARC Film Design and Deposition The Si,OyN, refractive indices can be tuned over a wide range by varying its composition. Fig. 1 shows the real and imaginary parts of the refractive index (n and k) as the composition of Si,O N, is tuned by varying the deposition gas flow ratios. ?he Si,OyN, stack is deposited in a commercial P5000 PECVD system. A particle test on 700 wafers shows that there are <20 particles per wafer at size >0.16pm. The Si,O,N, film and backside of wafer is analyzed by TXRF and SIMS: S, C1, K, Ca, Ti, Cr, Fe, Ni, Cu A1 and Zn are at trace level or below detection limit. PECVD provides much better uniformity of n (0=0.19%) and k (0=1.4%) than LPCVD, which is important for ARC implementation. Our methodology to design the thickness and composition of the Si,O,N, ARC starts with Pr0 l i th i2~ simulations to determine the n and k needed for R ~ 1 % at various ARC thicknesses. Fig. 2 plots the simulated contour maps of R at 248nm at thicknesses of 20? 29, 40 nm. We superpose the experimental n vs. k (i.e., Fig.1) on these contours to determine whether at a particular thickness the n and k for R <1% coincide with what can be achieved with our Si,OyN, deposition process. Thus technology may be extended to achieve sub-0.lpm f eatures patterning with etch b a s and organic ARC E or i-line is
我们报告了使用优化的Si,O,N薄膜，使用传统DUV光刻技术制造低于0.1 pm的多晶硅栅极。该膜具有双重功能:将基材反射率降低至0.16pm。利用TXRF和SIMS对硅片的Si、O、N、薄膜和背面进行了分析:S、C1、K、Ca、Ti、Cr、Fe、Ni、Cu、A1和Zn均处于痕量水平或低于检测限。PECVD提供了比LPCVD更好的n(0=0.19%)和k(0=1.4%)的均匀性，这对ARC的实现很重要。我们设计Si,O,N, ARC的厚度和成分的方法从Pr0 1开始，通过2~ 2的模拟来确定在不同的ARC厚度下R ~ 1%所需的N和k。图2为R在248nm处，厚度为20?29,40 nm。我们将实验n与k(即图1)叠加在这些轮廓上，以确定在特定厚度下，n和k的R是否为20%，焦深是否为1.2ym。我们使用传统的DUV光刻技术和我们的AkC d m在超过350nm的LOCOS top0图上绘制了0.22至0.26pm的抗蚀线。实现subO。LPM栅极长度我们使用等离子蚀刻器将图案电阻降低到0 LPM以下。在此蚀刻过程中，硅、氧、氮的选择性使我们能够优化蚀刻以实现最小的电阻损失。最后，多步ARC/多晶硅刻蚀各向异性去除暴露的成本刻蚀多晶硅栅极长度。利用0.16pm的蚀刻偏压，获得了质量小于0.1 m的多晶硅线，其标准偏差较小(30=0.01美元)。图7显示了线宽减小蚀刻后低于0.1 pm的抗蚀剂轮廓。图8显示了0.06pm多晶硅线在LOCOS上的位置。最终能达到的栅极尺寸主要取决于蚀刻抗蚀剂的线宽减小。剩余抗蚀剂高度很重要，因为它控制着多晶硅线在聚蚀刻后是否完好无损。使用Si,O N，是用DUV光刻制作0.06pm多晶硅栅极的关键。我们的研究结果表明，0.08pm是最大的蚀刻偏差可能(图f)。蚀刻厚的(160nm)有机电弧，它没有很好的选择性去除抗蚀剂的顶部表面，导致8没有足够的抗蚀剂留下，以完成线宽减小蚀刻。在多晶硅复刻过程中，硅OyN的选择性进一步提高了在抗蚀剂厚度小于0的情况下(如多晶硅复刻)保持多晶硅细粒完整的能力。图9显示了LOCOS地形上多晶硅线的SEM俯视图。由于有机电弧的抗蚀性差和低的蚀刻选择性，观察到断裂的ene。在使用我们的ssi x sarc时，不会遇到这样的问题。F, g。图10所示为Si、oyna、rz和有机电弧还原刻蚀过程示意图。Si,O,N作为ARC和硬掩膜，用于制作低于0.1 pm的多晶硅栅极。结论采用设计的'&，OyN，作为DUV电弧和硬掩膜，采用线宽减小蚀刻技术，成功地在传统DUV光刻机上制备了0.06ym多晶硅栅极。在0.1 pm以下的范围内实现了极好的线性和小的标准偏差。实现Si,O, N的光刻和蚀刻工艺与有机电弧相比较。结果表明，硅的光学性能和蚀刻性能是实现良好的多晶硅线宽的关键。商用沉积设备的B - s - e使得该工艺在制造环境中实现是可行的。如图5所示。曝光纬度为0.2 s pm线为多保真度。图6总结了得到的电阻图样线宽和0.06pm范围内的硅硅栅极。我们感谢Chris Bencher的技术讨论和Trace Hurd的金属污染分析。
{"title":"Fabrication Of 0.06 /spl mu/m Poly-si Gate Using Duv Lithography With A Designed Si/sub x/O/sub y/N/sub z/ Film As An Arc And Hardmask","authors":"Wei W. Lee, Qizhi He, Hanratty, Rogers, Chatterjee, Kraft, Chapman","doi":"10.1109/VLSIT.1997.623733","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623733","url":null,"abstract":"We report fabrication of sub-0.1 pm poly-Si gates using conventional DUV lithography with an optimized Si,O,N, film. This film has dual functions: reducing substrate reflectivit to <1%, and serving as a hardmask for the pol Si etch. &ith an aggressive etch bias process, linewidtxs down to 0.06ym are achieved with good linewidth control ( 3 ~ 1 2 n m ) and a near erfect lineari . Excellent optical manufacturable PECVD deposition process. uniformity of the n a n t k of the AR z is obtained with a Introduction Advances in microlithography have enab!ed si nificant success in VLSI and ULSI technolog While suk0. lpm resist patterning awaits e-beam and %-ray lithography to become widely available, we show that existin DUV using an optimized Si,O,N ARC (anti-reflective coating) and hardmask layer. LPeVD SIN, as an ARC for patterning sub-0.5ym oly gates is reported in 11 and poly reported in [2]. However, these techni ues cannot be used nonuniform gas &strigution causes unacce table optical linewidths 2 0.12pm. DUV or anic ARC has several substrate reflectivity R) and &e infamous undercut resist reduction and etch of the relatively thick ARC layer leaves less resist available to mask the pol Si etch. In contrast, use of Si,O N, results in less resist 7;s~. Moreover, unlike organic ARE, Si,O,N has high selectivity during the polySi overetch. This hardmask roperty is critical in patterning marginal. SixO$J D%6 ARC on metal substrates was initially reported by Ogawa [3], but not used as an etch hardmask. Here we show that an o timized Si,OyN, for reflectance is more severe. Sup ression of substrate obtain sub-0.1 pm poly-Si gates with excelfent CD control. DUV ARC Film Design and Deposition The Si,OyN, refractive indices can be tuned over a wide range by varying its composition. Fig. 1 shows the real and imaginary parts of the refractive index (n and k) as the composition of Si,O N, is tuned by varying the deposition gas flow ratios. ?he Si,OyN, stack is deposited in a commercial P5000 PECVD system. A particle test on 700 wafers shows that there are <20 particles per wafer at size >0.16pm. The Si,O,N, film and backside of wafer is analyzed by TXRF and SIMS: S, C1, K, Ca, Ti, Cr, Fe, Ni, Cu A1 and Zn are at trace level or below detection limit. PECVD provides much better uniformity of n (0=0.19%) and k (0=1.4%) than LPCVD, which is important for ARC implementation. Our methodology to design the thickness and composition of the Si,O,N, ARC starts with Pr0 l i th i2~ simulations to determine the n and k needed for R ~ 1 % at various ARC thicknesses. Fig. 2 plots the simulated contour maps of R at 248nm at thicknesses of 20? 29, 40 nm. We superpose the experimental n vs. k (i.e., Fig.1) on these contours to determine whether at a particular thickness the n and k for R <1% coincide with what can be achieved with our Si,OyN, deposition process. Thus technology may be extended to achieve sub-0.lpm f eatures patterning with etch b a s and organic ARC E or i-line is ","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130989233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623703
List, Jin, Russell, Yamanaka, Olsen, Le, Ting, Havemann
Results and Discussion Xerogel exhibits several attractive features as an interlayer dielectric (ILD) film. The dielectric constant is very low (k-1.1 2.0) and can be tailored by altering the inherent porosity. The SiOz based chemical nature is appealing in that it is familiar to the IC community and represents a logical extension of existing SiOz and SOG materials with thermal stability above 500 C and a low coefficient of thermal expansion. However, integration of xerogels is thought to be ]problematic due to its porosity and poor mechanical stability. This work reports the first successful integration of xerogel dielectrics into CMP-planarized, double level metal (DLM) structures. These xerogel structures exhibited a 14% total capacitance reduction compared to comparable low-k hydrogen silsesquioxane (HSQ) gapfill structures with both better electromigration reliability and lower leakage. Both ForceFillhigh pressure A1 extrusion and W plug via processes were successfully integrated.
{"title":"Integration Of Ultra-low-k Xerogel Gapfill Dielectric For high Performance Sub-o.18 /spl mu/m Interconnects","authors":"List, Jin, Russell, Yamanaka, Olsen, Le, Ting, Havemann","doi":"10.1109/VLSIT.1997.623703","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623703","url":null,"abstract":"Results and Discussion Xerogel exhibits several attractive features as an interlayer dielectric (ILD) film. The dielectric constant is very low (k-1.1 2.0) and can be tailored by altering the inherent porosity. The SiOz based chemical nature is appealing in that it is familiar to the IC community and represents a logical extension of existing SiOz and SOG materials with thermal stability above 500 C and a low coefficient of thermal expansion. However, integration of xerogels is thought to be ]problematic due to its porosity and poor mechanical stability. This work reports the first successful integration of xerogel dielectrics into CMP-planarized, double level metal (DLM) structures. These xerogel structures exhibited a 14% total capacitance reduction compared to comparable low-k hydrogen silsesquioxane (HSQ) gapfill structures with both better electromigration reliability and lower leakage. Both ForceFillhigh pressure A1 extrusion and W plug via processes were successfully integrated.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623740
Cheung, Colonell, Chang, Lai, Liu, Pai
Stress induced leakage current (SILC) and soft breakdown (SBD) are current hot topics[l,2] in thin gate-oxide reliability. We wish to report here some new experimental observations and to propose a new model for trap assisted tunneling (TAT), SBD and Hard breakdown (HBD).
{"title":"Energy funnels - A new oxide breakdown model","authors":"Cheung, Colonell, Chang, Lai, Liu, Pai","doi":"10.1109/VLSIT.1997.623740","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623740","url":null,"abstract":"Stress induced leakage current (SILC) and soft breakdown (SBD) are current hot topics[l,2] in thin gate-oxide reliability. We wish to report here some new experimental observations and to propose a new model for trap assisted tunneling (TAT), SBD and Hard breakdown (HBD).","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"20 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623705
Ralston, Gaynor, Singh, Le, Havemann, J G Cleary, Wing, Kelly
AF4 (or parylene-F) has been integrated into double-level-metal comb capacitors as the gap-fill dielectric. The capacitance of combs with AF4 dielectric and PECVD Si02 liner displays a 10% reduction in capacitance relative to capacitors using HSQ as the dielectric, while unlined combs using AF4 display a 13.5% reduction. The leakage current of the combs using HSQ and the lined combs using AF4 is comparable, while the leakage current for the unlined combs using AF4 is at least one order of magnitude higher.
{"title":"Integration Of Thermally Stable, Low-k AF4 Polymer For 0.18 /spl mu/m Interconnects And Beyond","authors":"Ralston, Gaynor, Singh, Le, Havemann, J G Cleary, Wing, Kelly","doi":"10.1109/VLSIT.1997.623705","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623705","url":null,"abstract":"AF4 (or parylene-F) has been integrated into double-level-metal comb capacitors as the gap-fill dielectric. The capacitance of combs with AF4 dielectric and PECVD Si02 liner displays a 10% reduction in capacitance relative to capacitors using HSQ as the dielectric, while unlined combs using AF4 display a 13.5% reduction. The leakage current of the combs using HSQ and the lined combs using AF4 is comparable, while the leakage current for the unlined combs using AF4 is at least one order of magnitude higher.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623671
T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashburn, Rajni Aggarwal, Albert Shih, Xin Zhang, George Misium, A. L. Esquivel, Manoj Jain, Sudhir Madan, Terence Breedijk, Abha Singh, Gautam Thakar, Greg Shinn, Bert Riemenschneider, Sean O’Brien, David Frystak, Jorge Kittl, A. Amerasekera, Shian Aur, Paul Nicollian, David Aldrich, Bob Eklund
T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashburn, Rajni Aggarwal, Albert Shih, Xin Zhang, George Misium, A. L. Esquivel, Manoj Jain, Sudhir Madan, Terence Breedijk, Abha Singh, Gautam Thakar, Greg Shinn, Bert Riemenschneider, Sean O’Brien, David Frystak, Jorge Kittl, Ajith Amerasekera, Shian Aur, Paul Nicollian, David Aldrich, and Bob Eklund Semiconductor Process and Device Center (SPDC) Andrew Appel, Chris Bowles, and Tom Parrill Productization (PDZ) Texas Instruments Inc. Dallas, Texas, USA
T. C. Holloway、G. A. Dixit、D. T. Grider、S. P. Ashburn、Rajni Aggarwal、Albert Shih、Xin Zhang、George Misium、A. L.Esquivel, Manoj Jain, Sudhir Madan, Terence Breedijk, Abha Singh, Gautam Thakar, Greg Shinn, Bert Riemenschneider, Sean O'Brien, David Frystak, Jorge Kittl, Ajith Amerasekera, Shian Aur, Paul Nicollian, David Aldrich, and Bob Eklund Semiconductor Process and Device Center (SPDC) Andrew Appel, Chris Bowles, and Tom Parrill Productization (PDZ) Texas Instruments Inc.美国德克萨斯州达拉斯市
{"title":"0.18 /spl mu/m CMOS Technology For High-performance, Low-power, And RF Applications","authors":"T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashburn, Rajni Aggarwal, Albert Shih, Xin Zhang, George Misium, A. L. Esquivel, Manoj Jain, Sudhir Madan, Terence Breedijk, Abha Singh, Gautam Thakar, Greg Shinn, Bert Riemenschneider, Sean O’Brien, David Frystak, Jorge Kittl, A. Amerasekera, Shian Aur, Paul Nicollian, David Aldrich, Bob Eklund","doi":"10.1109/VLSIT.1997.623671","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623671","url":null,"abstract":"T. C. Holloway, G. A. Dixit, D. T. Grider, S. P. Ashburn, Rajni Aggarwal, Albert Shih, Xin Zhang, George Misium, A. L. Esquivel, Manoj Jain, Sudhir Madan, Terence Breedijk, Abha Singh, Gautam Thakar, Greg Shinn, Bert Riemenschneider, Sean O’Brien, David Frystak, Jorge Kittl, Ajith Amerasekera, Shian Aur, Paul Nicollian, David Aldrich, and Bob Eklund Semiconductor Process and Device Center (SPDC) Andrew Appel, Chris Bowles, and Tom Parrill Productization (PDZ) Texas Instruments Inc. Dallas, Texas, USA","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128841519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-10DOI: 10.1109/VLSIT.1997.623713
Subramanian, Saraswat
With increasing chip size and complexity, interconnect delays are becoming limiting factors in increasing performance. 3-D device integration will result in a reduction in chip size and interconnect delay. We present a novel technique for achieving high-performance MOS devices for vertical integration. Poly-Ge is used as a seeding agent to laterally crystallize amorphous Si films into the channel of poly-TFTs, resulting in a substantial performance improvement through a simple, CMOS-compatible process. The technology is scaleable, and should enable near-single crystal performance in deep sub-micron devices. Introduction As chip complexity and size has increased, interconnect delays have become a bottleneck limiting further improvement in chip speed. The delays associated with long interconnect lines is approaching the delays associated with individual active elements within the chip. Therefore, the need exists for a means to reduce chip size and average interconnect length through vertical integration of active devices. Unfortunately, no viable techniques exist today which allow this integration to be achieved. Techniques such as SIMOX allow SOI devices to be built on a single layer, but cannot be extended for 3-D integration. Controlled seeding in amorphous Si and subsequent lateral crystallization is a promising technique for achieving vertical integration. Crystallization occurs through nucleation and subsequent grain growth. Seeding is used to enhance nucleation in specific regions. These regions thus nucleate first and act as starting points for the lateral growth of large single-crystal islands. This controlled grain growth is the key to obtaining single-grain electronic devices. Metal-induced crystallization has been previously described (1). Unfortunately, metallic seeding agents such as Ni, are not CMOS-compatible, and therefore have questionable applicability to 3-D integration. We present a novel seeding technique which is low thermal budget, low-cost, simple, and CMOS-compatible, and is therefore extremely promising for achieving 3-D integration. Germanium is used as a seeding agent to laterally crystallize amorphous Si films. This results in large-grain polysilicon having spatially-specified grains. It is therefore possible to fabricate high-performance TFTs with excellent control over the position of grain boundaries. We present results detailing the performance of TFTs fabricated using this technique. We discuss the extension of this technique to deep sub-micron MOS devices for 3-D integration, offering near-single crystal performance. Seeding and Crystallization Methodology Ge is an excellent seeding agent for the solid-phase crystallization of amorphous Si. It can be deposited by LPCVD, and can be deposited selectively using an oxide mask over the amorphous silicon film. Poly-Ge can be deposited at low temperatures (<400°). After Ge deposition, the Si film is crystallized at low temperature to inhibit nucleation within the film.
{"title":"A Novel Technique For 3-d Integration: Ge-seeded Laterally Crystallized TFTs","authors":"Subramanian, Saraswat","doi":"10.1109/VLSIT.1997.623713","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623713","url":null,"abstract":"With increasing chip size and complexity, interconnect delays are becoming limiting factors in increasing performance. 3-D device integration will result in a reduction in chip size and interconnect delay. We present a novel technique for achieving high-performance MOS devices for vertical integration. Poly-Ge is used as a seeding agent to laterally crystallize amorphous Si films into the channel of poly-TFTs, resulting in a substantial performance improvement through a simple, CMOS-compatible process. The technology is scaleable, and should enable near-single crystal performance in deep sub-micron devices. Introduction As chip complexity and size has increased, interconnect delays have become a bottleneck limiting further improvement in chip speed. The delays associated with long interconnect lines is approaching the delays associated with individual active elements within the chip. Therefore, the need exists for a means to reduce chip size and average interconnect length through vertical integration of active devices. Unfortunately, no viable techniques exist today which allow this integration to be achieved. Techniques such as SIMOX allow SOI devices to be built on a single layer, but cannot be extended for 3-D integration. Controlled seeding in amorphous Si and subsequent lateral crystallization is a promising technique for achieving vertical integration. Crystallization occurs through nucleation and subsequent grain growth. Seeding is used to enhance nucleation in specific regions. These regions thus nucleate first and act as starting points for the lateral growth of large single-crystal islands. This controlled grain growth is the key to obtaining single-grain electronic devices. Metal-induced crystallization has been previously described (1). Unfortunately, metallic seeding agents such as Ni, are not CMOS-compatible, and therefore have questionable applicability to 3-D integration. We present a novel seeding technique which is low thermal budget, low-cost, simple, and CMOS-compatible, and is therefore extremely promising for achieving 3-D integration. Germanium is used as a seeding agent to laterally crystallize amorphous Si films. This results in large-grain polysilicon having spatially-specified grains. It is therefore possible to fabricate high-performance TFTs with excellent control over the position of grain boundaries. We present results detailing the performance of TFTs fabricated using this technique. We discuss the extension of this technique to deep sub-micron MOS devices for 3-D integration, offering near-single crystal performance. Seeding and Crystallization Methodology Ge is an excellent seeding agent for the solid-phase crystallization of amorphous Si. It can be deposited by LPCVD, and can be deposited selectively using an oxide mask over the amorphous silicon film. Poly-Ge can be deposited at low temperatures (<400°). After Ge deposition, the Si film is crystallized at low temperature to inhibit nucleation within the film. ","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127701666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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