Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863210
Fuyuan Zhao, W. Deng, Rui Wu, Haikun Jia, Qixiu Wu, Jihao Xin, Zhiyuan Zeng, Yanlei Li, Zhihua Wang, B. Chi
This paper introduces a Ka-band 4-channel dual-stream phased-array joint radar-communication transceiver for the future radar-communication integrated wireless system. In order to enhance the signal to noise and distortion ratio in low input signal region and reduce the chip area, a current-flopping bi-directional active mixer is proposed. A variable-transmission-line-based phase shifter with tilting structure is introduced to achieve wide-band phase shifting and mitigate the in-band loss fluctuation. The proposed transceiver is designed and implemented in a 65nm CMOS technology. The chip area is 16.2 mm2. The measured TX peak saturated output power is 19.9 dBm and the output 1 dB compression point is 17.4 dBm. The measured RX minimum noise figure is 4.8 dB. System measurement results indicates that the proposed transceiver supports real-time centimeter-level 2D imaging and 400-Msym/s 64-QAM over-the-air (OTA) wireless link.
{"title":"A 29-to-36 GHz 4TX/4RX Dual-stream Phased-array Joint Radar-Communication CMOS Transceiver Supporting Centimeter-level 2D Imaging and 64-QAM OTA Wireless Link","authors":"Fuyuan Zhao, W. Deng, Rui Wu, Haikun Jia, Qixiu Wu, Jihao Xin, Zhiyuan Zeng, Yanlei Li, Zhihua Wang, B. Chi","doi":"10.1109/RFIC54546.2022.9863210","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863210","url":null,"abstract":"This paper introduces a Ka-band 4-channel dual-stream phased-array joint radar-communication transceiver for the future radar-communication integrated wireless system. In order to enhance the signal to noise and distortion ratio in low input signal region and reduce the chip area, a current-flopping bi-directional active mixer is proposed. A variable-transmission-line-based phase shifter with tilting structure is introduced to achieve wide-band phase shifting and mitigate the in-band loss fluctuation. The proposed transceiver is designed and implemented in a 65nm CMOS technology. The chip area is 16.2 mm2. The measured TX peak saturated output power is 19.9 dBm and the output 1 dB compression point is 17.4 dBm. The measured RX minimum noise figure is 4.8 dB. System measurement results indicates that the proposed transceiver supports real-time centimeter-level 2D imaging and 400-Msym/s 64-QAM over-the-air (OTA) wireless link.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114606929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9862953
Huajun Chen, Zhenqi Chen, Rongde Ou, Run Chen, Zhaohui Wu, Bin Li
This paper presents an IEEE 802.15.4z standard-compliant UWB digital transmitter that features reconfigurable pulse-shaping. The proposed UWB pulse-shaping technique exploits programmable delay lines to achieve high spectrum efficiency and significant sidelobe suppression. An on-chip broadband matching network with a second-harmonic trap is implemented to protect the digital power amplifier (DPA) realized by thin-gate transistors. Implemented in a 28nm CMOS process with a supply voltage of 0.9V, the prototype chip can operate from 4 to 9 GHz at various pulse repetition rates (PRF) from 1 to 249.6 MHz with programmable signal bandwidths (500 ∼ 1331 MHz). The measured transmitted waveform meets with IEEE 802.15.4z standard, and its spectrum efficiency is up to 59%. The output power is highly programmable with a peak value of 14.5 dBm.
{"title":"A 4-to-9GHz IEEE 802.15.4z-Compliant UWB Digital Transmitter with Reconfigurable Pulse-Shaping in 28nm CMOS","authors":"Huajun Chen, Zhenqi Chen, Rongde Ou, Run Chen, Zhaohui Wu, Bin Li","doi":"10.1109/RFIC54546.2022.9862953","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9862953","url":null,"abstract":"This paper presents an IEEE 802.15.4z standard-compliant UWB digital transmitter that features reconfigurable pulse-shaping. The proposed UWB pulse-shaping technique exploits programmable delay lines to achieve high spectrum efficiency and significant sidelobe suppression. An on-chip broadband matching network with a second-harmonic trap is implemented to protect the digital power amplifier (DPA) realized by thin-gate transistors. Implemented in a 28nm CMOS process with a supply voltage of 0.9V, the prototype chip can operate from 4 to 9 GHz at various pulse repetition rates (PRF) from 1 to 249.6 MHz with programmable signal bandwidths (500 ∼ 1331 MHz). The measured transmitted waveform meets with IEEE 802.15.4z standard, and its spectrum efficiency is up to 59%. The output power is highly programmable with a peak value of 14.5 dBm.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130624453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863208
Bill Y. Lin, H. Mani, Phil Marsh, R. Hadi, Hua Wang
This paper presents a compact broadband cryogenic low noise amplifier (LNA) with simultaneous noise and power matching with transformer-based feedback. The LNA is composed of an input impedance transforming network and three-stage amplifiers to achieve simultaneous broadband low-noise and power matching. The first stage is a cascode amplifier with a drain source-coupled transformer. The second stage is a current-reuse broadband amplifier, and the third stage is an inductive-peaking cascode common-source amplifier. The LNA is packaged in a custom chassis and measured at 300K and 16K. At 300K probing measurement, the LNA achieves minimum noise Fig. of 1.42dB and S11< -10dB from 3.6-8.2 GHz with 34dB-35.9dB gain. The overall group delay is less than 0.3ns and IIP3 is ≥ -6dBm across the frequency range. At 16K, the LNA achieves a minimum noise Fig. (NF) of 0.065dB and NF < 0.3dB from 4.2-9.2 GHz with 31.4dB-34.7dB gain.
{"title":"A 4.2-9.2GHz Cryogenic Transformer Feedback Low Noise Amplifier with 4.5K Noise Temperature and Noise-Power Matching in 22nm CMOS FDSOI","authors":"Bill Y. Lin, H. Mani, Phil Marsh, R. Hadi, Hua Wang","doi":"10.1109/RFIC54546.2022.9863208","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863208","url":null,"abstract":"This paper presents a compact broadband cryogenic low noise amplifier (LNA) with simultaneous noise and power matching with transformer-based feedback. The LNA is composed of an input impedance transforming network and three-stage amplifiers to achieve simultaneous broadband low-noise and power matching. The first stage is a cascode amplifier with a drain source-coupled transformer. The second stage is a current-reuse broadband amplifier, and the third stage is an inductive-peaking cascode common-source amplifier. The LNA is packaged in a custom chassis and measured at 300K and 16K. At 300K probing measurement, the LNA achieves minimum noise Fig. of 1.42dB and S11< -10dB from 3.6-8.2 GHz with 34dB-35.9dB gain. The overall group delay is less than 0.3ns and IIP3 is ≥ -6dBm across the frequency range. At 16K, the LNA achieves a minimum noise Fig. (NF) of 0.065dB and NF < 0.3dB from 4.2-9.2 GHz with 31.4dB-34.7dB gain.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"109 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/lmsa.2009.5074849
D. Landuyt, E. Truyen, W. Joosen
{"title":"Detailed author index","authors":"D. Landuyt, E. Truyen, W. Joosen","doi":"10.1109/lmsa.2009.5074849","DOIUrl":"https://doi.org/10.1109/lmsa.2009.5074849","url":null,"abstract":"","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863102
Seung-Uk Choi, Kyunghwan Kim, Kangseop Lee, Seunghoon Lee, Ho-Jin Song
A novel built-in self-test (BIST) circuit is presented. The proposed BIST enables the testing of active antenna impedance and the VSWR resilient channel response. The technique is achieved simply by extracting the complex voltages at two nodes on a short-distance transmission line. For efficient implementation, a single-pole double-throw RF switch is used for sharing the signal detector, and the required switch on-off ratio is analyzed mathematically based on detection accuracy. The proposed BIST was experimentally verified with a test chip fabricated with a 40-nm bulk CMOS process. The measured magnitude and phase rms errors for the complex forward waves are less than 1.1dB and 2.5°, respectively, within 82-86GHz. In the impedance estimation test, $Gamma$ magnitude and phase rms errors are less than 0.1 and 17°, respectively, within 76-86GHz.
{"title":"E-band CMOS Built-in Self-Test Circuit Capable of Testing Active Antenna Impedance and Complex Channel Response","authors":"Seung-Uk Choi, Kyunghwan Kim, Kangseop Lee, Seunghoon Lee, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9863102","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863102","url":null,"abstract":"A novel built-in self-test (BIST) circuit is presented. The proposed BIST enables the testing of active antenna impedance and the VSWR resilient channel response. The technique is achieved simply by extracting the complex voltages at two nodes on a short-distance transmission line. For efficient implementation, a single-pole double-throw RF switch is used for sharing the signal detector, and the required switch on-off ratio is analyzed mathematically based on detection accuracy. The proposed BIST was experimentally verified with a test chip fabricated with a 40-nm bulk CMOS process. The measured magnitude and phase rms errors for the complex forward waves are less than 1.1dB and 2.5°, respectively, within 82-86GHz. In the impedance estimation test, $Gamma$ magnitude and phase rms errors are less than 0.1 and 17°, respectively, within 76-86GHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133942677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863119
Xiaohan Zhang, Sensen Li, Daquan Huang, T. Chi
We propose a mmWave three-way Doherty output network synthesis methodology that can realize close-to-ideal dual-peaking Doherty active load modulation while absorbing the device parasitic capacitance. Following this methodology, we present a 38GHz PA prototype, achieving 13.7% / 11.0% PAE at 9.5dB / 11.5dB back-off, which are the highest among reported silicon PAs operating at 30GHz and above. Tested under 1-CC and 2-CC 5G NR FR2 64-QAM OFDM signals in the Band n260, the PA demonstrates state-of-the-art average output power (11.3dBm) and average efficiency (14.7%).
我们提出了一种毫米波三向Doherty输出网络合成方法，该方法可以在吸收器件寄生电容的同时实现接近理想的双峰Doherty有源负载调制。根据这种方法，我们提出了一个38GHz的PA原型，在9.5dB / 11.5dB的回退下实现了13.7% / 11.0%的PAE，这是在30GHz及以上工作的硅PA中最高的。在n260频段的1-CC和2-CC 5G NR FR2 64-QAM OFDM信号下进行测试，PA显示出最先进的平均输出功率(11.3dBm)和平均效率(14.7%)。
{"title":"A 38GHz Deep Back-Off Efficiency Enhancement PA with Three-Way Doherty Network Synthesis Achieving 11.3dBm Average Output Power and 14.7% Average Efficiency for 5G NR OFDM","authors":"Xiaohan Zhang, Sensen Li, Daquan Huang, T. Chi","doi":"10.1109/RFIC54546.2022.9863119","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863119","url":null,"abstract":"We propose a mmWave three-way Doherty output network synthesis methodology that can realize close-to-ideal dual-peaking Doherty active load modulation while absorbing the device parasitic capacitance. Following this methodology, we present a 38GHz PA prototype, achieving 13.7% / 11.0% PAE at 9.5dB / 11.5dB back-off, which are the highest among reported silicon PAs operating at 30GHz and above. Tested under 1-CC and 2-CC 5G NR FR2 64-QAM OFDM signals in the Band n260, the PA demonstrates state-of-the-art average output power (11.3dBm) and average efficiency (14.7%).","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863125
S. Myoung, Jonghoon Park, Chang Hun Song, Ryun Woo Kim, Jaeyoung Ryu, Jeongki Choi, Hoai-Nam Nguyen, Seungyun Lee, Ilyong Jung, J. Lim, Sok Kyu Lee
A novel 802.11ah transmitter for TV white space (TVWS) band devices is presented. To realize the transmitter meeting the stringent FCC and ETSI TVWS device emission limits for the adjacent channels and FCC restricted bands, a low noise and high linear class- AB voltage- to-current converter (V2I) as the mixer driver and a 2nd -order harmonic notch filter with the frequency tracking capability on the power amplifier (PA) load are newly proposed. The designed transmitter is implemented in a 40nm CMOS process as a part of the TVWS band 802.11ah connectivity System-on-Chip (SoC), and the measured results with the 802.11ah CBW4 signal show −55dBr and −58dBr Adjacent Channel Leakage Ratio (ACLR) at $pm 3mathbf{MHz}$ and $pm 20mathbf{MHz}$ frequency offset, respectively, and 60dB 2nd harmonic rejection for 470MHz ~ 790MHz TVWS bands. This transmitter is the first SoC level transmitter meeting the FCC and ETSI ACLR requirements.
{"title":"802.11ah Transmitter with −55dBr at $pm 3text{MHz}$ and −58dBr at $pm 20text{MHz}$ ACLR and 60dB 2nd-order Harmonic Rejection for 470MHz ~ 790MHz TV White Space Band Devices","authors":"S. Myoung, Jonghoon Park, Chang Hun Song, Ryun Woo Kim, Jaeyoung Ryu, Jeongki Choi, Hoai-Nam Nguyen, Seungyun Lee, Ilyong Jung, J. Lim, Sok Kyu Lee","doi":"10.1109/RFIC54546.2022.9863125","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863125","url":null,"abstract":"A novel 802.11ah transmitter for TV white space (TVWS) band devices is presented. To realize the transmitter meeting the stringent FCC and ETSI TVWS device emission limits for the adjacent channels and FCC restricted bands, a low noise and high linear class- AB voltage- to-current converter (V2I) as the mixer driver and a 2nd -order harmonic notch filter with the frequency tracking capability on the power amplifier (PA) load are newly proposed. The designed transmitter is implemented in a 40nm CMOS process as a part of the TVWS band 802.11ah connectivity System-on-Chip (SoC), and the measured results with the 802.11ah CBW4 signal show −55dBr and −58dBr Adjacent Channel Leakage Ratio (ACLR) at $pm 3mathbf{MHz}$ and $pm 20mathbf{MHz}$ frequency offset, respectively, and 60dB 2nd harmonic rejection for 470MHz ~ 790MHz TVWS bands. This transmitter is the first SoC level transmitter meeting the FCC and ETSI ACLR requirements.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133461520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863158
J. Plouchart, Dereje Yilma, John Timmerwilke, S. Chakraborty, K. Tien, A. Valdes-Garcia, D. Friedman
A 5.9-8.4GHz LNA intended for use at cryogenic temperatures was implemented in a 14nm FinFET CMOS technology. At 4.1 K, peak LNA gain of 13.4dB is measured at 7.1GHz, with a 3dB bandwidth of 2.5GHz and power consumption of 2.1mW. Also, at 4.1K, measured noise figure from 6 to 8GHz is 0.53-0.57dB and the measured noise temperature is 37.6-41K; power consumption in this set of measurements was 2.57mW.
{"title":"A 2.57mW 5.9-8.4GHz Cryogenic FinFET LNA for Qubit Readout","authors":"J. Plouchart, Dereje Yilma, John Timmerwilke, S. Chakraborty, K. Tien, A. Valdes-Garcia, D. Friedman","doi":"10.1109/RFIC54546.2022.9863158","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863158","url":null,"abstract":"A 5.9-8.4GHz LNA intended for use at cryogenic temperatures was implemented in a 14nm FinFET CMOS technology. At 4.1 K, peak LNA gain of 13.4dB is measured at 7.1GHz, with a 3dB bandwidth of 2.5GHz and power consumption of 2.1mW. Also, at 4.1K, measured noise figure from 6 to 8GHz is 0.53-0.57dB and the measured noise temperature is 37.6-41K; power consumption in this set of measurements was 2.57mW.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116647881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863148
Dongwon You, Yun Wang, Xi Fu, Hans Herdian, Xiaolin Wang, A. Fadila, Hojun Lee, Michihiro Ide, Sena Kato, Zheng Li, Jian Pang, A. Shirane, K. Okada
An adaptive scan impedance tuner for varying impedance of array antenna along with the beam scan and calibration circuits for deteriorated cross-polarization are proposed for the low earth orbit (LEO) satellite terminal for earth observation application. With the proposed load tuner, TX power efficiency is improved to 11.7 % from 6.5 % at a VSWR=1:3 load condition where the same load point as the 50° scan angle. Furthermore, 18.1 dB and 16.4 dB of the cross-polarization discrimination (XPD) is recovered for the right-handed circular polarization (RHPC) and left-handed circular polarization (LHPC), respectively, by the proposed circular polarization calibration circuit with the modulated signal. Accordingly, the error vector magnitudes (EVM) are also improved by 12.2 dB and 14.8dB at the RHCP and the LHCP, respectively. To the best of the authors' knowledge, the proposed TX is the first reported work with the dual circular polarization transmitting mode measurement results in Ka-band for satellites.
{"title":"A Ka- Band Dual Circularly Polarized CMOS Transmitter with Adaptive Scan Impedance Tuner and Active XPD Calibration Technique for Satellite Terminal","authors":"Dongwon You, Yun Wang, Xi Fu, Hans Herdian, Xiaolin Wang, A. Fadila, Hojun Lee, Michihiro Ide, Sena Kato, Zheng Li, Jian Pang, A. Shirane, K. Okada","doi":"10.1109/RFIC54546.2022.9863148","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863148","url":null,"abstract":"An adaptive scan impedance tuner for varying impedance of array antenna along with the beam scan and calibration circuits for deteriorated cross-polarization are proposed for the low earth orbit (LEO) satellite terminal for earth observation application. With the proposed load tuner, TX power efficiency is improved to 11.7 % from 6.5 % at a VSWR=1:3 load condition where the same load point as the 50° scan angle. Furthermore, 18.1 dB and 16.4 dB of the cross-polarization discrimination (XPD) is recovered for the right-handed circular polarization (RHPC) and left-handed circular polarization (LHPC), respectively, by the proposed circular polarization calibration circuit with the modulated signal. Accordingly, the error vector magnitudes (EVM) are also improved by 12.2 dB and 14.8dB at the RHCP and the LHCP, respectively. To the best of the authors' knowledge, the proposed TX is the first reported work with the dual circular polarization transmitting mode measurement results in Ka-band for satellites.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121890720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863076
S. Venkatesh, H. Saeidi, Xuyang Lu, K. Sengupta
Millimeter-wave wireless networks allow for spatial multiplexing and high throughput. However, they are critically susceptible to blockages, channel propagation variations, and fading. To incorporate resilience in such networks, a class of reconfigurable surfaces realized with reflect-arrays have shown theoretical promise in reconfiguring the channel on demand, creating programmable non-line-of-sight (NLOS) paths, and providing a scalable solution compared to densification of base stations and access points. In this paper, we present a scalable approach towards realizing active surfaces with the ability to simultaneously receive, amplify, beamform, and re-transmit to the intended receiver (Rx) in a secure fashion. We demonstrate with the proof-of-concept 2D and 1D arrays realized with custom silicon ICs in a 65-nm CMOS process while the reception and re-transmission is achieved through off-chip packaged dual-feed probe-fed patch antenna. Each chip incorporates two independent transceiver (TxRx) chains, with two-stage LNA and a 5-bit controlled 360° IQ phase shifter, collectively providing controllable gain of up to 15.2dB, Psat of 4.2dBm at 60GHz, noise figure ≈ 5–6dB, and supporting up to 20Gbps with 32-QAM constellation. With packaged 1D and 2D arrays, we demonstrate ±45° beamforming capability for various Tx positions closing links where simple reflective surfaces tend to fail. In addition, with spatio-temporal control over the surface, we also demonstrate physical layer security.
{"title":"Active Tunable Millimeter-wave Reflective Surface across 57-64 GHz for Blockage Mitigation and Physical Layer Security","authors":"S. Venkatesh, H. Saeidi, Xuyang Lu, K. Sengupta","doi":"10.1109/RFIC54546.2022.9863076","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863076","url":null,"abstract":"Millimeter-wave wireless networks allow for spatial multiplexing and high throughput. However, they are critically susceptible to blockages, channel propagation variations, and fading. To incorporate resilience in such networks, a class of reconfigurable surfaces realized with reflect-arrays have shown theoretical promise in reconfiguring the channel on demand, creating programmable non-line-of-sight (NLOS) paths, and providing a scalable solution compared to densification of base stations and access points. In this paper, we present a scalable approach towards realizing active surfaces with the ability to simultaneously receive, amplify, beamform, and re-transmit to the intended receiver (Rx) in a secure fashion. We demonstrate with the proof-of-concept 2D and 1D arrays realized with custom silicon ICs in a 65-nm CMOS process while the reception and re-transmission is achieved through off-chip packaged dual-feed probe-fed patch antenna. Each chip incorporates two independent transceiver (TxRx) chains, with two-stage LNA and a 5-bit controlled 360° IQ phase shifter, collectively providing controllable gain of up to 15.2dB, Psat of 4.2dBm at 60GHz, noise figure ≈ 5–6dB, and supporting up to 20Gbps with 32-QAM constellation. With packaged 1D and 2D arrays, we demonstrate ±45° beamforming capability for various Tx positions closing links where simple reflective surfaces tend to fail. In addition, with spatio-temporal control over the surface, we also demonstrate physical layer security.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126165856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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