Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863190
Kyumin Kwon, Omar Abdelatty, D. Wentzloff
In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.
{"title":"Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology","authors":"Kyumin Kwon, Omar Abdelatty, D. Wentzloff","doi":"10.1109/RFIC54546.2022.9863190","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863190","url":null,"abstract":"In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863099
J. Hwang, Byung-Wook Min
In this paper, a non-magnetic circulator, which realizes non-reciprocal signal flows by sequentially switching delay lines, is presented in 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The proposed circulator is designed differentially to increase power handling capability and bandwidth. The bandwidth of insertion loss and isolation can be extended by latticely coupled inductors used in the differential synthetic delay lines. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor. The measured insertion losses of transmitter (TX) to antenna (ANT) and ANT to receiver (RX) are 2.5 dB and 2.6 dB, respectively. TX to RX isolation is $> 20 text{dB}$ up to 7 GHz. The measured TX input power 1 dB compression point is 4.7 dBm at 3.5 GHz. The chip size of the differential circulator is $1.33times 0.72 text{mm}^{2}$, which is as small as a single ended version, thanks to the coupled inductors.
{"title":"Fully Integrated Ultra-Wideband Differential Circulator Based on Sequentially Switched Delay Line in 28-nm FDSOI CMOS","authors":"J. Hwang, Byung-Wook Min","doi":"10.1109/RFIC54546.2022.9863099","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863099","url":null,"abstract":"In this paper, a non-magnetic circulator, which realizes non-reciprocal signal flows by sequentially switching delay lines, is presented in 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The proposed circulator is designed differentially to increase power handling capability and bandwidth. The bandwidth of insertion loss and isolation can be extended by latticely coupled inductors used in the differential synthetic delay lines. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor. The measured insertion losses of transmitter (TX) to antenna (ANT) and ANT to receiver (RX) are 2.5 dB and 2.6 dB, respectively. TX to RX isolation is $> 20 text{dB}$ up to 7 GHz. The measured TX input power 1 dB compression point is 4.7 dBm at 3.5 GHz. The chip size of the differential circulator is $1.33times 0.72 text{mm}^{2}$, which is as small as a single ended version, thanks to the coupled inductors.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128803206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863191
Robin Garg, Paul Dania, Gaurav Sharma, Armagan Dascurcu, Soumya Gupta, H. Krishnaswamy, A. Natarajan
Dense-aperture mm-wave MIMO RX front-ends will require simplified IF interfaces, particularly when multiple 5G NR bands must be supported. The first dual-band 28 GHz and 39 GHz MIMO RX front-end with beam-space frequency-domain multiplexing (FDM) is presented that enables concurrent amplitude/phase weighted signal combining across four elements and 28 GHz/39 GHz bands. The FDM scheme places the four beam-space outputs at four different IF frequencies. The IC includes local multi-phase LO generation in each element, consumes 516mW (32.3mW/beam/element) and occupies 14mm2 in 65-nm CMOS.
密集孔径毫米波MIMO RX前端将需要简化中频接口，特别是在必须支持多个5G NR频段的情况下。提出了首个采用波束空间频域复用(FDM)的双频28ghz和39ghz MIMO RX前端，实现了跨4个单元和28ghz / 39ghz频段的幅度/相位加权信号合并。FDM方案将四个波束空间输出置于四个不同的中频频率。该IC在每个元件中包含本地多相LO生成，功耗为516mW (32.3mW/波束/元件)，在65nm CMOS中占地14mm2。
{"title":"A 28 GHz/39 GHz Dual-Band Four-Element MIMO RX with Beamspace Multiplexing at IF in 65-nm CMOS","authors":"Robin Garg, Paul Dania, Gaurav Sharma, Armagan Dascurcu, Soumya Gupta, H. Krishnaswamy, A. Natarajan","doi":"10.1109/RFIC54546.2022.9863191","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863191","url":null,"abstract":"Dense-aperture mm-wave MIMO RX front-ends will require simplified IF interfaces, particularly when multiple 5G NR bands must be supported. The first dual-band 28 GHz and 39 GHz MIMO RX front-end with beam-space frequency-domain multiplexing (FDM) is presented that enables concurrent amplitude/phase weighted signal combining across four elements and 28 GHz/39 GHz bands. The FDM scheme places the four beam-space outputs at four different IF frequencies. The IC includes local multi-phase LO generation in each element, consumes 516mW (32.3mW/beam/element) and occupies 14mm2 in 65-nm CMOS.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128573666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863185
Wen Zhou, Y. Tousi
This paper presents a bi-static integrated pulse radar in the E-band based on a digitally modulated transmitter and an analog processing receiver module. The proposed frontend correlator operates at 1Gbps and uses a 1.5-bit sampler to compress the sensing data, enabling a low-speed and energy-efficient digital backend while delivering a high range resolution. The TSMC 65nm chip prototype has a 1.5mm x 1.3mm area and consumes a total of 407mW with only 38mW corresponding to the analog baseband and digital backend. Over-the-air measurements at the 66GHz carrier frequency indicate the measured distance from the correlator output has an RMS error of 11.6cm and the integral non-linearity is less than 10cm across the entire target range, demonstrating the state-of-the-art range resolution with superior energy efficiency.
本文提出了一种基于数字调制发射机和模拟处理接收机模块的e波段双基地集成脉冲雷达。所提出的前端相关器工作速度为1Gbps，使用1.5位采样器压缩传感数据，在提供高范围分辨率的同时实现低速节能的数字后端。台积电65nm芯片原型的面积为1.5mm x 1.3mm，总功耗为407mW，其中模拟基带和数字后端仅对应38mW。在66GHz载波频率下的空中测量表明，在整个目标范围内，与相关器输出的测量距离的RMS误差为11.6cm，积分非线性小于10cm，展示了最先进的距离分辨率和卓越的能源效率。
{"title":"An E-Band Phase Modulated Pulse Radar SoC with An Analog Correlator","authors":"Wen Zhou, Y. Tousi","doi":"10.1109/RFIC54546.2022.9863185","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863185","url":null,"abstract":"This paper presents a bi-static integrated pulse radar in the E-band based on a digitally modulated transmitter and an analog processing receiver module. The proposed frontend correlator operates at 1Gbps and uses a 1.5-bit sampler to compress the sensing data, enabling a low-speed and energy-efficient digital backend while delivering a high range resolution. The TSMC 65nm chip prototype has a 1.5mm x 1.3mm area and consumes a total of 407mW with only 38mW corresponding to the analog baseband and digital backend. Over-the-air measurements at the 66GHz carrier frequency indicate the measured distance from the correlator output has an RMS error of 11.6cm and the integral non-linearity is less than 10cm across the entire target range, demonstrating the state-of-the-art range resolution with superior energy efficiency.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128643897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863124
Shuyang Li, Wen-hua Chen, Xingcun Li, Yunfan Wang
This paper presents a D-band frequency sextupler in 22 nm FD-SOI CMOS. It consists of a differential frequency tripler followed by a push-push frequency doubler for six times frequency multiplication, and several differential amplifiers for enhanced conversion gain and output power. A broadband balance-compensation method is proposed for transformer-based baluns to realize wideband conversion between single-ended and balanced signals. The measured peak output power and peak efficiency are 5.1 dBm and 8.49% at 145.5 GHz, respectively. The fabricated frequency sextupler features a 3-dB output power bandwidth from 127 to 162 GHz and low DC power consumption less than 50 m W from 0.8 V power supply.
本文提出了一种22 nm FD-SOI CMOS的d波段频率六倍器。它包括一个差分三倍频器，然后是一个推推式倍频器，用于六倍频乘法，以及几个差分放大器，用于增强转换增益和输出功率。提出了一种基于变压器的平衡器宽带平衡补偿方法，实现了单端与平衡信号之间的宽带转换。在145.5 GHz频段测量到的峰值输出功率和峰值效率分别为5.1 dBm和8.49%。制作的频率六倍器具有从127到162 GHz的3db输出功率带宽和0.8 V电源下低于50 m W的低直流功耗。
{"title":"A 5.1 dBm 127–162 GHz Frequency Sextupler with Broadband Compensated Transformer-Based Baluns in 22nm FD-SOI CMOS","authors":"Shuyang Li, Wen-hua Chen, Xingcun Li, Yunfan Wang","doi":"10.1109/RFIC54546.2022.9863124","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863124","url":null,"abstract":"This paper presents a D-band frequency sextupler in 22 nm FD-SOI CMOS. It consists of a differential frequency tripler followed by a push-push frequency doubler for six times frequency multiplication, and several differential amplifiers for enhanced conversion gain and output power. A broadband balance-compensation method is proposed for transformer-based baluns to realize wideband conversion between single-ended and balanced signals. The measured peak output power and peak efficiency are 5.1 dBm and 8.49% at 145.5 GHz, respectively. The fabricated frequency sextupler features a 3-dB output power bandwidth from 127 to 162 GHz and low DC power consumption less than 50 m W from 0.8 V power supply.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863207
S. Akhtar, G. Schuppener, T. Dinc, B. Haroun, S. Sankaran
An active balun using dual stage feedback and distributed feedforward distortion cancellation for use as a driver amplifier for wideband RF sampling ADCs is presented. With a gain of 16.5dB & HD2 of 60dBc while delivering 3dBm (100Ω), the DC coupled balun achieves a linear-bandwidth of >12GHz holding OIP3>27dBm & NF<8dB, and small-signal bandwidth of 18GHz with <±0.5dB amplitude & <±2.5° phase imbalance. Cascaded balun + ADC measurements demonstrate no linearity limitation, while allowing for 19.5dB lower input signal. Occupying 1mm2in a 130nm BiCMOS process, the device consumes 100mA from 5V in a 2×2mm2 flip chip QFN package.
{"title":"DC to 12+GHz, +30dBm OIP3, 7.2dB Noise Figure Active Balun in 130nm BiCMOS for RF Sampling Multi-Gbps Data Converters","authors":"S. Akhtar, G. Schuppener, T. Dinc, B. Haroun, S. Sankaran","doi":"10.1109/RFIC54546.2022.9863207","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863207","url":null,"abstract":"An active balun using dual stage feedback and distributed feedforward distortion cancellation for use as a driver amplifier for wideband RF sampling ADCs is presented. With a gain of 16.5dB & HD2 of 60dBc while delivering 3dBm (100Ω), the DC coupled balun achieves a linear-bandwidth of >12GHz holding OIP3>27dBm & NF<8dB, and small-signal bandwidth of 18GHz with <±0.5dB amplitude & <±2.5° phase imbalance. Cascaded balun + ADC measurements demonstrate no linearity limitation, while allowing for 19.5dB lower input signal. Occupying 1mm2in a 130nm BiCMOS process, the device consumes 100mA from 5V in a 2×2mm2 flip chip QFN package.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863137
Kaisarbek Omirzakhov, M. H. Idjadi, Tzu-Yung Huang, S. Breitweiser, David A. Hopper, L. Bassett, F. Aflatouni
Solid-state electron spins are key building blocks for emerging applications in quantum information science, including quantum computers, quantum communication links, and quantum sensors. However, solid-state spins are controlled using complex microwave pulse sequences, which are typically generated using benchtop electrical instruments. Integration of the required electronics will enable realization of a scalable low-power and compact optically addressable quantum system. Here, we report an integrated reconfigurable quantum control system, which is used to perform Rabi and Ramsey oscillation measurements for an NV center in diamond. The 180nm CMOS chip, fabricated within a footprint of 3.02mm2, consumes 80 mW of power, and is capable of generating a tunable microwave signal from 1.6 GHz to 2.6 GHz modulated with a sequence of up to 4098 reconfigurable pulses with a pulse width adjustable from 10ns to 42ms and a pulse-to-pulse delay adjustable between 18 ns to 42m, at a resolution of 2.5 ns.
{"title":"An Integrated Quantum Spin Control System in 180nm CMOS","authors":"Kaisarbek Omirzakhov, M. H. Idjadi, Tzu-Yung Huang, S. Breitweiser, David A. Hopper, L. Bassett, F. Aflatouni","doi":"10.1109/RFIC54546.2022.9863137","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863137","url":null,"abstract":"Solid-state electron spins are key building blocks for emerging applications in quantum information science, including quantum computers, quantum communication links, and quantum sensors. However, solid-state spins are controlled using complex microwave pulse sequences, which are typically generated using benchtop electrical instruments. Integration of the required electronics will enable realization of a scalable low-power and compact optically addressable quantum system. Here, we report an integrated reconfigurable quantum control system, which is used to perform Rabi and Ramsey oscillation measurements for an NV center in diamond. The 180nm CMOS chip, fabricated within a footprint of 3.02mm2, consumes 80 mW of power, and is capable of generating a tunable microwave signal from 1.6 GHz to 2.6 GHz modulated with a sequence of up to 4098 reconfigurable pulses with a pulse width adjustable from 10ns to 42ms and a pulse-to-pulse delay adjustable between 18 ns to 42m, at a resolution of 2.5 ns.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863181
Renzhi Liu, Beevi K. T. Asma, R. Dorrance, T. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, B. Carlton
This paper presents a sub-10GHz wireless transceiver for short-range multicast applications in a reconfigurable FDD wireless network. The transceiver adopts a digital-process-friendly architecture and can deliver up to 2Gb/s data rate in a 500MHz channel bandwidth with 19.8mW power consumption and 9.9pJ/b energy efficiency. Being a coherent transceiver, it outputs -5.5dBm power, achieves -67.5dBm sensitivity at 1Gb/s and 1dB de-sensitization during FDD operation while tolerating -26dBm close-in Wi-Fi blockers.
{"title":"A 2Gb/s 9.9pJ/b Sub-10GHz Wireless Transceiver for Reconfigurable FDD Wireless Networks and Short-Range Multicast Applications","authors":"Renzhi Liu, Beevi K. T. Asma, R. Dorrance, T. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, B. Carlton","doi":"10.1109/RFIC54546.2022.9863181","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863181","url":null,"abstract":"This paper presents a sub-10GHz wireless transceiver for short-range multicast applications in a reconfigurable FDD wireless network. The transceiver adopts a digital-process-friendly architecture and can deliver up to 2Gb/s data rate in a 500MHz channel bandwidth with 19.8mW power consumption and 9.9pJ/b energy efficiency. Being a coherent transceiver, it outputs -5.5dBm power, achieves -67.5dBm sensitivity at 1Gb/s and 1dB de-sensitization during FDD operation while tolerating -26dBm close-in Wi-Fi blockers.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131845379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863130
Amr Ahmed, Gabriel M. Rebeiz
This work presents a passive harmonic rejection mixer which employs resistive scaling to maintain high linearity and to achieve 3rd and 5th harmonic rejection. The 8-phase 50% duty-cycle clocks are generated using polyphase filters without any clock dividers, and isolation between the 4 mixers is achieved using a Wilkinson network in the RF path. This enables the mixer to operate at mm-wave frequencies with wide instantaneous bandwidth, and greatly reduces the LO power consumption due to the much lower operating frequency of the LO network. The mixer is fabricated in the GlobalFoundries CMOS 45-RFSOI process and has a measured conversion loss of 12 dB with a 3-dB bandwidth of 8- 30 GHz, and an IF instantaneous bandwidth of up to 8 GHz. The measured harmonic rejection ratio (HRR) at the 2nd, 3rd and 5th harmonics is better than 27 dBc across the entire bandwidth. An input P1dB of 4.2-7 dBm is achieved at 8–30 GHz due to the passive architecture. Application areas are in high linearity high-If mm-wave 5G systems and wideband receivers.
{"title":"A 8–30 GHz Passive Harmonic Rejection Mixer with 8 GHz Instantaneous IF Bandwidth in 45RFSOI","authors":"Amr Ahmed, Gabriel M. Rebeiz","doi":"10.1109/RFIC54546.2022.9863130","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863130","url":null,"abstract":"This work presents a passive harmonic rejection mixer which employs resistive scaling to maintain high linearity and to achieve 3rd and 5th harmonic rejection. The 8-phase 50% duty-cycle clocks are generated using polyphase filters without any clock dividers, and isolation between the 4 mixers is achieved using a Wilkinson network in the RF path. This enables the mixer to operate at mm-wave frequencies with wide instantaneous bandwidth, and greatly reduces the LO power consumption due to the much lower operating frequency of the LO network. The mixer is fabricated in the GlobalFoundries CMOS 45-RFSOI process and has a measured conversion loss of 12 dB with a 3-dB bandwidth of 8- 30 GHz, and an IF instantaneous bandwidth of up to 8 GHz. The measured harmonic rejection ratio (HRR) at the 2nd, 3rd and 5th harmonics is better than 27 dBc across the entire bandwidth. An input P1dB of 4.2-7 dBm is achieved at 8–30 GHz due to the passive architecture. Application areas are in high linearity high-If mm-wave 5G systems and wideband receivers.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133455860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863116
Rajath Bindiganavile, Asif Wahid, Jacob Atkinson, A. Tajalli
A wideband and ultra low-noise Phase-Locked Loop (PLL) circuit is designed and implemented in a $0.18 mu mathrm{m}$ BiCMOS/SiGe technology to operate at a nominal frequency of 35.68 GHz. Incorporating a multi-phase phase frequency detector along with a high frequency reference signal, the bandwidth of the PLL was maximized to reduce the phase noise and jitter contribution of the forward path loop components within the frequency band of interest. A multi-phase phase comparator also relaxes the constraints imposed by the sampling nature of the PLL, allowing for a more convenient performance optimization with reduced jitter peaking and more optimal loop characteristics. The PLL was measured to have a Phase Noise of −113.3 dBc/Hz at an offset frequency of 1 MHz, and a total integrated jitter of 59 fs-rms integrated from 1 kHz to 100 MHz, consuming 194.6 mW with a jitter-power FoM −241.6 dB. The power dissipation of the proposed PLL is lower than implementations in similar technology nodes, while obviously higher than designs made in advanced CMOS/FinFET technologies. The PLL has been designed in BiCMOS/SiGe $0.18 mu mathrm{m}$, aiming to be integrated together with power amplifiers in a 3D structure targeted for the next generation 5G systems.
设计并实现了一种宽带超低噪声锁相环(PLL)电路，该电路采用$0.18 mu mathrm{m}$ BiCMOS/SiGe技术，工作频率为35.68 GHz。结合多相相位频率检测器和高频参考信号，锁相环的带宽被最大化，以减少感兴趣频带内正向路径环路分量的相位噪声和抖动贡献。多相相位比较器还放宽了锁相环采样特性所施加的限制，允许更方便的性能优化，减少抖动峰值和更优化的环路特性。在偏移频率为1mhz时，锁相环的相位噪声为- 113.3 dBc/Hz，从1khz到100mhz的总集成抖动为59 fs-rms，抖动功率为- 241.6 dB，消耗194.6 mW。所提出的锁相环的功耗低于类似技术节点的实现，而明显高于先进CMOS/FinFET技术的设计。该锁相环采用BiCMOS/SiGe $0.18 mu maththrm {m}$设计，旨在与功率放大器集成在针对下一代5G系统的3D结构中。
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