Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863164
Elham Rahimi, Farhad Bozorgi, G. Hueber
This work presents a 2-way 3-stage D-band Power Amplifier (PA) in 22nm FD-SOI technology. A dynamic 3-stage bias scaling technique is proposed for this PA. It is based on leveraging the back-gate terminal in CMOS FD-SOI technology to optimize the power consumption of each stage adaptive to the input power of the PA, and hence improve its overall PAE in the linear range, i.e. at OP1dB and power back-off. The PA has been fabricated on a die with the core area of 0.16mm 2. Small signal and large signal characteristics of the PA chip have been measured. At 1V supply voltage and frequency of 135GHz, it provides 14.2dB power gain with 20GHz and 52GHz 3-dB and 6-dB bandwidth, respectively. Measurement results show this PA achieves 7.7% and 3.1% PAE at 9.6 dBm OP1dB and 6dB back-off that features >1.5X and >2X improvement, respectively, compared to the state-of-the-art D-band PAs in CMOS technologies.
{"title":"A 22nm FD-SOI CMOS 2-way D-band Power Amplifier Achieving PAE of 7.7% at 9.6dBm OP1dB and 3.1% at 6dB Back-off by Leveraging Adaptive Back-Gate Bias Technique","authors":"Elham Rahimi, Farhad Bozorgi, G. Hueber","doi":"10.1109/RFIC54546.2022.9863164","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863164","url":null,"abstract":"This work presents a 2-way 3-stage D-band Power Amplifier (PA) in 22nm FD-SOI technology. A dynamic 3-stage bias scaling technique is proposed for this PA. It is based on leveraging the back-gate terminal in CMOS FD-SOI technology to optimize the power consumption of each stage adaptive to the input power of the PA, and hence improve its overall PAE in the linear range, i.e. at OP1dB and power back-off. The PA has been fabricated on a die with the core area of 0.16mm 2. Small signal and large signal characteristics of the PA chip have been measured. At 1V supply voltage and frequency of 135GHz, it provides 14.2dB power gain with 20GHz and 52GHz 3-dB and 6-dB bandwidth, respectively. Measurement results show this PA achieves 7.7% and 3.1% PAE at 9.6 dBm OP1dB and 6dB back-off that features >1.5X and >2X improvement, respectively, compared to the state-of-the-art D-band PAs in CMOS technologies.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122301444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863193
Mengchu Fang, T. Yoshimasu
In this paper, a harmonic tuned low-power low-phase-noise VCO IC with a novel bias feedback circuit is proposed. The transformer-based LC tank providing high impedance at the second and third harmonics is used to improve the phase noise performance. In addition, a novel feedback circuit is designed to suppress the gate-to-source voltage of the core transistors under their threshold voltage at the steady state while guaranteeing the robust start-up of the oscillation. The novel feedback circuit that requires no dc power supply can operate with an extremely small additional dc power consumption. The proposed VCO IC is designed, fabricated, and fully evaluated on-wafer in 40-nm CMOS SOI process. The proposed VCO IC has exhibited a measured best phase noise of -131.8 dBc/Hz at 10-MHz offset from the oscillation frequency of 14.94 GHz under a dc power consumption of only 1.4 mW.
{"title":"A 14-GHz-Band Harmonic Tuned Low-Power Low-Phase-Noise VCO IC with a Novel Bias Feedback Circuit in 40-nm CMOS SOI","authors":"Mengchu Fang, T. Yoshimasu","doi":"10.1109/RFIC54546.2022.9863193","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863193","url":null,"abstract":"In this paper, a harmonic tuned low-power low-phase-noise VCO IC with a novel bias feedback circuit is proposed. The transformer-based LC tank providing high impedance at the second and third harmonics is used to improve the phase noise performance. In addition, a novel feedback circuit is designed to suppress the gate-to-source voltage of the core transistors under their threshold voltage at the steady state while guaranteeing the robust start-up of the oscillation. The novel feedback circuit that requires no dc power supply can operate with an extremely small additional dc power consumption. The proposed VCO IC is designed, fabricated, and fully evaluated on-wafer in 40-nm CMOS SOI process. The proposed VCO IC has exhibited a measured best phase noise of -131.8 dBc/Hz at 10-MHz offset from the oscillation frequency of 14.94 GHz under a dc power consumption of only 1.4 mW.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130343263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863196
M. Radpour, L. Belostotski
This paper proposes using the back-gate terminal of an FDSOI transistor for input power matching. This concept is experimentally demonstrated with a 22-nm FDSOI low-noise amplifier (LNA). Thanks to the real part of the back-gate impedance, the LNA| S11| < −10-dB bandwidth extends from 6.1 to 38.6 GHz. In addition, applying input to both the front-and back-gate terminals, as well as employing a current-reuse configuration, increases the effective transconductance of the LNA first stage, thereby increasing its gain and lowering its input-referred noise. As a result, the LNA is able to achieve 12.2 ± 3.4dB of gain, −13dBm of IP1dB, and a noise-figure minimum of 1.9 dB while consuming 7.8 mW of power and occupying 0.03-mm2 of active area.
{"title":"An LNA with Input Power Match from 6.1 to 38.6 GHz, the Noise-Figure Minimum of 1.9 dB, and Employing Back Gate for Matching","authors":"M. Radpour, L. Belostotski","doi":"10.1109/RFIC54546.2022.9863196","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863196","url":null,"abstract":"This paper proposes using the back-gate terminal of an FDSOI transistor for input power matching. This concept is experimentally demonstrated with a 22-nm FDSOI low-noise amplifier (LNA). Thanks to the real part of the back-gate impedance, the LNA| S11| < −10-dB bandwidth extends from 6.1 to 38.6 GHz. In addition, applying input to both the front-and back-gate terminals, as well as employing a current-reuse configuration, increases the effective transconductance of the LNA first stage, thereby increasing its gain and lowering its input-referred noise. As a result, the LNA is able to achieve 12.2 ± 3.4dB of gain, −13dBm of IP1dB, and a noise-figure minimum of 1.9 dB while consuming 7.8 mW of power and occupying 0.03-mm2 of active area.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126114791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863107
Ce Yang, Shiyu Su, M. Chen
This paper presents a non-uniform (NU) time-approximation filter (TAF) technique for a wireless receiver to reject unwanted blockers spectrally. The proposed NU-TAF leverages the alias-spreading property of NU sampling (NUS) and a TAF that approximates an FIR filter response in the time domain, achieving an overall flexible filter response with a higher attenuation factor. The filter response can be readily reconfigured by changing the NU sequence and/or the TAF waveform without adjusting the passive component value. Additionally, a quad-switch integrator is proposed to significantly reduce power consumption by sharing the current among the Gm cells. A proof-of-concept millimeter-wave receiver is implemented in 28nm CMOS. Thanks to the NU-TAF, the receiver prototype achieves >45dB blocker rejection with a 33.7-GHz carrier frequency. The EVM measures −30.9dB using a 100-MSymbol/s 64QAM signal in the presence of a 10dBc out-of-band blocker.
{"title":"A Millimeter-Wave Mixer-First Receiver with Non-Uniform Time-Approximation Filter Achieving $> 45text{-dB}$ Blocker Rejection","authors":"Ce Yang, Shiyu Su, M. Chen","doi":"10.1109/RFIC54546.2022.9863107","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863107","url":null,"abstract":"This paper presents a non-uniform (NU) time-approximation filter (TAF) technique for a wireless receiver to reject unwanted blockers spectrally. The proposed NU-TAF leverages the alias-spreading property of NU sampling (NUS) and a TAF that approximates an FIR filter response in the time domain, achieving an overall flexible filter response with a higher attenuation factor. The filter response can be readily reconfigured by changing the NU sequence and/or the TAF waveform without adjusting the passive component value. Additionally, a quad-switch integrator is proposed to significantly reduce power consumption by sharing the current among the Gm cells. A proof-of-concept millimeter-wave receiver is implemented in 28nm CMOS. Thanks to the NU-TAF, the receiver prototype achieves >45dB blocker rejection with a 33.7-GHz carrier frequency. The EVM measures −30.9dB using a 100-MSymbol/s 64QAM signal in the presence of a 10dBc out-of-band blocker.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114922197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863117
Kangseop Lee, Chan-Gyu Choi, Kyunghwan Kim, Seunghoon Lee, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song
Despite several advantages in terms of linearity and operating bandwidth, LO phase-shifting is not widely used in beamforming transceivers due to the difficulty in realizing fine phase resolution. Regarding the use of a $times mathrm{M}$ frequency multiplier, the phase resolution at $mathrm{f}_{text{LO}}/mathrm{M}$ should be much higher than that desired at $mathrm{f}_{text{LO}}$ Here, we propose a frequency multiplier based LO phase-shifting technique that does not reduce the phase resolution after the frequency multiplication. At the cost of a few phase states out of $2^{mathrm{n}}$, the phase resolution at fLO/M can be retained after the frequency multiplier. For experimental evaluation, the proposed scheme was implemented in an E-band beamforming receiver. Because the proposed scheme is suitable for fine resolution and broadband transceivers at millimeter-wave frequencies, the bandwidth of the receiver reaches as high as 23 GHz at 77 GHz with phase resolution and rms phase error of 2.835° and 0.29°, respectively.
{"title":"Highly Accurate Frequency Quadrupler Based LO Phase Shifter Achieving 0.29° RMS Phase Error for Wideband E-band Beamforming Receiver","authors":"Kangseop Lee, Chan-Gyu Choi, Kyunghwan Kim, Seunghoon Lee, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9863117","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863117","url":null,"abstract":"Despite several advantages in terms of linearity and operating bandwidth, LO phase-shifting is not widely used in beamforming transceivers due to the difficulty in realizing fine phase resolution. Regarding the use of a $times mathrm{M}$ frequency multiplier, the phase resolution at $mathrm{f}_{text{LO}}/mathrm{M}$ should be much higher than that desired at $mathrm{f}_{text{LO}}$ Here, we propose a frequency multiplier based LO phase-shifting technique that does not reduce the phase resolution after the frequency multiplication. At the cost of a few phase states out of $2^{mathrm{n}}$, the phase resolution at fLO/M can be retained after the frequency multiplier. For experimental evaluation, the proposed scheme was implemented in an E-band beamforming receiver. Because the proposed scheme is suitable for fine resolution and broadband transceivers at millimeter-wave frequencies, the bandwidth of the receiver reaches as high as 23 GHz at 77 GHz with phase resolution and rms phase error of 2.835° and 0.29°, respectively.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-01DOI: 10.1109/RFIC54546.2022.9863079
Travis Forbes, Benjamin Magstadt, J. Moody, Andrew Suchanek, Spencer Nelson
A 0.2-2 GHz digitally programmable RF delay element based on a time-interleaved multi-stage switched-capacitor (TIMS-SC) approach is presented. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. The delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55-448.6 ns programmable delay range with $< 0.12 %$ delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm2 area efficiency. The device achieves 24 dB gain, 7.1 dB noise figure, and consumes 80 mW from a 1 V supply with an active area of 1.36 mm2.
{"title":"A 0.2-2 GHz Time-Interleaved Multi-Stage Switched-Capacitor Delay Element Achieving 448.6 ns Delay and 330 ns/mm2 Area Efficiency","authors":"Travis Forbes, Benjamin Magstadt, J. Moody, Andrew Suchanek, Spencer Nelson","doi":"10.1109/RFIC54546.2022.9863079","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863079","url":null,"abstract":"A 0.2-2 GHz digitally programmable RF delay element based on a time-interleaved multi-stage switched-capacitor (TIMS-SC) approach is presented. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. The delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55-448.6 ns programmable delay range with $< 0.12 %$ delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm2 area efficiency. The device achieves 24 dB gain, 7.1 dB noise figure, and consumes 80 mW from a 1 V supply with an active area of 1.36 mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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