Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863118
Q. Yu, Jeffrey Garrett, Seahee Hwangbo, G. Dogiamis, S. Rami
This paper presents an F-band power amplifier (PA) designed using novel back-end-of-line (BEOL) in Intel 16 technology. In the PA transistor array, skip-layer vias which directly connect transistor to thick metal layers are used to reduce parasitics from BEOL and improve the PA performance. This 2-stage PA shows excellent peak PAE and gain per stage. At 110GHz, the measured $mathrm{P}_{text{sat}}$, peak PAE, linear power gain, and OP1dB are 11.8dBm, 23.8%, 17.1dB, and 9.2dBm, respectively. The core area of the PA is 0.023mm2, enabling compact integration into phased array or waveguide based transceivers. To the authors' knowledge, this is the first circuit demonstration using skip-layer via that operates beyond 100GHz.
{"title":"An F-Band Power Amplifier with Skip-Layer Via Achieving 23.8% PAE in FinFET Technology","authors":"Q. Yu, Jeffrey Garrett, Seahee Hwangbo, G. Dogiamis, S. Rami","doi":"10.1109/RFIC54546.2022.9863118","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863118","url":null,"abstract":"This paper presents an F-band power amplifier (PA) designed using novel back-end-of-line (BEOL) in Intel 16 technology. In the PA transistor array, skip-layer vias which directly connect transistor to thick metal layers are used to reduce parasitics from BEOL and improve the PA performance. This 2-stage PA shows excellent peak PAE and gain per stage. At 110GHz, the measured $mathrm{P}_{text{sat}}$, peak PAE, linear power gain, and OP1dB are 11.8dBm, 23.8%, 17.1dB, and 9.2dBm, respectively. The core area of the PA is 0.023mm2, enabling compact integration into phased array or waveguide based transceivers. To the authors' knowledge, this is the first circuit demonstration using skip-layer via that operates beyond 100GHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125370582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863159
Seongwoog Oh, Jinhyun Kim, Jungsuek Oh
This work presents a novel switch-less reconfigurable triple-/push-push dual-band VCO topology and design methods for a W-band metal-oxide-semiconductor (CMOS) voltage-controlled oscillator (VCO). A clover-shaped inductor with a three-port connection and single frequency multiplied output port configuration provides switch-less mode changes between triple-push and push-push operation. This topology is demonstrated in a W-band VCO by controlling three cores with a measured phase noise of −109.17 dBc/Hz at a 10-MHz offset of a 105.3 GHz carrier. The measured center frequency of each band is 91.04 GHz and 102.33 GHz with a tuning range of 10.4% and 14.1 %, respectively. The proposed VCO with independent core on/off state control enables low parasitic switch-less frequency band shift resulting in a superior tuning range compared to those of conventional dual-/single-band VCOs. The effectiveness of this approach is demonstrated through fabrication in a 28-nm CMOS process, with the best FOMT being −174.4 dBc/Hz in this case.
{"title":"Sub- THz Switch-less Reconfigurable Triple-/Push-push Dual-band VCO for 6G Communication","authors":"Seongwoog Oh, Jinhyun Kim, Jungsuek Oh","doi":"10.1109/RFIC54546.2022.9863159","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863159","url":null,"abstract":"This work presents a novel switch-less reconfigurable triple-/push-push dual-band VCO topology and design methods for a W-band metal-oxide-semiconductor (CMOS) voltage-controlled oscillator (VCO). A clover-shaped inductor with a three-port connection and single frequency multiplied output port configuration provides switch-less mode changes between triple-push and push-push operation. This topology is demonstrated in a W-band VCO by controlling three cores with a measured phase noise of −109.17 dBc/Hz at a 10-MHz offset of a 105.3 GHz carrier. The measured center frequency of each band is 91.04 GHz and 102.33 GHz with a tuning range of 10.4% and 14.1 %, respectively. The proposed VCO with independent core on/off state control enables low parasitic switch-less frequency band shift resulting in a superior tuning range compared to those of conventional dual-/single-band VCOs. The effectiveness of this approach is demonstrated through fabrication in a 28-nm CMOS process, with the best FOMT being −174.4 dBc/Hz in this case.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133768570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863116
Rajath Bindiganavile, Asif Wahid, Jacob Atkinson, A. Tajalli
A wideband and ultra low-noise Phase-Locked Loop (PLL) circuit is designed and implemented in a $0.18 mu mathrm{m}$ BiCMOS/SiGe technology to operate at a nominal frequency of 35.68 GHz. Incorporating a multi-phase phase frequency detector along with a high frequency reference signal, the bandwidth of the PLL was maximized to reduce the phase noise and jitter contribution of the forward path loop components within the frequency band of interest. A multi-phase phase comparator also relaxes the constraints imposed by the sampling nature of the PLL, allowing for a more convenient performance optimization with reduced jitter peaking and more optimal loop characteristics. The PLL was measured to have a Phase Noise of −113.3 dBc/Hz at an offset frequency of 1 MHz, and a total integrated jitter of 59 fs-rms integrated from 1 kHz to 100 MHz, consuming 194.6 mW with a jitter-power FoM −241.6 dB. The power dissipation of the proposed PLL is lower than implementations in similar technology nodes, while obviously higher than designs made in advanced CMOS/FinFET technologies. The PLL has been designed in BiCMOS/SiGe $0.18 mu mathrm{m}$, aiming to be integrated together with power amplifiers in a 3D structure targeted for the next generation 5G systems.
设计并实现了一种宽带超低噪声锁相环(PLL)电路，该电路采用$0.18 mu mathrm{m}$ BiCMOS/SiGe技术，工作频率为35.68 GHz。结合多相相位频率检测器和高频参考信号，锁相环的带宽被最大化，以减少感兴趣频带内正向路径环路分量的相位噪声和抖动贡献。多相相位比较器还放宽了锁相环采样特性所施加的限制，允许更方便的性能优化，减少抖动峰值和更优化的环路特性。在偏移频率为1mhz时，锁相环的相位噪声为- 113.3 dBc/Hz，从1khz到100mhz的总集成抖动为59 fs-rms，抖动功率为- 241.6 dB，消耗194.6 mW。所提出的锁相环的功耗低于类似技术节点的实现，而明显高于先进CMOS/FinFET技术的设计。该锁相环采用BiCMOS/SiGe $0.18 mu maththrm {m}$设计，旨在与功率放大器集成在针对下一代5G系统的3D结构中。
{"title":"A 59-fs-rms 35-GHz PLL with FoM of −241-dB in $0.18-mu mathrm{m}$ BiCMOS/SiGe Technology","authors":"Rajath Bindiganavile, Asif Wahid, Jacob Atkinson, A. Tajalli","doi":"10.1109/RFIC54546.2022.9863116","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863116","url":null,"abstract":"A wideband and ultra low-noise Phase-Locked Loop (PLL) circuit is designed and implemented in a $0.18 mu mathrm{m}$ BiCMOS/SiGe technology to operate at a nominal frequency of 35.68 GHz. Incorporating a multi-phase phase frequency detector along with a high frequency reference signal, the bandwidth of the PLL was maximized to reduce the phase noise and jitter contribution of the forward path loop components within the frequency band of interest. A multi-phase phase comparator also relaxes the constraints imposed by the sampling nature of the PLL, allowing for a more convenient performance optimization with reduced jitter peaking and more optimal loop characteristics. The PLL was measured to have a Phase Noise of −113.3 dBc/Hz at an offset frequency of 1 MHz, and a total integrated jitter of 59 fs-rms integrated from 1 kHz to 100 MHz, consuming 194.6 mW with a jitter-power FoM −241.6 dB. The power dissipation of the proposed PLL is lower than implementations in similar technology nodes, while obviously higher than designs made in advanced CMOS/FinFET technologies. The PLL has been designed in BiCMOS/SiGe $0.18 mu mathrm{m}$, aiming to be integrated together with power amplifiers in a 3D structure targeted for the next generation 5G systems.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863182
Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi
This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.
{"title":"28 GHz Compact LNAs with 1.9 dB NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques in 65nm CMOS","authors":"Xiangrong Huang, Haikun Jia, W. Deng, Zhihua Wang, B. Chi","doi":"10.1109/RFIC54546.2022.9863182","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863182","url":null,"abstract":"This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and EM dual-feedforward techniques are proposed to improve the LNA's noise performance and reduce the chip area. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3-dB bandwidth (BW) from 25.6 to 29.9 GHz, and -12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW Pdc. The second LNA employs the current-reuse topology, which reduces the power consumption to 3.6 mW at the cost of a 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65nm CMOS process. The two LNAs have the same 200 µm × 300 µm core chip area.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132677510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9862949
Seunghoon Lee, Kyunghwan Kim, Kangseop Lee, Sungmin Cho, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song
This paper presents an E-band direct conversion IQ transmitter (TX) with IQ calibration for joint radar-communications system. To generate high-quality digitally modulated signal and frequency-modulated continuous-wave (FMCW) radar chirp signal, I/Q calibration capability is integrated in the TX with a miniaturized hybrid coupler and variable capacitors. The measured image rejection ratio and LO feedthrough suppression, which are critical for both communication and FMCW signal generation, are better than 36 and 23 dB, respectively, in the range of 74–83 GHz. The TX successfully generates not only a 24-Gb/s 16-QAM modulated signal but also a FMCW modulated signal with 1 GHz bandwidth. Moreover, as the LO frequency is tuned from around 74 GHz to 83 GHz, 16-QAM with EVM around −22 dB is measured. The output P1dB and conversion gain of the TX are 9.8 dBm and 12 dB, respectively.
{"title":"An E-band CMOS Direct Conversion IQ Transmitter for Radar and Communication Applications","authors":"Seunghoon Lee, Kyunghwan Kim, Kangseop Lee, Sungmin Cho, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9862949","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9862949","url":null,"abstract":"This paper presents an E-band direct conversion IQ transmitter (TX) with IQ calibration for joint radar-communications system. To generate high-quality digitally modulated signal and frequency-modulated continuous-wave (FMCW) radar chirp signal, I/Q calibration capability is integrated in the TX with a miniaturized hybrid coupler and variable capacitors. The measured image rejection ratio and LO feedthrough suppression, which are critical for both communication and FMCW signal generation, are better than 36 and 23 dB, respectively, in the range of 74–83 GHz. The TX successfully generates not only a 24-Gb/s 16-QAM modulated signal but also a FMCW modulated signal with 1 GHz bandwidth. Moreover, as the LO frequency is tuned from around 74 GHz to 83 GHz, 16-QAM with EVM around −22 dB is measured. The output P1dB and conversion gain of the TX are 9.8 dBm and 12 dB, respectively.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9862955
T. Zou, Hao Xu, Yizhuo Wang, Weitian Liu, T. Han, Zengqi Wang, Nan Li, Mi Tian, Weiqiang Zhu, Na Yan
This paper presents a novel capacitor assisting triple-winding transformer (CTTF) low noise amplifier (LNA) with ultra-low noise figure (NF) and a flat passband gain in 130nm SOI CMOS process. The assisting capacitor in the triple-winding transformer expands the design space by enabling independent control of the coupling strength between each two inductors. The negative resistor enhanced by the assisting capacitor boosts the transformer gain that not only suppresses the noise from the second stage, but also leads to a wider passband by compensating the gain droop from the active transistors. Through two-stage simultaneous noise and power matching, the LNA provides a remarkable 0.8-1.5 dB NF, <−14dB S11, <−8dB S22, −11.8dBm IP1dB and 21.8-23.3dB power gain across the 6-12GHz passband with ±0.75dB ripple while drawing 20mA from a 3.3V supply. It reports the lowest NF so far.
{"title":"A Capacitor Assisting Triple-Winding Transformer Low-Noise Amplifier with 0.8-1.5dB NF $6-12text{GHz BW} pm 0.75text{dB}$ Ripple in 130nm SOI CMOS","authors":"T. Zou, Hao Xu, Yizhuo Wang, Weitian Liu, T. Han, Zengqi Wang, Nan Li, Mi Tian, Weiqiang Zhu, Na Yan","doi":"10.1109/RFIC54546.2022.9862955","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9862955","url":null,"abstract":"This paper presents a novel capacitor assisting triple-winding transformer (CTTF) low noise amplifier (LNA) with ultra-low noise figure (NF) and a flat passband gain in 130nm SOI CMOS process. The assisting capacitor in the triple-winding transformer expands the design space by enabling independent control of the coupling strength between each two inductors. The negative resistor enhanced by the assisting capacitor boosts the transformer gain that not only suppresses the noise from the second stage, but also leads to a wider passband by compensating the gain droop from the active transistors. Through two-stage simultaneous noise and power matching, the LNA provides a remarkable 0.8-1.5 dB NF, <−14dB S11, <−8dB S22, −11.8dBm IP1dB and 21.8-23.3dB power gain across the 6-12GHz passband with ±0.75dB ripple while drawing 20mA from a 3.3V supply. It reports the lowest NF so far.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127455896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863147
Mina Kim, Cheng Wang, L. Yi, Hae-Seung Lee, R. Han
This paper presents a dual-loop chip-scale molecular clock (CSMC), which enhances the Allan Deviation performance by combining high signal-to-noise ratio of using fundamental mode and long-term stability of using higher order modes in derivative molecular absorption spectroscopy. In addition, digital frequency-error integration is adopted in the frequency-locked loop to provide an infinite open-loop DC gain, which fully suppresses any frequency drift caused by the temperature-sensitive crystal oscillator. This new generation CSMC is implemented in 65-nm CMOS, and achieves 20 ppt (part-per-trillion) Allan Deviation at 10,000 s averaging time with 71-mW power consumption.
{"title":"A Sub- THz CMOS Molecular Clock with 20 ppt Stability at 10,000 s Based on Dual-Loop Spectroscopic Detection and Digital Frequency Error Integration","authors":"Mina Kim, Cheng Wang, L. Yi, Hae-Seung Lee, R. Han","doi":"10.1109/RFIC54546.2022.9863147","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863147","url":null,"abstract":"This paper presents a dual-loop chip-scale molecular clock (CSMC), which enhances the Allan Deviation performance by combining high signal-to-noise ratio of using fundamental mode and long-term stability of using higher order modes in derivative molecular absorption spectroscopy. In addition, digital frequency-error integration is adopted in the frequency-locked loop to provide an infinite open-loop DC gain, which fully suppresses any frequency drift caused by the temperature-sensitive crystal oscillator. This new generation CSMC is implemented in 65-nm CMOS, and achieves 20 ppt (part-per-trillion) Allan Deviation at 10,000 s averaging time with 71-mW power consumption.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125298394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863143
Victor Åberg, C. Fager, R. Hou, L. Svensson
We present a Cartesian I/Q modulator based on dual 10-bit RF-DACs. Non-overlapping LO signals and a segmented RF - DAC architecture with scaled bit currents contribute to good linearity and allow low-complexity DPD. Unit-cell flip-flops with a balanced clock distribution enable a high sample rate. Drive slope control for data switches reduce out-of-band emissions. Implemented in 22 nm FDSOI CMOS, the modulator operates up to 26 GHz with a maximum sample rate of 11 GS/s. The modulator is used to demonstrate transmission of a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and an OFDM signal comprising four aggregated 400-MHz 64QAM channels at an EVM of 6.43 %. The results demonstrate the potential of the proposed modulator architecture for realization of ultra wideband transmitters for high performance mm-wave systems.
{"title":"An 11 GS/s 2×10b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals","authors":"Victor Åberg, C. Fager, R. Hou, L. Svensson","doi":"10.1109/RFIC54546.2022.9863143","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863143","url":null,"abstract":"We present a Cartesian I/Q modulator based on dual 10-bit RF-DACs. Non-overlapping LO signals and a segmented RF - DAC architecture with scaled bit currents contribute to good linearity and allow low-complexity DPD. Unit-cell flip-flops with a balanced clock distribution enable a high sample rate. Drive slope control for data switches reduce out-of-band emissions. Implemented in 22 nm FDSOI CMOS, the modulator operates up to 26 GHz with a maximum sample rate of 11 GS/s. The modulator is used to demonstrate transmission of a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and an OFDM signal comprising four aggregated 400-MHz 64QAM channels at an EVM of 6.43 %. The results demonstrate the potential of the proposed modulator architecture for realization of ultra wideband transmitters for high performance mm-wave systems.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127518732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863142
Heyu Ren, D. Ye, Binbin Chen, Xu Jin, Wenjun Gong, Rongjin Xu, C. R. Shi
A 915MHz ultra-low-power blocker-enhanced wake- up receiver (BE-WuRx) is presented in a 65nm CMOS process. Employing the proposed frequency-hopping two-tone modulation (FH-TTM), the BE-WuRx can dynamically convert the in-band blocker power to data power, and achieves a −63.6dBm sensitivity without blocker and a −90dBm enhanced sensitivity with a −25dBm CW interferer, while just consuming $mathbf{19}mathbf{mu}mathbf{W}$. With the −63.6dBm sensitivity, the BE-WuRx performs 53dB tolerance to the in-band blocker, exhibiting 14dB improvement compared to the case that FH- TTM is off. The wake-up latency is 6.4ms for a quiet channel and 6.4 to 64ms for a congested channel.
{"title":"A 915MHz $19mu mathrm{W}$ Blocker-Enhanced Wake-Up Receiver with Frequency-Hopping Two-Tone Modulation Achieving 53dB Tolerance to In-Band Interference","authors":"Heyu Ren, D. Ye, Binbin Chen, Xu Jin, Wenjun Gong, Rongjin Xu, C. R. Shi","doi":"10.1109/RFIC54546.2022.9863142","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863142","url":null,"abstract":"A 915MHz ultra-low-power blocker-enhanced wake- up receiver (BE-WuRx) is presented in a 65nm CMOS process. Employing the proposed frequency-hopping two-tone modulation (FH-TTM), the BE-WuRx can dynamically convert the in-band blocker power to data power, and achieves a −63.6dBm sensitivity without blocker and a −90dBm enhanced sensitivity with a −25dBm CW interferer, while just consuming $mathbf{19}mathbf{mu}mathbf{W}$. With the −63.6dBm sensitivity, the BE-WuRx performs 53dB tolerance to the in-band blocker, exhibiting 14dB improvement compared to the case that FH- TTM is off. The wake-up latency is 6.4ms for a quiet channel and 6.4 to 64ms for a congested channel.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127537644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863085
D. Parat, A. Serhan, P. Reynier, R. Mourot, A. Giry
This paper presents a high-power monolithic SOI-CMOS Front End-Module (FEM) supporting Wi-Fi 6/6E signals at 2.4GHz. The FEM includes an SP4T antenna switch, a power amplifier (PA), a low noise amplifier (LNA) with bypass mode, and a digital controller. The RX path achieves 15dB of power gain with less than 1.8dB of noise figure (NF) with 10mW of power consumption. The TX path delivers 33.4dBm of saturated output power $(mathrm{P}_{text{sat}})$ with 51.7% of peak PAE and 28.5dB of power gain. Without DPD, the reconfigurable TX path achieves state-of-the art performance with 23.4/20dBm of linear output power $(mathrm{P}_{text{out}})$ for an EVM of −35.1/−43.9dB and an operating current of 282/254mA for 802.11ac/ax MCS9/MCS11 40MHz signals.
{"title":"A Linear High-Power Reconfigurable SOI-CMOS Front-End Module for WI-FI 6/6E Applications","authors":"D. Parat, A. Serhan, P. Reynier, R. Mourot, A. Giry","doi":"10.1109/RFIC54546.2022.9863085","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863085","url":null,"abstract":"This paper presents a high-power monolithic SOI-CMOS Front End-Module (FEM) supporting Wi-Fi 6/6E signals at 2.4GHz. The FEM includes an SP4T antenna switch, a power amplifier (PA), a low noise amplifier (LNA) with bypass mode, and a digital controller. The RX path achieves 15dB of power gain with less than 1.8dB of noise figure (NF) with 10mW of power consumption. The TX path delivers 33.4dBm of saturated output power $(mathrm{P}_{text{sat}})$ with 51.7% of peak PAE and 28.5dB of power gain. Without DPD, the reconfigurable TX path achieves state-of-the art performance with 23.4/20dBm of linear output power $(mathrm{P}_{text{out}})$ for an EVM of −35.1/−43.9dB and an operating current of 282/254mA for 802.11ac/ax MCS9/MCS11 40MHz signals.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125781117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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