Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863121
Tzu-Yuan Huang, Bill Y. Lin, N. Mannem, Hua Wang
This work proposes a wideband 26-33GHz MIMO receiver (RX) array that leverages time-modulation operation to achieve concurrent steerable Multi-Beam MIMOs (MB-MIMO) using only one set of array beamformer. The time-modulation enables spectral-spatial mapping that maps the multi-beam information to a single-wire interface. A proof-of-concept 26- 33GHz time-modulated RX array with MB-MIMOs is implemented in 45nm CMOS RF SOI. The proposed RX demonstrates S11 < −10 dB across 24~32 GHz and its maximum conversion gain of 28dB with a 3dB-bandwidth of 26 to 33 GHz. The measured NF is 5.78 dB at 28 GHz with RX input-referred IP1dB of −38dBm. Also, this proposed RX is supported with wideband-16/64QAM single carrier modulations.
{"title":"A 26-to-33GHz Time-Modulated Spectral-Spatial Mapping MIMO Receiver Array with Concurrent Steerable Multi-Beams Using Only One Beamformer and One Single-Wire Interface","authors":"Tzu-Yuan Huang, Bill Y. Lin, N. Mannem, Hua Wang","doi":"10.1109/RFIC54546.2022.9863121","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863121","url":null,"abstract":"This work proposes a wideband 26-33GHz MIMO receiver (RX) array that leverages time-modulation operation to achieve concurrent steerable Multi-Beam MIMOs (MB-MIMO) using only one set of array beamformer. The time-modulation enables spectral-spatial mapping that maps the multi-beam information to a single-wire interface. A proof-of-concept 26- 33GHz time-modulated RX array with MB-MIMOs is implemented in 45nm CMOS RF SOI. The proposed RX demonstrates S11 < −10 dB across 24~32 GHz and its maximum conversion gain of 28dB with a 3dB-bandwidth of 26 to 33 GHz. The measured NF is 5.78 dB at 28 GHz with RX input-referred IP1dB of −38dBm. Also, this proposed RX is supported with wideband-16/64QAM single carrier modulations.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124356440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863192
Aniello Franzese, R. Negra, A. Malignaggi
This paper presents a miniaturized bidirectional power divider (PD) which incorporates the function of a single-pole-double-throw (SPDT) switch in addition to its regular operation. Therefore, the new component can be used as a transmitting/receiving (TRx) switch. With the proposed solution, several PDs are removed, and the SPDT is integrated, thereby saving area and reducing the overall insertion loss (IL) in phased antenna arrays. Moreover, due to its compact size and simplified routing strategy, the design is also suitable whenever many TRx elements are required, i.e., especially for 5G mm-wave beamformers. A 4-way prototype has been fabricated in a 130-nm SiGe BiCMOS technology to validate the concept and occupies an effective area of 180x170 µm2. Measurements results show an IL of 3.1 dB at 28 GHz and isolation higher than 19 dB. In addition, phase and amplitude errors are lower than 3° and 0.2 dB, respectively. In conclusion, a device that integrates the functionalities of SPDTs and PDs is reported without increasing area occupation compared to state-of-the-art PDs and, therefore, paving the way for compact, cost-effective beamformer chips.
{"title":"4-Way 0.031-mm2 Switchable Bidirectional Power Divider for 5G mm-Wave Beamformers","authors":"Aniello Franzese, R. Negra, A. Malignaggi","doi":"10.1109/RFIC54546.2022.9863192","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863192","url":null,"abstract":"This paper presents a miniaturized bidirectional power divider (PD) which incorporates the function of a single-pole-double-throw (SPDT) switch in addition to its regular operation. Therefore, the new component can be used as a transmitting/receiving (TRx) switch. With the proposed solution, several PDs are removed, and the SPDT is integrated, thereby saving area and reducing the overall insertion loss (IL) in phased antenna arrays. Moreover, due to its compact size and simplified routing strategy, the design is also suitable whenever many TRx elements are required, i.e., especially for 5G mm-wave beamformers. A 4-way prototype has been fabricated in a 130-nm SiGe BiCMOS technology to validate the concept and occupies an effective area of 180x170 µm2. Measurements results show an IL of 3.1 dB at 28 GHz and isolation higher than 19 dB. In addition, phase and amplitude errors are lower than 3° and 0.2 dB, respectively. In conclusion, a device that integrates the functionalities of SPDTs and PDs is reported without increasing area occupation compared to state-of-the-art PDs and, therefore, paving the way for compact, cost-effective beamformer chips.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121354445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863144
Hongxin Tang, H. Qian, Bingzheng Yang, Tianyi Wang, Xun Luo
In this paper, an efficient switched-capacitor power amplifier (SCPA) with high linearity using on-chip self-calibration technique is proposed. The inherent AM-PM distortion in digital power amplifier (DPA) is decreased by the proposed self-calibration technique without any pre-distortion. Meanwhile, to improve the modulation bandwidth, a storage capacitor array (SCA) is introduced to decrease the settle-time of the calibration loop for transition among various baseband signals. The proposed polar Doherty SCPA is implemented in conventional 40-nm CMOS technology. It operates in 1.4-2.8 GHz with peak output power of 28.9 dBm, peak drain efficiency (DE) of 43.9%, peak system efficiency (SE) of 37.2%, and AM-PM distortion of 4.4°at 1.8 GHz. It supports 100 MHz 64-QAM signal (i.e., 22.6 dBm average output power, 4.87% EVM, and 33.9% average DE) and 10 MHz 1024-QAM signal (i.e., 21.3 dBm average output power, 1.77% EVM, and 32.1 % average DE) without any pre-distortion.
{"title":"A Polar Doherty SCPA with 4.4°AM-PM Distortion Using On-Chip Self-Calibration Supporting 64-/256-/1024-QAM","authors":"Hongxin Tang, H. Qian, Bingzheng Yang, Tianyi Wang, Xun Luo","doi":"10.1109/RFIC54546.2022.9863144","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863144","url":null,"abstract":"In this paper, an efficient switched-capacitor power amplifier (SCPA) with high linearity using on-chip self-calibration technique is proposed. The inherent AM-PM distortion in digital power amplifier (DPA) is decreased by the proposed self-calibration technique without any pre-distortion. Meanwhile, to improve the modulation bandwidth, a storage capacitor array (SCA) is introduced to decrease the settle-time of the calibration loop for transition among various baseband signals. The proposed polar Doherty SCPA is implemented in conventional 40-nm CMOS technology. It operates in 1.4-2.8 GHz with peak output power of 28.9 dBm, peak drain efficiency (DE) of 43.9%, peak system efficiency (SE) of 37.2%, and AM-PM distortion of 4.4°at 1.8 GHz. It supports 100 MHz 64-QAM signal (i.e., 22.6 dBm average output power, 4.87% EVM, and 33.9% average DE) and 10 MHz 1024-QAM signal (i.e., 21.3 dBm average output power, 1.77% EVM, and 32.1 % average DE) without any pre-distortion.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863080
Xi Chen, T. Siriburanon, Zhongzheng Wang, Jianglin Du, Yizhe Hu, A. Zhu, R. Staszewski
In this paper, we propose a digital-to-time conversion (DTC) technique operating entirely in the sinusiodal waveform voltage domain of a crystal oscillator (XO) before the signal's final slicing into the time-domain of the programmably delayed clock, with a deterministic predistortion to further improve the linearity. Precise timing delay is obtained by simply adjusting the dc offset of the sine signal. The technique merges the functionality of DTC with XO generation, thus drastically reducing the power consumption, while offering wide range with fine resolution, low noise and high linearity. Fabricated in 22-nm FD-SOI CMOS, the prototype of XO+DTC consumes only 0.52 mW while achieving a 546 ps range with fine resolution of 266 fs. The rms jitter is only 86.6 fs at a frequency of 100 MHz.
{"title":"A Digital-to-Time Converter Based on Crystal Oscillator Waveform Achieving 86-fs Jitter in 22-nm FD-SOI CMOS","authors":"Xi Chen, T. Siriburanon, Zhongzheng Wang, Jianglin Du, Yizhe Hu, A. Zhu, R. Staszewski","doi":"10.1109/RFIC54546.2022.9863080","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863080","url":null,"abstract":"In this paper, we propose a digital-to-time conversion (DTC) technique operating entirely in the sinusiodal waveform voltage domain of a crystal oscillator (XO) before the signal's final slicing into the time-domain of the programmably delayed clock, with a deterministic predistortion to further improve the linearity. Precise timing delay is obtained by simply adjusting the dc offset of the sine signal. The technique merges the functionality of DTC with XO generation, thus drastically reducing the power consumption, while offering wide range with fine resolution, low noise and high linearity. Fabricated in 22-nm FD-SOI CMOS, the prototype of XO+DTC consumes only 0.52 mW while achieving a 546 ps range with fine resolution of 266 fs. The rms jitter is only 86.6 fs at a frequency of 100 MHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863162
S. Parthasarathy, R. Shumovich, J. Salcedo, Roxann Broughton-Blanchard, J. Hajjar
The relatively poor ESD robustness of many RF ports is a direct result of the performance degradation introduced by traditional ESD diodes. The later limits the amount of ESD protection that can be tolerated in RF applications. This paper introduces a ground-referenced low capacitance and highly linear Silicon Controlled Rectifiers (SCR) topology designed in l6nm CMOS FinFET process technology. The device presented in this work is employed to protect RF ports with asymmetrical signal swings in the range of + 3.0V /-l.0V operating to 20 GHz with a 3rd order linearity specification requirement of −75dBc or greater.
{"title":"Device for Protecting High Frequency and High Data Rate Interface Applications in FinFET Process Technologies","authors":"S. Parthasarathy, R. Shumovich, J. Salcedo, Roxann Broughton-Blanchard, J. Hajjar","doi":"10.1109/RFIC54546.2022.9863162","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863162","url":null,"abstract":"The relatively poor ESD robustness of many RF ports is a direct result of the performance degradation introduced by traditional ESD diodes. The later limits the amount of ESD protection that can be tolerated in RF applications. This paper introduces a ground-referenced low capacitance and highly linear Silicon Controlled Rectifiers (SCR) topology designed in l6nm CMOS FinFET process technology. The device presented in this work is employed to protect RF ports with asymmetrical signal swings in the range of + 3.0V /-l.0V operating to 20 GHz with a 3rd order linearity specification requirement of −75dBc or greater.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"341 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117350285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863114
S. Khokale, T. Ethirajan, H. K. Kakara, B. humphrey, K. Shanbhag, V. Vanukuru, V. Jain, S. Jai
An experimental low noise FET (LNFET) device is presented in this paper with $f_{mathrm{T}}/f_{text{MAX}}$ of 325/475GHz. To authors' knowledge, this is the highest reported $f_{text{MAX}}$ for a CMOS device. The device was demonstrated on a 45 nm partially depleted Silicon on insulator (PDSOI) CMOS wafer for low noise amplifier (LNA) design. The device has been developed for Ku/K/Ka-band applications in SATCOM (satellite communications) RF transceiver. It shows $sim 0.26/0.47/0.60 text{dB}$ NFMIN and $sim 20.1/17.8/16.6 text{dB} text{MSG}$ at 12 / 20 / 26 GHz respectively. LNA reference circuits at 12GHz and 20GHz were designed using this device with an inductively degenerated source cascode. Measured data from the circuits show NF of $sim 0.82text{dB}$ at 12GHz and $sim 1.23text{dB}$ at 20GHz with 15.2dB and 12.3dB gain respectively. Measured NF is the lowest amongst recent silicon-based designs in these frequency bands.
{"title":"LNFET device with 325/475GHz $f_{mathrm{T}}/f_{text{MAX}}$ and 0.47dB NFMIN at 20GHz for SATCOM applications in 45nm PDSOI CMOS","authors":"S. Khokale, T. Ethirajan, H. K. Kakara, B. humphrey, K. Shanbhag, V. Vanukuru, V. Jain, S. Jai","doi":"10.1109/RFIC54546.2022.9863114","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863114","url":null,"abstract":"An experimental low noise FET (LNFET) device is presented in this paper with $f_{mathrm{T}}/f_{text{MAX}}$ of 325/475GHz. To authors' knowledge, this is the highest reported $f_{text{MAX}}$ for a CMOS device. The device was demonstrated on a 45 nm partially depleted Silicon on insulator (PDSOI) CMOS wafer for low noise amplifier (LNA) design. The device has been developed for Ku/K/Ka-band applications in SATCOM (satellite communications) RF transceiver. It shows $sim 0.26/0.47/0.60 text{dB}$ NFMIN and $sim 20.1/17.8/16.6 text{dB} text{MSG}$ at 12 / 20 / 26 GHz respectively. LNA reference circuits at 12GHz and 20GHz were designed using this device with an inductively degenerated source cascode. Measured data from the circuits show NF of $sim 0.82text{dB}$ at 12GHz and $sim 1.23text{dB}$ at 20GHz with 15.2dB and 12.3dB gain respectively. Measured NF is the lowest amongst recent silicon-based designs in these frequency bands.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116620892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863172
Iman Habibagahi, Jaeeun Jang, A. Babakhani
Multisite stimulation has shown enhanced clinical outcomes in different biomedical applications. This work presents a novel System on Chip (SoC) solution that enables up to 16 implantable stimulators to be powered and controlled using a single transmitter. The implants can be powered at 40.68MHz industrial, scientific and medical (ISM) band up to 80mm in air. Each implant can tolerate up to 70° misalignment between the Tx and Rx coil, and they provide two channels for constant voltage stimulation. The frequency, voltage, and pulse width are sent wirelessly using pulse width modulated amplitude shift keying (PWM-ASK) to each chip. The performance of implantable devices was verified by bilateral in vivo (pig) vagus nerve stimulation (VNS) and in-vitro measurements. The implant has a diameter of 14mm and weighs 80mg.
{"title":"Miniaturized Wirelessly Powered and Controlled Implants for Vagus Nerve Stimulation","authors":"Iman Habibagahi, Jaeeun Jang, A. Babakhani","doi":"10.1109/RFIC54546.2022.9863172","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863172","url":null,"abstract":"Multisite stimulation has shown enhanced clinical outcomes in different biomedical applications. This work presents a novel System on Chip (SoC) solution that enables up to 16 implantable stimulators to be powered and controlled using a single transmitter. The implants can be powered at 40.68MHz industrial, scientific and medical (ISM) band up to 80mm in air. Each implant can tolerate up to 70° misalignment between the Tx and Rx coil, and they provide two channels for constant voltage stimulation. The frequency, voltage, and pulse width are sent wirelessly using pulse width modulated amplitude shift keying (PWM-ASK) to each chip. The performance of implantable devices was verified by bilateral in vivo (pig) vagus nerve stimulation (VNS) and in-vitro measurements. The implant has a diameter of 14mm and weighs 80mg.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114998860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nanosecond-scale on-chip delay is critical for integrated wideband self-interference cancellation (SIC) in full-duplex (FD) system, especially for radio frequency (RF) domain SIC. In this paper, we presented a FD receiver with multi-domain SIC using capacitor stacking based second-order delay cell in the RF canceller which breaks the trade-off between delay, loss, size and noise. A prototype is fabricated in 65nm CMOS process. The FD receiver can operate in 0.5-4GHz with gain of 29-32dB. At 2GHz local oscillator (LO) frequency, the RF canceller can achieve delay of 2-8ns while consuming 10mW. The baseband (BB) canceller can achieve delay of 9-15ns while consuming 4.4mW. These large nanosecond-scale delays ensure more than 34dB SIC over 20MHz modulated signal bandwidth in case of applying a commercial circulator (isolation of 23-26dB). In FD mode, the RF and BB cancellers degrade the receiver noise figure (NF) by 0.9dB and 0.4dB, respectively. The receiver power handling is improved by 11.5dB. The active chip area is only 0.4mm2.
{"title":"A 0.5-4GHz Full-Duplex Receiver with Multi-Domain Self-Interference Cancellation Using Capacitor Stacking Based Second-Order Delay Cells in RF Canceller","authors":"Chuangguo Wang, Wei Li, Fan Chen, Wen Zuo, Yunyou Pu, Hongtao Xu","doi":"10.1109/RFIC54546.2022.9863120","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863120","url":null,"abstract":"Nanosecond-scale on-chip delay is critical for integrated wideband self-interference cancellation (SIC) in full-duplex (FD) system, especially for radio frequency (RF) domain SIC. In this paper, we presented a FD receiver with multi-domain SIC using capacitor stacking based second-order delay cell in the RF canceller which breaks the trade-off between delay, loss, size and noise. A prototype is fabricated in 65nm CMOS process. The FD receiver can operate in 0.5-4GHz with gain of 29-32dB. At 2GHz local oscillator (LO) frequency, the RF canceller can achieve delay of 2-8ns while consuming 10mW. The baseband (BB) canceller can achieve delay of 9-15ns while consuming 4.4mW. These large nanosecond-scale delays ensure more than 34dB SIC over 20MHz modulated signal bandwidth in case of applying a commercial circulator (isolation of 23-26dB). In FD mode, the RF and BB cancellers degrade the receiver noise figure (NF) by 0.9dB and 0.4dB, respectively. The receiver power handling is improved by 11.5dB. The active chip area is only 0.4mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122656825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863133
Soumen Mohapatra, Chung-Ching Lin, M. Chahardori, Erfan Ghaderi, Md Aminul Hoque, Subhanshu Gupta, D. Heo
In the baseband time delay (TD) elements used for delay compensation in discrete-time beamformers, phase interpolator (PI) plays a crucial role as the resolution of the PI defines the delay resolution of the TD. In this paper, we present a process and temperature invariant high-resolution and highly linear low-power PI. The proposed PI uses current integration which generates an adaptable constant slope-and-swing ramp signal to achieve low power. By switched-capacitor bias generation, the PI linearity is enhanced with 0.2 LSB DNL and 0.3 LSB INL, respectively. The 7-bit PI is realized in 65nm CMOS technology can generate the full range delay with a resolution of 8psec with the input of 1GHz. The PI consumes a power of $mathbf{345}mu mathbf{W}$ and and occupies an active area of 0.021mm2.
{"title":"A $345mu mathbf{W}$ 1 GHz Process and Temperature Invariant Constant Slope-and-Swing Ramp-based 7-bit Phase Interpolator for True-Time-Delay Spatial Signal Processors","authors":"Soumen Mohapatra, Chung-Ching Lin, M. Chahardori, Erfan Ghaderi, Md Aminul Hoque, Subhanshu Gupta, D. Heo","doi":"10.1109/RFIC54546.2022.9863133","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863133","url":null,"abstract":"In the baseband time delay (TD) elements used for delay compensation in discrete-time beamformers, phase interpolator (PI) plays a crucial role as the resolution of the PI defines the delay resolution of the TD. In this paper, we present a process and temperature invariant high-resolution and highly linear low-power PI. The proposed PI uses current integration which generates an adaptable constant slope-and-swing ramp signal to achieve low power. By switched-capacitor bias generation, the PI linearity is enhanced with 0.2 LSB DNL and 0.3 LSB INL, respectively. The 7-bit PI is realized in 65nm CMOS technology can generate the full range delay with a resolution of 8psec with the input of 1GHz. The PI consumes a power of $mathbf{345}mu mathbf{W}$ and and occupies an active area of 0.021mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124945517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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