Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9862949
Seunghoon Lee, Kyunghwan Kim, Kangseop Lee, Sungmin Cho, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song
This paper presents an E-band direct conversion IQ transmitter (TX) with IQ calibration for joint radar-communications system. To generate high-quality digitally modulated signal and frequency-modulated continuous-wave (FMCW) radar chirp signal, I/Q calibration capability is integrated in the TX with a miniaturized hybrid coupler and variable capacitors. The measured image rejection ratio and LO feedthrough suppression, which are critical for both communication and FMCW signal generation, are better than 36 and 23 dB, respectively, in the range of 74–83 GHz. The TX successfully generates not only a 24-Gb/s 16-QAM modulated signal but also a FMCW modulated signal with 1 GHz bandwidth. Moreover, as the LO frequency is tuned from around 74 GHz to 83 GHz, 16-QAM with EVM around −22 dB is measured. The output P1dB and conversion gain of the TX are 9.8 dBm and 12 dB, respectively.
{"title":"An E-band CMOS Direct Conversion IQ Transmitter for Radar and Communication Applications","authors":"Seunghoon Lee, Kyunghwan Kim, Kangseop Lee, Sungmin Cho, Seung-Uk Choi, Ja-yol Lee, B. Koo, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9862949","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9862949","url":null,"abstract":"This paper presents an E-band direct conversion IQ transmitter (TX) with IQ calibration for joint radar-communications system. To generate high-quality digitally modulated signal and frequency-modulated continuous-wave (FMCW) radar chirp signal, I/Q calibration capability is integrated in the TX with a miniaturized hybrid coupler and variable capacitors. The measured image rejection ratio and LO feedthrough suppression, which are critical for both communication and FMCW signal generation, are better than 36 and 23 dB, respectively, in the range of 74–83 GHz. The TX successfully generates not only a 24-Gb/s 16-QAM modulated signal but also a FMCW modulated signal with 1 GHz bandwidth. Moreover, as the LO frequency is tuned from around 74 GHz to 83 GHz, 16-QAM with EVM around −22 dB is measured. The output P1dB and conversion gain of the TX are 9.8 dBm and 12 dB, respectively.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863138
Shuxin Ming, Rakibul Islam, Jin Zhou
This work presents a commutated-LC-negative-R delay circuit for broadband signal processing at RF. It introduces negative resistance to compensate inductor loss in a commutated- LC broadband delay circuit, and unveils a new capability of time-varying RF circuits that we call harmonic power recycling. For a time-invariant circuit or an N -path filter circuit, its desired passband consists of only one harmonic. Hence, energies at all other harmonics provided by the broadband negative resistance are wasted. In contrast, a commutated-LC broadband delay circuit has multiple harmonics across its passband, recycling the wasted RF energies from the negative resistance. This harmonic power recycling results in improved noise figure and low dc power in addition to reduced insertion loss (IL). A proof-of-concept CMOS delay line is implemented, achieving 1.5-ns delay, 1.4-GHz instantaneous bandwidth (BW), and 6-dB IL at the C band.
本文提出了一种用于射频宽带信号处理的换相lc -负r延迟电路。它在整流LC宽带延迟电路中引入负电阻来补偿电感损耗，并揭示了时变射频电路的新能力，我们称之为谐波功率回收。对于时不变电路或N路滤波电路，其期望通带仅由一个谐波组成。因此，宽带负电阻提供的所有其他谐波的能量都被浪费了。相反，换相lc宽带延迟电路在其通频带上具有多个谐波，从负电阻中回收浪费的射频能量。这种谐波功率循环除了降低插入损耗(IL)外，还可以改善噪声系数和降低直流功率。实现了一种概念验证型CMOS延迟线，在C波段实现了1.5 ns延迟、1.4 ghz瞬时带宽(BW)和6 db IL。
{"title":"A C-Band Commutated-LC-Negative-R Delay Circuit with Harmonic Power Recycling Achieving 1.5-ns Delay, 1.4-GHz BW, and 6-dB IL","authors":"Shuxin Ming, Rakibul Islam, Jin Zhou","doi":"10.1109/RFIC54546.2022.9863138","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863138","url":null,"abstract":"This work presents a commutated-LC-negative-R delay circuit for broadband signal processing at RF. It introduces negative resistance to compensate inductor loss in a commutated- LC broadband delay circuit, and unveils a new capability of time-varying RF circuits that we call harmonic power recycling. For a time-invariant circuit or an N -path filter circuit, its desired passband consists of only one harmonic. Hence, energies at all other harmonics provided by the broadband negative resistance are wasted. In contrast, a commutated-LC broadband delay circuit has multiple harmonics across its passband, recycling the wasted RF energies from the negative resistance. This harmonic power recycling results in improved noise figure and low dc power in addition to reduced insertion loss (IL). A proof-of-concept CMOS delay line is implemented, achieving 1.5-ns delay, 1.4-GHz instantaneous bandwidth (BW), and 6-dB IL at the C band.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134308994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863211
Ji-Seong Kim, Chan-Gyu Choi, Kangseop Lee, Kyunghwan Kim, Seung-Uk Choi, Ho-Jin Song
In order to overcome the performance limitation of CMOS technology at high frequencies above 100 GHz, the concept of maximum achievable gain (Gmax) with an embedding network has been investigated. In this work, a novel Gmax-core embedding a T-shaped gain-boosting network that provides two Gmax-peaks is analyzed and demonstrated in the D-band with a 28-nm FD-SOI CMOS process. With the proposed topology, one can design the peak Gmax frequencies and in/output impedances simultaneously as desired for high gain and broadband operation. The fabricated amplifier offers a peak small-signal gain and bandwidth of 14.5 dB and 26 GHz, respectively, with power consumption of 21.6 mW in 117 - 143 GHz.
{"title":"Analysis and Design of Dual-Peak Gmax-Core CMOS Amplifier in D-Band Embedding a T-Shaped Network","authors":"Ji-Seong Kim, Chan-Gyu Choi, Kangseop Lee, Kyunghwan Kim, Seung-Uk Choi, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9863211","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863211","url":null,"abstract":"In order to overcome the performance limitation of CMOS technology at high frequencies above 100 GHz, the concept of maximum achievable gain (Gmax) with an embedding network has been investigated. In this work, a novel Gmax-core embedding a T-shaped gain-boosting network that provides two Gmax-peaks is analyzed and demonstrated in the D-band with a 28-nm FD-SOI CMOS process. With the proposed topology, one can design the peak Gmax frequencies and in/output impedances simultaneously as desired for high gain and broadband operation. The fabricated amplifier offers a peak small-signal gain and bandwidth of 14.5 dB and 26 GHz, respectively, with power consumption of 21.6 mW in 117 - 143 GHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131222987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863101
Benqing Guo, Haishi Wang, Yao Wang, Kenneth K. Li, Lei Li, Wanting Zhou
A mixer-first receiver frontend with resistive-feedback baseband is proposed. The baseband combination of Gm and transimpedance amplifier (TIA) is designed to cover a wide frequency range for high data rate applications. The N-path filtering at the RF side and enhanced filtering at the BB side inhibit out-of-band blocker interferences. The receiver is fabricated in a 65 nm CMOS. Measurement results display an NF of 2.3 dB and a conversion gain of 33.5 dB at 2 GHz fLO. The in-band and out-of-band IIP3 are −7.5 dBm and 19 dBm respectively. The receiver core draws 34 mW in the signal path and occupies an active area of 0.31 mm2.
{"title":"A Mixer-First Receiver Frontend with Resistive-Feedback Baseband Achieving 200 MHz IF Bandwidth in 65 nm CMOS","authors":"Benqing Guo, Haishi Wang, Yao Wang, Kenneth K. Li, Lei Li, Wanting Zhou","doi":"10.1109/RFIC54546.2022.9863101","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863101","url":null,"abstract":"A mixer-first receiver frontend with resistive-feedback baseband is proposed. The baseband combination of Gm and transimpedance amplifier (TIA) is designed to cover a wide frequency range for high data rate applications. The N-path filtering at the RF side and enhanced filtering at the BB side inhibit out-of-band blocker interferences. The receiver is fabricated in a 65 nm CMOS. Measurement results display an NF of 2.3 dB and a conversion gain of 33.5 dB at 2 GHz fLO. The in-band and out-of-band IIP3 are −7.5 dBm and 19 dBm respectively. The receiver core draws 34 mW in the signal path and occupies an active area of 0.31 mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114498136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863096
Antoine Le Ravallec, P. Garcia, J. A. Gonçalves, L. Vincent, J. Duchamp, P. Benech
This paper presents a 76–81 GHz receiver path for automotive radar applications in 28-nm FD-SOI CMOS technology. It introduces a new accurate phase control using MOS varactors. The proposed solution implemented in the front-end low noise amplifier (LNA) allows a phase control of maximum 22° with a 0.2° resolution for minimum degradation of the LNA and the receiver performances. The receiver contains a two-stage LNA with 5.5 dB noise figure (NF), a passive mixer, a local oscillator (LO) driver and a baseband (BB) amplifier. The receiver exhibits input compression points (ICP1dB) of −25.2 dBm and −12.6 dBm with and without BB amplifier, respectively. The active area of the receiver path is only 0.057 mm2 for a total power consumption of 41.7 mW.
{"title":"A Compact 28-nm FD-SOI CMOS 76–81 GHz Automotive Band Receiver Path with Accurate 0.2° Phase Control Resolution","authors":"Antoine Le Ravallec, P. Garcia, J. A. Gonçalves, L. Vincent, J. Duchamp, P. Benech","doi":"10.1109/RFIC54546.2022.9863096","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863096","url":null,"abstract":"This paper presents a 76–81 GHz receiver path for automotive radar applications in 28-nm FD-SOI CMOS technology. It introduces a new accurate phase control using MOS varactors. The proposed solution implemented in the front-end low noise amplifier (LNA) allows a phase control of maximum 22° with a 0.2° resolution for minimum degradation of the LNA and the receiver performances. The receiver contains a two-stage LNA with 5.5 dB noise figure (NF), a passive mixer, a local oscillator (LO) driver and a baseband (BB) amplifier. The receiver exhibits input compression points (ICP1dB) of −25.2 dBm and −12.6 dBm with and without BB amplifier, respectively. The active area of the receiver path is only 0.057 mm2 for a total power consumption of 41.7 mW.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127274811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863173
X. Ding, G. Niu, H. Zhang, W. Wang, K. Imura, F. Dai
Impact of non-conducting RF and DC stresses on transistor I-V and RF characteristics are investigated experimentally on a production 14/16-nm FinFET technology for the first time, for high voltage devices commonly used in RF PAs. The degradation is shown to be non-quasi static (NQS), and does not permit the use of DC stress to predict device lifetime under RF stress. Further modeling shows that these FinFETs provide enough margins against non-conducting RF stress for intended PA application.
{"title":"Impact of non-Conducting RF and DC Hot Carrier Stresses on FinFET Reliability for RF Power Amplifiers","authors":"X. Ding, G. Niu, H. Zhang, W. Wang, K. Imura, F. Dai","doi":"10.1109/RFIC54546.2022.9863173","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863173","url":null,"abstract":"Impact of non-conducting RF and DC stresses on transistor I-V and RF characteristics are investigated experimentally on a production 14/16-nm FinFET technology for the first time, for high voltage devices commonly used in RF PAs. The degradation is shown to be non-quasi static (NQS), and does not permit the use of DC stress to predict device lifetime under RF stress. Further modeling shows that these FinFETs provide enough margins against non-conducting RF stress for intended PA application.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121459126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863141
Zhaowu Wang, Zhenyu Wang, T. Yang, Yong Wang
As a rule of thumb, the number of throws, bandwidth (BW), and insertion losses (IL) limit each other in a single switch circuit. This paper proposes three topologies, i.e. symmetrically-routed structure, series-transmission-line-shunt unit, and reconfigurable matching network, to breakthrough these limits. Demonstrations show this work attains a single-pole ten-throw (SP10T) switch and achieves an impressive BW from DC-to-18 GHz with a favourable IL performance (1.1-3.2 dB) compared to prior arts. RF input power for 1-dB compression is 21.2 dBm, and isolation is higher than 24 dB.
{"title":"A DC-to-18 GHz SP10T RF Switch Using Symmetrically-Routed Series- TL-Shunt and Reconfigurable Single-Pole Network Topologies Presenting 1.1-to-3.2 dB IL in 0.15 $mu$ m GaAs pHEMT","authors":"Zhaowu Wang, Zhenyu Wang, T. Yang, Yong Wang","doi":"10.1109/RFIC54546.2022.9863141","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863141","url":null,"abstract":"As a rule of thumb, the number of throws, bandwidth (BW), and insertion losses (IL) limit each other in a single switch circuit. This paper proposes three topologies, i.e. symmetrically-routed structure, series-transmission-line-shunt unit, and reconfigurable matching network, to breakthrough these limits. Demonstrations show this work attains a single-pole ten-throw (SP10T) switch and achieves an impressive BW from DC-to-18 GHz with a favourable IL performance (1.1-3.2 dB) compared to prior arts. RF input power for 1-dB compression is 21.2 dBm, and isolation is higher than 24 dB.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863175
Kyunghwan Kim, Kangseop Lee, Seung-Uk Choi, Ji-Seong Kim, Chan-Gyu Choi, Ho-Jin Song
A 97–107 GHz power amplifier (PA) based on a stacked-FET topology is presented. In a triple-stacked-FeT structure, stacking efficiency is analyzed using four combinations of series or shunt inductors for compensating phase of impedances between stack nodes, and optimal inductances are chosen. Phase-compensation inductors are implemented by considering a finite quality factor with the tradeoff between layout size and stacking efficiency. A layout of a transistor cell is customized to reduce gate resistance. The triple-stacked-FET PA provides peak PSAT and PAEMAX of 15.1 dBm and 18.6%, respectively. The presented PA achieves the highest power density and efficiency compared to state-of-the-art CMOS PAs in F-band.
{"title":"A 97–107 GHz Triple-Stacked-FET Power Amplifier with 23.7dB Peak Gain, 15.1dBm PSAT, and 18.6% PAEMAX in 28-nm FD-SOI CMOS","authors":"Kyunghwan Kim, Kangseop Lee, Seung-Uk Choi, Ji-Seong Kim, Chan-Gyu Choi, Ho-Jin Song","doi":"10.1109/RFIC54546.2022.9863175","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863175","url":null,"abstract":"A 97–107 GHz power amplifier (PA) based on a stacked-FET topology is presented. In a triple-stacked-FeT structure, stacking efficiency is analyzed using four combinations of series or shunt inductors for compensating phase of impedances between stack nodes, and optimal inductances are chosen. Phase-compensation inductors are implemented by considering a finite quality factor with the tradeoff between layout size and stacking efficiency. A layout of a transistor cell is customized to reduce gate resistance. The triple-stacked-FET PA provides peak PSAT and PAEMAX of 15.1 dBm and 18.6%, respectively. The presented PA achieves the highest power density and efficiency compared to state-of-the-art CMOS PAs in F-band.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117255992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863161
M. Ouvrier-Buffet, A. Siligaris, J. González-Jiménez
This paper presents a multi-tone frequency generator in the sub-10 GHz range. The implemented circuit allows to reduce the number of interconnections between the control electronics and the quantum processor layer during reflectometry readout of spin qubits. The circuit is fabricated in a 45nm CMOS SOI technology. It is able to generate a multi-tone signal spaced by 500 MHz with 2.3 dB power ripple between the tones. It achieves phase noise performances between −107 dBc/Hz and −112 dBc/Hz @1 MHz offset according the considered tones. The complete system presents a consumption of 84.4 m W for an area of 0.27 mm2.
{"title":"Multi- Tone Frequency Generator for Gate-Based Readout of Spin Qubits","authors":"M. Ouvrier-Buffet, A. Siligaris, J. González-Jiménez","doi":"10.1109/RFIC54546.2022.9863161","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863161","url":null,"abstract":"This paper presents a multi-tone frequency generator in the sub-10 GHz range. The implemented circuit allows to reduce the number of interconnections between the control electronics and the quantum processor layer during reflectometry readout of spin qubits. The circuit is fabricated in a 45nm CMOS SOI technology. It is able to generate a multi-tone signal spaced by 500 MHz with 2.3 dB power ripple between the tones. It achieves phase noise performances between −107 dBc/Hz and −112 dBc/Hz @1 MHz offset according the considered tones. The complete system presents a consumption of 84.4 m W for an area of 0.27 mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115833730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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