Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161708
S. Ido, M. Imai, T. Kumise, M. Satoh, H. Horir, S. Ando
A vertical test structure was developed for measuring the contact resistance between two kinds of metal. The contact resistance between Al/TiN/AlSi and heavily As/sup +/-doped n/sup +/-poly Si was measured using this structure. The test structure was found to suppress nonuniform current density in the contact hole and to provide more accurate contact resistances. In addition, the R/sub c/ of a small contact window could be obtained from the extrapolation of the measurement data found for large contact windows.<>
{"title":"The vertical test structure for measuring contact resistance between two kinds of metal","authors":"S. Ido, M. Imai, T. Kumise, M. Satoh, H. Horir, S. Ando","doi":"10.1109/ICMTS.1990.161708","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161708","url":null,"abstract":"A vertical test structure was developed for measuring the contact resistance between two kinds of metal. The contact resistance between Al/TiN/AlSi and heavily As/sup +/-doped n/sup +/-poly Si was measured using this structure. The test structure was found to suppress nonuniform current density in the contact hole and to provide more accurate contact resistances. In addition, the R/sub c/ of a small contact window could be obtained from the extrapolation of the measurement data found for large contact windows.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114821639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161726
M. Cresswell, M. Gaitan, R. Allen, L. W. Linholm
Present a modified voltage-dividing potentiometer test structure which overcomes a problem typical in scaling electrical test structures: it provides a correction for electrical length shortening of a resistor strip caused by the attachment of voltage taps of nonnegligible width. The test structure was implemented in chrome on quartz, and measurements of displacements between 10 and 500 nm with +or-12-nm random error were made using available test equipment. The enhanced precision of the measurement derives from reducing the size of the structure from previous design methods. The enhanced accuracy of the displacement measurement derives from scaling the length of the potentiometer bridge while simultaneously providing for nonscaled widths of the voltage taps. Measurements using these corrections demonstrate an improvement of up to 20% in measurement accuracy, and further improvements can be expected with optimized designs.<>
{"title":"A modified sliding wire potentiometer test structure for mapping nanometer-level distances","authors":"M. Cresswell, M. Gaitan, R. Allen, L. W. Linholm","doi":"10.1109/ICMTS.1990.161726","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161726","url":null,"abstract":"Present a modified voltage-dividing potentiometer test structure which overcomes a problem typical in scaling electrical test structures: it provides a correction for electrical length shortening of a resistor strip caused by the attachment of voltage taps of nonnegligible width. The test structure was implemented in chrome on quartz, and measurements of displacements between 10 and 500 nm with +or-12-nm random error were made using available test equipment. The enhanced precision of the measurement derives from reducing the size of the structure from previous design methods. The enhanced accuracy of the displacement measurement derives from scaling the length of the potentiometer bridge while simultaneously providing for nonscaled widths of the voltage taps. Measurements using these corrections demonstrate an improvement of up to 20% in measurement accuracy, and further improvements can be expected with optimized designs.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161731
M. Fallon, J. Robertson, A. Walton, R. Holwill
Device isolation by means of LOCOS and field implantation are commonly incorporated in current MOS processes. These two process steps interact to affect the effective MOS transistor width. The authors examine the topographical features determined by pad oxide and nitride thicknesses and compare the physical with the effective electrical width. It is concluded that the limit in topographical packing density may be achieved by physical reduction of the bird's beak, but for varying pad oxide/nitride mask combinations the effective device width is limited by the presence of the field implant.<>
{"title":"Examination of LOCOS process parameters and the measurement of effective width","authors":"M. Fallon, J. Robertson, A. Walton, R. Holwill","doi":"10.1109/ICMTS.1990.161731","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161731","url":null,"abstract":"Device isolation by means of LOCOS and field implantation are commonly incorporated in current MOS processes. These two process steps interact to affect the effective MOS transistor width. The authors examine the topographical features determined by pad oxide and nitride thicknesses and compare the physical with the effective electrical width. It is concluded that the limit in topographical packing density may be achieved by physical reduction of the bird's beak, but for varying pad oxide/nitride mask combinations the effective device width is limited by the presence of the field implant.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131699324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161720
S. Voldman
Two- and three-dimensional leakage phenomena in moderately and heavily doped and gate diode structures are analyzed using a novel set of macro-array trench DRAM (dynamic random-access memory) capacitor storage nodes and planar MOS drain structures. Heavily doped gated diode structures (trench and planar) are used for the analysis of the gate-induced thermal generation mechanism and band-to-band tunneling. The results are relevant for understanding the leakage phenomena in trench DRAM and MOSFET drain structures.<>
{"title":"Trench DRAM structures for the analysis of two- and three-dimensional leakage phenomena","authors":"S. Voldman","doi":"10.1109/ICMTS.1990.161720","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161720","url":null,"abstract":"Two- and three-dimensional leakage phenomena in moderately and heavily doped and gate diode structures are analyzed using a novel set of macro-array trench DRAM (dynamic random-access memory) capacitor storage nodes and planar MOS drain structures. Heavily doped gated diode structures (trench and planar) are used for the analysis of the gate-induced thermal generation mechanism and band-to-band tunneling. The results are relevant for understanding the leakage phenomena in trench DRAM and MOSFET drain structures.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"1 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113990225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161723
M. Buehler, B. Blaes, G. Soli
Describes a methodology for using alpha particles to provide an independent measure of the cross section of an upset sensitive region in test SRAMs (static random-access memories). In addition, the thickness of over-layers and the alpha-particle collection depth were determined. These parameters are necessary in order to make precise estimates of the upset rates of memories due to cosmic-ray strikes. Measurements were made on 1.6- mu m n-well CMOS 4-kb test SRAMs irradiated with an Am-241 alpha-particle source.<>
描述了一种在测试sram(静态随机存取存储器)中使用α粒子来提供扰动敏感区域横截面的独立测量的方法。此外，还确定了覆盖层厚度和α -粒子收集深度。这些参数对于精确估计由于宇宙射线撞击造成的记忆破坏率是必要的。在用Am-241 α粒子源辐照的1.6 μ m n孔CMOS 4kb测试sram上进行了测量。
{"title":"Test SRAMs for characterizing alpha particle tracks in CMOS/bulk memories","authors":"M. Buehler, B. Blaes, G. Soli","doi":"10.1109/ICMTS.1990.161723","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161723","url":null,"abstract":"Describes a methodology for using alpha particles to provide an independent measure of the cross section of an upset sensitive region in test SRAMs (static random-access memories). In addition, the thickness of over-layers and the alpha-particle collection depth were determined. These parameters are necessary in order to make precise estimates of the upset rates of memories due to cosmic-ray strikes. Measurements were made on 1.6- mu m n-well CMOS 4-kb test SRAMs irradiated with an Am-241 alpha-particle source.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121987783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161712
P. Dars, R. Basset, G. Merckel
The use of gate isolated test transistors can lead to the creation of process-induced charges which cannot occur on transistors implemented on circuits. A test structure has been designed to separate the intrinsic process related defects which can result in yield losses on circuits, and the charges or states created in the devices usually used in test patterns. With the use of this collection test structure (CTS), the influence of the different process steps in terms of creation of charges can be identified; in particular, the role of the last steps can be pointed out.<>
{"title":"Analysis of process-induced charges created in MOSFETs and related collection test structures","authors":"P. Dars, R. Basset, G. Merckel","doi":"10.1109/ICMTS.1990.161712","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161712","url":null,"abstract":"The use of gate isolated test transistors can lead to the creation of process-induced charges which cannot occur on transistors implemented on circuits. A test structure has been designed to separate the intrinsic process related defects which can result in yield losses on circuits, and the charges or states created in the devices usually used in test patterns. With the use of this collection test structure (CTS), the influence of the different process steps in terms of creation of charges can be identified; in particular, the role of the last steps can be pointed out.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121102345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161734
K. Kubota, Y. Kawashima, S. Yoshida, M. Ishida
A simple method is proposed to determine lateral diffusion profiles for MOSFETs. The method compares the gate-to-substrate capacitance for a MOSFET with the gate biased in accumulation and the source and drain slightly forward-biased to that for a MOS capacitor with no diffusions. The results can be utilized for optimal design of submicrometer devices and modeling of two-dimensional diffusion.<>
{"title":"Measurement of lateral diffusion profiles for submicrometer MOSFETs","authors":"K. Kubota, Y. Kawashima, S. Yoshida, M. Ishida","doi":"10.1109/ICMTS.1990.161734","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161734","url":null,"abstract":"A simple method is proposed to determine lateral diffusion profiles for MOSFETs. The method compares the gate-to-substrate capacitance for a MOSFET with the gate biased in accumulation and the source and drain slightly forward-biased to that for a MOS capacitor with no diffusions. The results can be utilized for optimal design of submicrometer devices and modeling of two-dimensional diffusion.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121143578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161735
J. Anguita, C. Perello, M. Lozano, C. Cané, E. Lora-Tamayo
A novel test structure consisting of a varying length depletion IGFET (insulated-gate field effect transistor) with a shorted polysilicon gate-source junction is presented. This structure makes it possible to extract an effective channel length from an electrical measurement and, as a result, the amount of lateral diffusion on its source junction is extracted. A particular arrangement of the gate and source shorts is selected to eliminate misalignment errors.<>
{"title":"Measurement of lateral diffusion on technologies with polysilicon doping source with misalignment correction","authors":"J. Anguita, C. Perello, M. Lozano, C. Cané, E. Lora-Tamayo","doi":"10.1109/ICMTS.1990.161735","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161735","url":null,"abstract":"A novel test structure consisting of a varying length depletion IGFET (insulated-gate field effect transistor) with a shorted polysilicon gate-source junction is presented. This structure makes it possible to extract an effective channel length from an electrical measurement and, as a result, the amount of lateral diffusion on its source junction is extracted. A particular arrangement of the gate and source shorts is selected to eliminate misalignment errors.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161733
A. McCarthy, W. Lukaszek
A set of novel ion implant electrical test structures designed to measure shadowing channeling, and dose uniformity effects for the purpose of implanter calibration and evaluation has been designed and integrated onto one wafer, permitting the simultaneous monitoring of these effects in a single implant. The mask set has been designed so that it can be used in monitoring either p-type or n-type implants. It has been possible to fabricate eight different structures on a single wafer using only six mask levels. Results of experiments using these structures are presented and discussed.<>
{"title":"A new set of electrical test structures for simultaneous single-wafer monitoring of ion implant shadowing, channeling, and dose uniformity","authors":"A. McCarthy, W. Lukaszek","doi":"10.1109/ICMTS.1990.161733","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161733","url":null,"abstract":"A set of novel ion implant electrical test structures designed to measure shadowing channeling, and dose uniformity effects for the purpose of implanter calibration and evaluation has been designed and integrated onto one wafer, permitting the simultaneous monitoring of these effects in a single implant. The mask set has been designed so that it can be used in monitoring either p-type or n-type implants. It has been possible to fabricate eight different structures on a single wafer using only six mask levels. Results of experiments using these structures are presented and discussed.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122789526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161737
T. Ueda, H. Aoki, Y. Kinoshita, S. Wada, H. Miyatake, J. Kudo, T. Ashida
The lateral spread of high-energy implanted ions in Si is studied by electronic test structures. It is shown that the ions implanted through thick overlying layers spread significantly in the substrate. The lateral spread of boron ions is estimated to be about 1 mu m at a 650-keV implantation energy for 650-nm-thick dielectric film. The spread measured with the test structures shows rough agreement with simulation but with a slight difference. When it is required to separately control the threshold voltage of neighboring transistors in small-dimension devices using high-energy ion implantation, the neighboring transistors should be separated at least by the space determined by the spread of ions.<>
{"title":"Lateral spread of high energy implanted ions studied by electronic test structures","authors":"T. Ueda, H. Aoki, Y. Kinoshita, S. Wada, H. Miyatake, J. Kudo, T. Ashida","doi":"10.1109/ICMTS.1990.161737","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161737","url":null,"abstract":"The lateral spread of high-energy implanted ions in Si is studied by electronic test structures. It is shown that the ions implanted through thick overlying layers spread significantly in the substrate. The lateral spread of boron ions is estimated to be about 1 mu m at a 650-keV implantation energy for 650-nm-thick dielectric film. The spread measured with the test structures shows rough agreement with simulation but with a slight difference. When it is required to separately control the threshold voltage of neighboring transistors in small-dimension devices using high-energy ion implantation, the neighboring transistors should be separated at least by the space determined by the spread of ions.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116953475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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