Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161719
P. Girard, P. Nouet, F. M. Roche
A test structure dedicated to the evaluation of very low currents for MOS process characterization is presented. The device consists of an amplifier plus a bias voltage set implemented on the chip and connected to the leaky element. The principle is given, and SPICE simulations, based on 2- mu m CMOS industrial technology, show the structure response. Owing to this structure, a strong current amplification is obtained. Consequently, only a classical transistor parameter analyzer is required to evaluate currents in the fA range.<>
提出了一种用于评价MOS工艺特性的极低电流的测试结构。该器件包括放大器和在芯片上实现并连接到漏电元件的偏置电压组。给出了其工作原理，并基于2 μ m CMOS工业技术进行了SPICE仿真，验证了其结构响应。由于这种结构，获得了强电流放大。因此，只需要一个经典的晶体管参数分析仪来评估fA范围内的电流
{"title":"Simple evaluation of very low currents in process characterization","authors":"P. Girard, P. Nouet, F. M. Roche","doi":"10.1109/ICMTS.1990.161719","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161719","url":null,"abstract":"A test structure dedicated to the evaluation of very low currents for MOS process characterization is presented. The device consists of an amplifier plus a bias voltage set implemented on the chip and connected to the leaky element. The principle is given, and SPICE simulations, based on 2- mu m CMOS industrial technology, show the structure response. Owing to this structure, a strong current amplification is obtained. Consequently, only a classical transistor parameter analyzer is required to evaluate currents in the fA range.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117277475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161714
D. Dumin, N.B. Heilemann, N. Husain
A study of the dependence of thin dielectric wearout and breakdown on capacitor geometry was undertaken. A test chip was designed and fabricated with thin silicon oxides using different gate-metal processes. The breakdown voltage distributions as a function of area, perimeter, and process variations were measured. It was found that the intrinsic breakdown voltage depended on details of the capacitor geometry and gate processing. The wearout of the oxide was apparently independent of area. It was shown that ramp current-voltage testing was useful for characterizing a thin oxide process and for determining when edge effects were important.<>
{"title":"Test structures to investigate thin insulator dielectric wearout and breakdown","authors":"D. Dumin, N.B. Heilemann, N. Husain","doi":"10.1109/ICMTS.1990.161714","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161714","url":null,"abstract":"A study of the dependence of thin dielectric wearout and breakdown on capacitor geometry was undertaken. A test chip was designed and fabricated with thin silicon oxides using different gate-metal processes. The breakdown voltage distributions as a function of area, perimeter, and process variations were measured. It was found that the intrinsic breakdown voltage depended on details of the capacitor geometry and gate processing. The wearout of the oxide was apparently independent of area. It was shown that ramp current-voltage testing was useful for characterizing a thin oxide process and for determining when edge effects were important.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123737448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161724
M. Lozano, C. Cané, C. Perello, J. Anguita, E. Lora-Tamayo
An improvement of the triangular gate MOS transistor for misalignment measurement between gate and active area levels is presented. The number of devices required for the simultaneous determination of X and Y misalignment is reduced from four to three, resulting in a very compact structure with just four pads. Although this simplification is obtained at the cost of an increment of the complexity of the calculations, a simple iterative algorithm is enough to solve them. Two different device arrangements have been designed and fabricated with a NMOS/CMOS, 5- mu m, polysilicon gate technology.<>
{"title":"Improvement of the triangular MOS transistor for misalignment measurement","authors":"M. Lozano, C. Cané, C. Perello, J. Anguita, E. Lora-Tamayo","doi":"10.1109/ICMTS.1990.161724","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161724","url":null,"abstract":"An improvement of the triangular gate MOS transistor for misalignment measurement between gate and active area levels is presented. The number of devices required for the simultaneous determination of X and Y misalignment is reduced from four to three, resulting in a very compact structure with just four pads. Although this simplification is obtained at the cost of an increment of the complexity of the calculations, a simple iterative algorithm is enough to solve them. Two different device arrangements have been designed and fabricated with a NMOS/CMOS, 5- mu m, polysilicon gate technology.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123794487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161755
N. Shiono, T. Mizusawa
NAND and NOR gate chains including on-chip frequency variable clock generators are presented as a way of evaluating hot-electron-induced degradation of CMOS performance under realistic high-speed dynamic stress. Dual gate chains with a common input clock are suitable for measuring net gate delay time by subtracting the delay times of the two chains with different numbers of stages. Operating gate chains at higher frequencies and elevated supply voltages accelerates hot-electron-induced degradation of circuit performance to yield useful information for estimating lifetimes under normal-use conditions and realistic dynamic stress. Aluminum NAND gate chains with aluminum interconnect line loads are also suitable for estimating electromigration failure of aluminum lines in actual circuits through high-frequency operation and elevated temperature.<>
{"title":"Gate chain structures with on-chip clock generators for realistic high-speed dynamic stress","authors":"N. Shiono, T. Mizusawa","doi":"10.1109/ICMTS.1990.161755","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161755","url":null,"abstract":"NAND and NOR gate chains including on-chip frequency variable clock generators are presented as a way of evaluating hot-electron-induced degradation of CMOS performance under realistic high-speed dynamic stress. Dual gate chains with a common input clock are suitable for measuring net gate delay time by subtracting the delay times of the two chains with different numbers of stages. Operating gate chains at higher frequencies and elevated supply voltages accelerates hot-electron-induced degradation of circuit performance to yield useful information for estimating lifetimes under normal-use conditions and realistic dynamic stress. Aluminum NAND gate chains with aluminum interconnect line loads are also suitable for estimating electromigration failure of aluminum lines in actual circuits through high-frequency operation and elevated temperature.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161715
Y. Uraoka, H. Yoshikawa, N. Tsutsu, S. Akiyama
This system permits measurements of the initial breakdown characteristics, determination of the stress condition, and failure analysis consistently based on the evaluation theory. The failure modes both in initial characteristics and the time-dependent dielectric breakdown (TDDB) characteristics are experimentally found to correspond to each other. The intrinsic breakdown is considered to be caused by the concentration of the current in the edge region. The LOCOS structure plays an important role in the lifetime of the gate oxide.<>
{"title":"Evaluation of gate oxide reliability using luminescence method","authors":"Y. Uraoka, H. Yoshikawa, N. Tsutsu, S. Akiyama","doi":"10.1109/ICMTS.1990.161715","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161715","url":null,"abstract":"This system permits measurements of the initial breakdown characteristics, determination of the stress condition, and failure analysis consistently based on the evaluation theory. The failure modes both in initial characteristics and the time-dependent dielectric breakdown (TDDB) characteristics are experimentally found to correspond to each other. The intrinsic breakdown is considered to be caused by the concentration of the current in the edge region. The LOCOS structure plays an important role in the lifetime of the gate oxide.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127623493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161728
A. Satya
The IBM East Fishkill Facility uniquely utilizes the yield management test sites (YMTSs) as the basis for all of its accelerated yield learning. The author reviews the evolution of the YMTS to the improvements required to ensure rapid root-cause analysis and timely corrective actions. The YMTS data analysis, which reveals a high correlation between the predicted and the actual product final test yields, and the design criteria that helped achieve it are discussed. The success of the YMTS in predicting the job-by-job final test yields of the product has been demonstrated. A few design and model enhancements are identified as the pivotal contributors to this success. The current state of the art in test site design is also briefly introduced.<>
IBM East Fishkill设施独特地利用产量管理测试站点(ymts)作为其所有加速产量学习的基础。作者回顾了YMTS的演变，以确保快速的根本原因分析和及时的纠正措施所需的改进。YMTS数据分析揭示了预测和实际产品最终测试良率之间的高度相关性，并讨论了有助于实现这一目标的设计标准。该方法成功地预测了产品的每个作业的最终测试收率。一些设计和模型增强被认为是这一成功的关键贡献者。并简要介绍了试验场地设计的现状。
{"title":"Yield measurement tests sites","authors":"A. Satya","doi":"10.1109/ICMTS.1990.161728","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161728","url":null,"abstract":"The IBM East Fishkill Facility uniquely utilizes the yield management test sites (YMTSs) as the basis for all of its accelerated yield learning. The author reviews the evolution of the YMTS to the improvements required to ensure rapid root-cause analysis and timely corrective actions. The YMTS data analysis, which reveals a high correlation between the predicted and the actual product final test yields, and the design criteria that helped achieve it are discussed. The success of the YMTS in predicting the job-by-job final test yields of the product has been demonstrated. A few design and model enhancements are identified as the pivotal contributors to this success. The current state of the art in test site design is also briefly introduced.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121196243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161730
C. Weber
A plan for standardization of test structure design based on a high-level information model is presented. The plan's implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels.<>
{"title":"Standardization of test structure design","authors":"C. Weber","doi":"10.1109/ICMTS.1990.161730","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161730","url":null,"abstract":"A plan for standardization of test structure design based on a high-level information model is presented. The plan's implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116182165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161739
H. Yie, Yao Jiannan
Combined with a microelectronic test structure, an experimental design model building methodology is developed, where a self-consistent subdomain decomposition method is used to assure high accuracy and reasonable computation costs simultaneously. With some examples, the application of the derived regression model in IC performance prediction and optimum process design is discussed. A real-time statistical process analysis methodology that is incorporated with the experimental design method is presented. The applicability of the real-time statistical analysis methodology is demonstrated.<>
{"title":"Progress on model building and statistical analysis methodology of IC characteristics with process","authors":"H. Yie, Yao Jiannan","doi":"10.1109/ICMTS.1990.161739","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161739","url":null,"abstract":"Combined with a microelectronic test structure, an experimental design model building methodology is developed, where a self-consistent subdomain decomposition method is used to assure high accuracy and reasonable computation costs simultaneously. With some examples, the application of the derived regression model in IC performance prediction and optimum process design is discussed. A real-time statistical process analysis methodology that is incorporated with the experimental design method is presented. The applicability of the real-time statistical analysis methodology is demonstrated.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130507495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161753
J. Komori, Y. Takata, J. Mitsuhashi, N. Tsubouchi
A quick wafer-level evaluation technique for electromigration immunity is proposed. Noise measurements (1/f, 1/f/sup 2/) are performed on a test pattern with stress gradients under high current density up to 2*10/sup 7/ A/cm/sup 2/. Each of the measurements is completed within a few minutes. The temperature of the interconnections (200 degrees C for a current density of 2*10/sup 7/ A/cm/sup 2/) is low enough to evaluate electromigration. The effectiveness of the proposed technique has been verified by observing that the current noise spectrum is closely related to the void formation.<>
提出了一种晶圆级电迁移免疫快速评价技术。噪声测量(1/f, 1/f/sup 2/)在高电流密度下的应力梯度测试模式下进行，最高可达2*10/sup 7/ a /cm/sup 2/。每次测量都在几分钟内完成。互连的温度(200摄氏度的电流密度为2*10/sup 7/ a /cm/sup 2/)是低到足以评估电迁移。通过观察电流噪声谱与孔隙形成密切相关，验证了该技术的有效性
{"title":"A fast testing of electromigration immunity using noise measurement technique","authors":"J. Komori, Y. Takata, J. Mitsuhashi, N. Tsubouchi","doi":"10.1109/ICMTS.1990.161753","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161753","url":null,"abstract":"A quick wafer-level evaluation technique for electromigration immunity is proposed. Noise measurements (1/f, 1/f/sup 2/) are performed on a test pattern with stress gradients under high current density up to 2*10/sup 7/ A/cm/sup 2/. Each of the measurements is completed within a few minutes. The temperature of the interconnections (200 degrees C for a current density of 2*10/sup 7/ A/cm/sup 2/) is low enough to evaluate electromigration. The effectiveness of the proposed technique has been verified by observing that the current noise spectrum is closely related to the void formation.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130512960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-03-18DOI: 10.1109/ICMTS.1990.161748
Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu
The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<>
{"title":"Photoemission identification of emitter resistance for CMOS latch-up hysteresis","authors":"Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu","doi":"10.1109/ICMTS.1990.161748","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.161748","url":null,"abstract":"The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116585259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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