Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490943
Zhaoqing Chen
A receiver macro modeling method is proposed. It includes the Mpilog macro model and the filter-preamplifier model which consists of small signal model followed by the hyperbolic-tangent function nonlinear post-processing. By using the directional junction model, we make use of the Mpilog model for receiver input port DC and nonlinear reflection properties, and make use of the small-signal/hyperbolic-tangent model for the output port of the preamplifier. Each model works at its own condition without unwanted interfering to each other. The assembled receiver macro model can be used in packaging system transient simulations directly. A practical modeling procedure in detail is described in the paper. The comparison between the proposed model and the original transistor-level model are given to evaluate the accuracy and simulation speed. Several application examples are also shown as test cases including high-end server packaging system transient simulations taking into account the crosstalk from the adjacent aggressor channels.
{"title":"Receiver macro modeling including DC, filter, and preamplifier nonlinear properties for packaging system transient simulations","authors":"Zhaoqing Chen","doi":"10.1109/ECTC.2010.5490943","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490943","url":null,"abstract":"A receiver macro modeling method is proposed. It includes the Mpilog macro model and the filter-preamplifier model which consists of small signal model followed by the hyperbolic-tangent function nonlinear post-processing. By using the directional junction model, we make use of the Mpilog model for receiver input port DC and nonlinear reflection properties, and make use of the small-signal/hyperbolic-tangent model for the output port of the preamplifier. Each model works at its own condition without unwanted interfering to each other. The assembled receiver macro model can be used in packaging system transient simulations directly. A practical modeling procedure in detail is described in the paper. The comparison between the proposed model and the original transistor-level model are given to evaluate the accuracy and simulation speed. Several application examples are also shown as test cases including high-end server packaging system transient simulations taking into account the crosstalk from the adjacent aggressor channels.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116618050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490920
W. Woods, H. Ding, Guoan Wang, A. Joseph
On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.
{"title":"Novel on-chip Through-Silicon-Via Wilkinson power divider","authors":"W. Woods, H. Ding, Guoan Wang, A. Joseph","doi":"10.1109/ECTC.2010.5490920","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490920","url":null,"abstract":"On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490963
T. Sugimoto, Y. Hashimoto, K. Yamamoto, M. Kurihara, M. Oda, J. Sakai, H. Ono, T. Akagawa, K. Yashiki, H. Hatayama, N. Suzuki, M. Tsuji, I. Ogura, H. Kouta, K. Kurata
We have developed 12-channel × 20-Gbps optical transmitter/receiver modules with 9 × 14-mm footprints. To achieve stable optical coupling efficiency, we also developed a precise multi-chip mounting technique. The three dies of 4-channel vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD) arrays are mounted at the same time. The accuracy of the Z-axis can be controlled by monitoring the dies' positions for the optical reference plane. The coupling losses were less than 1.5 dB in the 12-channel transmitter/receiver modules. The standard deviations of the coupling losses were less than 1.0 dB in all samples. Error-free transmissions at a data rate of 20 Gbps were also demonstrated. A reliability test indicated that the modules are repairable and reliable.
{"title":"12-Channel × 20-Gbps on-board parallel optical modules using multi-chip visual alignment technique","authors":"T. Sugimoto, Y. Hashimoto, K. Yamamoto, M. Kurihara, M. Oda, J. Sakai, H. Ono, T. Akagawa, K. Yashiki, H. Hatayama, N. Suzuki, M. Tsuji, I. Ogura, H. Kouta, K. Kurata","doi":"10.1109/ECTC.2010.5490963","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490963","url":null,"abstract":"We have developed 12-channel × 20-Gbps optical transmitter/receiver modules with 9 × 14-mm footprints. To achieve stable optical coupling efficiency, we also developed a precise multi-chip mounting technique. The three dies of 4-channel vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD) arrays are mounted at the same time. The accuracy of the Z-axis can be controlled by monitoring the dies' positions for the optical reference plane. The coupling losses were less than 1.5 dB in the 12-channel transmitter/receiver modules. The standard deviations of the coupling losses were less than 1.0 dB in all samples. Error-free transmissions at a data rate of 20 Gbps were also demonstrated. A reliability test indicated that the modules are repairable and reliable.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128991946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490654
J. Agar, Katy J. Lin, Rongwei Zhang, J. Durden, K. Moon, C. Wong
Future electronics will undoubtedly require natural integration at the system, device and package level in the form of a functional, flexible package. Functional, flexible electronics expand the functionality of devices allowing morphological-electronic response for ergonomic and natural interfaces between the device and its surroundings. Recent technological successes have been able to fabricate functional, flexible electronics, however have all failed to develop a package capable of meeting the stringent cost, reliability and performance required of consumer electronics. We demonstrate the application of electrically conductive adhesive technology to produce low cost, flexible electronics without metallization. We have shown the capability of fabrication of highly conductive Poly(dimethlysiloxane) (PDMS) (ρ~7×10−4 Ω•cm) by incorporation of 80 wt% bimodal distribution of micron sized silver flakes. PDMS is both the ideal substrate and composite matrix material due to its unique properties; PDMS is optically transparent, viscoelastic, chemically and thermally stable, highly flexible, hydrophobic and can easily be molded with high resolution and aspect ratio. These unique properties of PDMS allow for high resolution molds to be prepared from photolithographically defined substrates. Screen printing of electrically conductive PDMS into these molds with micro-sized features creates a low cost, flexible electronic package. We have coined this package PDMS-in-PDMS. We show that PDMS ECA can be prepared by curing a novel formulation of PDMS at curing temperatures of 150 °C for 15 minutes. Upon curing, the ECA undergoes a transition from insulating to conductive. TMA results have shown that this transition is due to ECA shrinkage >20%. Furthermore, we show simultaneous conductivity and tensile strain measurements to show the electrical properties of PDMS ECA are unaffected by tensile strains of >40%. We show the feasibility of this technology to create low cost, flexible devices without the need for metallization.
{"title":"Novel PDMS(silicone)-in-PDMS(silicone): Low cost flexible electronics without metallization","authors":"J. Agar, Katy J. Lin, Rongwei Zhang, J. Durden, K. Moon, C. Wong","doi":"10.1109/ECTC.2010.5490654","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490654","url":null,"abstract":"Future electronics will undoubtedly require natural integration at the system, device and package level in the form of a functional, flexible package. Functional, flexible electronics expand the functionality of devices allowing morphological-electronic response for ergonomic and natural interfaces between the device and its surroundings. Recent technological successes have been able to fabricate functional, flexible electronics, however have all failed to develop a package capable of meeting the stringent cost, reliability and performance required of consumer electronics. We demonstrate the application of electrically conductive adhesive technology to produce low cost, flexible electronics without metallization. We have shown the capability of fabrication of highly conductive Poly(dimethlysiloxane) (PDMS) (ρ~7×10−4 Ω•cm) by incorporation of 80 wt% bimodal distribution of micron sized silver flakes. PDMS is both the ideal substrate and composite matrix material due to its unique properties; PDMS is optically transparent, viscoelastic, chemically and thermally stable, highly flexible, hydrophobic and can easily be molded with high resolution and aspect ratio. These unique properties of PDMS allow for high resolution molds to be prepared from photolithographically defined substrates. Screen printing of electrically conductive PDMS into these molds with micro-sized features creates a low cost, flexible electronic package. We have coined this package PDMS-in-PDMS. We show that PDMS ECA can be prepared by curing a novel formulation of PDMS at curing temperatures of 150 °C for 15 minutes. Upon curing, the ECA undergoes a transition from insulating to conductive. TMA results have shown that this transition is due to ECA shrinkage >20%. Furthermore, we show simultaneous conductivity and tensile strain measurements to show the electrical properties of PDMS ECA are unaffected by tensile strains of >40%. We show the feasibility of this technology to create low cost, flexible devices without the need for metallization.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490954
J. Kim, S. Seok, N. Rolland, P. Rolland
This paper reports on a simple wafer scale transfer technology for polymer-based zero-level packaging. By controlling the adhesive strength of the interface between the packaging material and the carrier wafer, the ablation process of carrier wafer is substituted with the mechanical separation of it. Surface modification technique using hydrophobic SAM is selected for the formation of an anti-adhesion layer. Prefabricated BCB packaging caps on the carrier wafer is wafer-level bonded with a Si substrate and released from the carrier wafer by mechanical detachment using a razor blade. In order to confirm the validity of the technique in RF applications, the insertion loss of BCB-encapsulated CPW lines is measured from DC to 70 GHz.
{"title":"A novel wafer level bonding/debonding technique using an anti-adhesion layer for polymer-based zero-level packaging of RF device","authors":"J. Kim, S. Seok, N. Rolland, P. Rolland","doi":"10.1109/ECTC.2010.5490954","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490954","url":null,"abstract":"This paper reports on a simple wafer scale transfer technology for polymer-based zero-level packaging. By controlling the adhesive strength of the interface between the packaging material and the carrier wafer, the ablation process of carrier wafer is substituted with the mechanical separation of it. Surface modification technique using hydrophobic SAM is selected for the formation of an anti-adhesion layer. Prefabricated BCB packaging caps on the carrier wafer is wafer-level bonded with a Si substrate and released from the carrier wafer by mechanical detachment using a razor blade. In order to confirm the validity of the technique in RF applications, the insertion loss of BCB-encapsulated CPW lines is measured from DC to 70 GHz.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490789
J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh
Recently, the application of Ag bonding wires in electronic devices has been attempted as alternative to Au bonding wires to reduce the material cost of Au. Nevertheless, Ag bonding wires have not been applied to devices due to interface corrosion problems between the Ag wire and Al pad during humidity reliability tests, such as the PCT (Pressure Cooker Test). As the technology for alloying Pd element in Ag wire has developed recently, the corrosive failure problem at the interface in the PCT has been improved significantly. This study examined the behavior of IMCs(intermetallic compounds) and interface corrosion between an Ag wire and Al metallization under humidity conditions (100%RH, 121'C). The chemical compositions of the Ag wires tested were pure Ag, Ag — 1wt%Pd and Ag-3%Pd. These wires are bonded to Al and noble metal(Au, Pd) metallization using a thermo-sonic bonder. The interfaces were characterized by FIB(Focused ion beam), HRTEM (High Resolution Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectroscopy) The findings show that, (1) the interfacial reliability between the Ag wire and Ag metallization was improved considerably. The interface corrosion was suppressed significantly as the Pd content was increased. (2) Ag wires on a noble metal(Au, Pd) pad have stable reliability in PCT.
{"title":"Pd effects on the reliability in the low cost Ag bonding wire","authors":"J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh","doi":"10.1109/ECTC.2010.5490789","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490789","url":null,"abstract":"Recently, the application of Ag bonding wires in electronic devices has been attempted as alternative to Au bonding wires to reduce the material cost of Au. Nevertheless, Ag bonding wires have not been applied to devices due to interface corrosion problems between the Ag wire and Al pad during humidity reliability tests, such as the PCT (Pressure Cooker Test). As the technology for alloying Pd element in Ag wire has developed recently, the corrosive failure problem at the interface in the PCT has been improved significantly. This study examined the behavior of IMCs(intermetallic compounds) and interface corrosion between an Ag wire and Al metallization under humidity conditions (100%RH, 121'C). The chemical compositions of the Ag wires tested were pure Ag, Ag — 1wt%Pd and Ag-3%Pd. These wires are bonded to Al and noble metal(Au, Pd) metallization using a thermo-sonic bonder. The interfaces were characterized by FIB(Focused ion beam), HRTEM (High Resolution Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectroscopy) The findings show that, (1) the interfacial reliability between the Ag wire and Ag metallization was improved considerably. The interface corrosion was suppressed significantly as the Pd content was increased. (2) Ag wires on a noble metal(Au, Pd) pad have stable reliability in PCT.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490674
S. Chung, Mi-Jin Kim
The reliability of Pb-free solder interconnect under drop impact was investigated. In this paper, solder ball pull and shear tests were introduced to assess the interconnect reliability since high speed pull and shear tests exhibit high strain rate deformation followed by brittle fracture of actual drop scenario. The design, material, and process parameters considered in this study are SR condition, Cu pad surface finish, and strain rate, respectively. The adhesion strength was measured and the failure mode was categorized in each test condition. Next, the maximum applied force in ball pull test was used for loading condition in finite element analysis to calculate the interfacial fracture toughness at the corresponding fracture location. The effect of parameters on interfacial reliability was shown by interfacial fracture toughness, and it was compared with the drop life of boardlevel reliability test to investigate the correlation. Finally, the applicability and limitation of ball pull/shear tests for replacing BLR test were discussed.
{"title":"Investigation of Pb-free solder interconnect under drop impact by ball pull and shear tests","authors":"S. Chung, Mi-Jin Kim","doi":"10.1109/ECTC.2010.5490674","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490674","url":null,"abstract":"The reliability of Pb-free solder interconnect under drop impact was investigated. In this paper, solder ball pull and shear tests were introduced to assess the interconnect reliability since high speed pull and shear tests exhibit high strain rate deformation followed by brittle fracture of actual drop scenario. The design, material, and process parameters considered in this study are SR condition, Cu pad surface finish, and strain rate, respectively. The adhesion strength was measured and the failure mode was categorized in each test condition. Next, the maximum applied force in ball pull test was used for loading condition in finite element analysis to calculate the interfacial fracture toughness at the corresponding fracture location. The effect of parameters on interfacial reliability was shown by interfacial fracture toughness, and it was compared with the drop life of boardlevel reliability test to investigate the correlation. Finally, the applicability and limitation of ball pull/shear tests for replacing BLR test were discussed.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123901992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490851
A. Agwai, I. Guven, E. Madenci
This study presents a comparison of extended finite elements (XFEM), cohesive zone model (CZM) and the peridynamic theory (PD). By comparisons against two experimental benchmark studies, the capability of these techniques to predict dynamic fracture is demonstrated through both qualitative and quantitative observations.
{"title":"Predicting crack initiation and propagation using XFEM, CZM and peridynamics: A comparative study","authors":"A. Agwai, I. Guven, E. Madenci","doi":"10.1109/ECTC.2010.5490851","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490851","url":null,"abstract":"This study presents a comparison of extended finite elements (XFEM), cohesive zone model (CZM) and the peridynamic theory (PD). By comparisons against two experimental benchmark studies, the capability of these techniques to predict dynamic fracture is demonstrated through both qualitative and quantitative observations.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121146331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490844
Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans
Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.
{"title":"Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics","authors":"Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans","doi":"10.1109/ECTC.2010.5490844","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490844","url":null,"abstract":"Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490885
S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn
In this paper we have provided analysis of carbon nanotube (CNT) based Through Silicon Vias (TSVs) for package interconnects. The package interconnects are fundamental bottlenecks to achieving high performance and reliability. We have provided electrical modeling and performed simulations on TSV with copper and carbon nanotubes. The results from the CNT-based TSVs were greatly superior to conventional vias with copper.
{"title":"Analysis of carbon nanotube based Through Silicon Vias","authors":"S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn","doi":"10.1109/ECTC.2010.5490885","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490885","url":null,"abstract":"In this paper we have provided analysis of carbon nanotube (CNT) based Through Silicon Vias (TSVs) for package interconnects. The package interconnects are fundamental bottlenecks to achieving high performance and reliability. We have provided electrical modeling and performed simulations on TSV with copper and carbon nanotubes. The results from the CNT-based TSVs were greatly superior to conventional vias with copper.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129376509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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