Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490649
Minghui Sun, Zhiyong Xiao, Y. Chai, Yuan Li, P. Chan
In this study, we investigated the inductance properties of as-grown horizontal MWNT arrays with different length and width combinations. Statistical data processing was employed to explore the relationship between kinetic inductance and dimension of CNT arrays. We have experimentally confirmed that kinetic inductance forward scales with the length of CNTs and reversely scales with the number of CNTs in parallel. This work provides a systematic experimental study of CNT kinetic inductance and provides useful data for further investigating the possibility of using CNT-based inductors in RFIC.
{"title":"Inductance properties of silicon-in-grown horizontal carbon nanotubes","authors":"Minghui Sun, Zhiyong Xiao, Y. Chai, Yuan Li, P. Chan","doi":"10.1109/ECTC.2010.5490649","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490649","url":null,"abstract":"In this study, we investigated the inductance properties of as-grown horizontal MWNT arrays with different length and width combinations. Statistical data processing was employed to explore the relationship between kinetic inductance and dimension of CNT arrays. We have experimentally confirmed that kinetic inductance forward scales with the length of CNTs and reversely scales with the number of CNTs in parallel. This work provides a systematic experimental study of CNT kinetic inductance and provides useful data for further investigating the possibility of using CNT-based inductors in RFIC.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":" 41","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113947133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490696
J. Hsu, Sam Yang, Wei-Da Guo, R. Lee, Tung-Yang Chen
A systematic design method by using channel factorial design is proposed to meet the low-cost DDRII system solution with quad-flat-package (QFP) and two-layer printed circuit board. The channel characteristic was analyzed through one numerical transformation between time and frequency domains to figure out the time-variant waveform on the corresponding spectrum for potential radiated emission issues. By using the factorial analysis, the critical electrical parameters could be clearly list down and optimized in the pre-design analysis. This methodology could be usefully applied in the electrical physical constraint setup and budget control on the design phase. We can make a right compromise among the different design electrical factors with the corresponding penalties to robustly function up to DDRII 800Mbps in this low-cost system.
{"title":"High-speed parallel interface implementation with low-cost system solution by using signal integrity factorial design","authors":"J. Hsu, Sam Yang, Wei-Da Guo, R. Lee, Tung-Yang Chen","doi":"10.1109/ECTC.2010.5490696","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490696","url":null,"abstract":"A systematic design method by using channel factorial design is proposed to meet the low-cost DDRII system solution with quad-flat-package (QFP) and two-layer printed circuit board. The channel characteristic was analyzed through one numerical transformation between time and frequency domains to figure out the time-variant waveform on the corresponding spectrum for potential radiated emission issues. By using the factorial analysis, the critical electrical parameters could be clearly list down and optimized in the pre-design analysis. This methodology could be usefully applied in the electrical physical constraint setup and budget control on the design phase. We can make a right compromise among the different design electrical factors with the corresponding penalties to robustly function up to DDRII 800Mbps in this low-cost system.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126222462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490937
Kiwon Lee, K. Paik
In this study, in order to improve the electrical properties and the reliability of ACF joints, we propose the simultaneous fluxless solder joining and adhesive bonding technology. This technology utilizes fluxless soldering within an adhesive matrix on metal electrodes combined with room temperature ultrasonic (U/S) ACF bonding technique advantages. According to the experimental results, the temperature of the solder ACF joints showed rapid heating rates up to 400 °C/s and peak values above 250°C by applying ultrasonic vibration. The ACF temperature could be precisely controlled ranging from 75°C to 260°C by adjusting U/S vibration amplitudes from 4 um to 13 um. At above the melting temperatures of solder particles, U/S bonded solder ACF joints showed higher than 80% soldering ratios and no void formation with optimized U/S parameters. The soldering ratio at the solder ACF joints increased as the ACF temperature increased and it was presumably due to the viscosity decrease of the ACF adhesive matrix. On the other hand, thermocompression (T/C) bonded solder ACF joints showed poor soldering ratios lower than 30% and severe void formation at above 200°C. At the same time, U/S bonded solder ACF joints showed 30% reduced electrical contact resistances and twice better reliability in an unbiased autoclave test (121°C, 2 atm, 100%RH) compared with conventional ACF joints. Significance of this result is that fluxless solder joining and adhesive bonding can be simultaneously achieved within 5 seconds by using solder ACFs combined with the room temperature U/S bonding technique.
{"title":"High power and fine pitch assembly using solder Anisotropic Conductive Films (ACFs) combined with ultrasonic bonding technique","authors":"Kiwon Lee, K. Paik","doi":"10.1109/ECTC.2010.5490937","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490937","url":null,"abstract":"In this study, in order to improve the electrical properties and the reliability of ACF joints, we propose the simultaneous fluxless solder joining and adhesive bonding technology. This technology utilizes fluxless soldering within an adhesive matrix on metal electrodes combined with room temperature ultrasonic (U/S) ACF bonding technique advantages. According to the experimental results, the temperature of the solder ACF joints showed rapid heating rates up to 400 °C/s and peak values above 250°C by applying ultrasonic vibration. The ACF temperature could be precisely controlled ranging from 75°C to 260°C by adjusting U/S vibration amplitudes from 4 um to 13 um. At above the melting temperatures of solder particles, U/S bonded solder ACF joints showed higher than 80% soldering ratios and no void formation with optimized U/S parameters. The soldering ratio at the solder ACF joints increased as the ACF temperature increased and it was presumably due to the viscosity decrease of the ACF adhesive matrix. On the other hand, thermocompression (T/C) bonded solder ACF joints showed poor soldering ratios lower than 30% and severe void formation at above 200°C. At the same time, U/S bonded solder ACF joints showed 30% reduced electrical contact resistances and twice better reliability in an unbiased autoclave test (121°C, 2 atm, 100%RH) compared with conventional ACF joints. Significance of this result is that fluxless solder joining and adhesive bonding can be simultaneously achieved within 5 seconds by using solder ACFs combined with the room temperature U/S bonding technique.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490767
P. Su, Boaz Khan, Min Ding
Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.
{"title":"An evaluation of die crack risk of over-molded packages due to external impact","authors":"P. Su, Boaz Khan, Min Ding","doi":"10.1109/ECTC.2010.5490767","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490767","url":null,"abstract":"Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490954
J. Kim, S. Seok, N. Rolland, P. Rolland
This paper reports on a simple wafer scale transfer technology for polymer-based zero-level packaging. By controlling the adhesive strength of the interface between the packaging material and the carrier wafer, the ablation process of carrier wafer is substituted with the mechanical separation of it. Surface modification technique using hydrophobic SAM is selected for the formation of an anti-adhesion layer. Prefabricated BCB packaging caps on the carrier wafer is wafer-level bonded with a Si substrate and released from the carrier wafer by mechanical detachment using a razor blade. In order to confirm the validity of the technique in RF applications, the insertion loss of BCB-encapsulated CPW lines is measured from DC to 70 GHz.
{"title":"A novel wafer level bonding/debonding technique using an anti-adhesion layer for polymer-based zero-level packaging of RF device","authors":"J. Kim, S. Seok, N. Rolland, P. Rolland","doi":"10.1109/ECTC.2010.5490954","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490954","url":null,"abstract":"This paper reports on a simple wafer scale transfer technology for polymer-based zero-level packaging. By controlling the adhesive strength of the interface between the packaging material and the carrier wafer, the ablation process of carrier wafer is substituted with the mechanical separation of it. Surface modification technique using hydrophobic SAM is selected for the formation of an anti-adhesion layer. Prefabricated BCB packaging caps on the carrier wafer is wafer-level bonded with a Si substrate and released from the carrier wafer by mechanical detachment using a razor blade. In order to confirm the validity of the technique in RF applications, the insertion loss of BCB-encapsulated CPW lines is measured from DC to 70 GHz.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490789
J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh
Recently, the application of Ag bonding wires in electronic devices has been attempted as alternative to Au bonding wires to reduce the material cost of Au. Nevertheless, Ag bonding wires have not been applied to devices due to interface corrosion problems between the Ag wire and Al pad during humidity reliability tests, such as the PCT (Pressure Cooker Test). As the technology for alloying Pd element in Ag wire has developed recently, the corrosive failure problem at the interface in the PCT has been improved significantly. This study examined the behavior of IMCs(intermetallic compounds) and interface corrosion between an Ag wire and Al metallization under humidity conditions (100%RH, 121'C). The chemical compositions of the Ag wires tested were pure Ag, Ag — 1wt%Pd and Ag-3%Pd. These wires are bonded to Al and noble metal(Au, Pd) metallization using a thermo-sonic bonder. The interfaces were characterized by FIB(Focused ion beam), HRTEM (High Resolution Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectroscopy) The findings show that, (1) the interfacial reliability between the Ag wire and Ag metallization was improved considerably. The interface corrosion was suppressed significantly as the Pd content was increased. (2) Ag wires on a noble metal(Au, Pd) pad have stable reliability in PCT.
{"title":"Pd effects on the reliability in the low cost Ag bonding wire","authors":"J. Cho, Kyeong-Ah Yoo, S. Hong, J. Moon, Yong-Je Lee, Wongil Han, Hanki Park, S. Ha, Seong-Bum Son, S. Kang, K. Oh","doi":"10.1109/ECTC.2010.5490789","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490789","url":null,"abstract":"Recently, the application of Ag bonding wires in electronic devices has been attempted as alternative to Au bonding wires to reduce the material cost of Au. Nevertheless, Ag bonding wires have not been applied to devices due to interface corrosion problems between the Ag wire and Al pad during humidity reliability tests, such as the PCT (Pressure Cooker Test). As the technology for alloying Pd element in Ag wire has developed recently, the corrosive failure problem at the interface in the PCT has been improved significantly. This study examined the behavior of IMCs(intermetallic compounds) and interface corrosion between an Ag wire and Al metallization under humidity conditions (100%RH, 121'C). The chemical compositions of the Ag wires tested were pure Ag, Ag — 1wt%Pd and Ag-3%Pd. These wires are bonded to Al and noble metal(Au, Pd) metallization using a thermo-sonic bonder. The interfaces were characterized by FIB(Focused ion beam), HRTEM (High Resolution Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectroscopy) The findings show that, (1) the interfacial reliability between the Ag wire and Ag metallization was improved considerably. The interface corrosion was suppressed significantly as the Pd content was increased. (2) Ag wires on a noble metal(Au, Pd) pad have stable reliability in PCT.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490674
S. Chung, Mi-Jin Kim
The reliability of Pb-free solder interconnect under drop impact was investigated. In this paper, solder ball pull and shear tests were introduced to assess the interconnect reliability since high speed pull and shear tests exhibit high strain rate deformation followed by brittle fracture of actual drop scenario. The design, material, and process parameters considered in this study are SR condition, Cu pad surface finish, and strain rate, respectively. The adhesion strength was measured and the failure mode was categorized in each test condition. Next, the maximum applied force in ball pull test was used for loading condition in finite element analysis to calculate the interfacial fracture toughness at the corresponding fracture location. The effect of parameters on interfacial reliability was shown by interfacial fracture toughness, and it was compared with the drop life of boardlevel reliability test to investigate the correlation. Finally, the applicability and limitation of ball pull/shear tests for replacing BLR test were discussed.
{"title":"Investigation of Pb-free solder interconnect under drop impact by ball pull and shear tests","authors":"S. Chung, Mi-Jin Kim","doi":"10.1109/ECTC.2010.5490674","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490674","url":null,"abstract":"The reliability of Pb-free solder interconnect under drop impact was investigated. In this paper, solder ball pull and shear tests were introduced to assess the interconnect reliability since high speed pull and shear tests exhibit high strain rate deformation followed by brittle fracture of actual drop scenario. The design, material, and process parameters considered in this study are SR condition, Cu pad surface finish, and strain rate, respectively. The adhesion strength was measured and the failure mode was categorized in each test condition. Next, the maximum applied force in ball pull test was used for loading condition in finite element analysis to calculate the interfacial fracture toughness at the corresponding fracture location. The effect of parameters on interfacial reliability was shown by interfacial fracture toughness, and it was compared with the drop life of boardlevel reliability test to investigate the correlation. Finally, the applicability and limitation of ball pull/shear tests for replacing BLR test were discussed.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123901992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490851
A. Agwai, I. Guven, E. Madenci
This study presents a comparison of extended finite elements (XFEM), cohesive zone model (CZM) and the peridynamic theory (PD). By comparisons against two experimental benchmark studies, the capability of these techniques to predict dynamic fracture is demonstrated through both qualitative and quantitative observations.
{"title":"Predicting crack initiation and propagation using XFEM, CZM and peridynamics: A comparative study","authors":"A. Agwai, I. Guven, E. Madenci","doi":"10.1109/ECTC.2010.5490851","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490851","url":null,"abstract":"This study presents a comparison of extended finite elements (XFEM), cohesive zone model (CZM) and the peridynamic theory (PD). By comparisons against two experimental benchmark studies, the capability of these techniques to predict dynamic fracture is demonstrated through both qualitative and quantitative observations.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121146331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490844
Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans
Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.
{"title":"Sensitivity analysis of Pb free reflow profile parameters toward flip chip on silicon assembly yield, reliability and intermetallic compound characteristics","authors":"Zhaozhi Li, Sangil Lee, B. Lewis, P. Houston, D. Baldwin, G. Stout, T. Tessier, John L. Evans","doi":"10.1109/ECTC.2010.5490844","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490844","url":null,"abstract":"Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490885
S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn
In this paper we have provided analysis of carbon nanotube (CNT) based Through Silicon Vias (TSVs) for package interconnects. The package interconnects are fundamental bottlenecks to achieving high performance and reliability. We have provided electrical modeling and performed simulations on TSV with copper and carbon nanotubes. The results from the CNT-based TSVs were greatly superior to conventional vias with copper.
{"title":"Analysis of carbon nanotube based Through Silicon Vias","authors":"S. Kannan, Anurag Gupta, Bruce C. Kim, F. Mohammed, Byoungchul Ahn","doi":"10.1109/ECTC.2010.5490885","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490885","url":null,"abstract":"In this paper we have provided analysis of carbon nanotube (CNT) based Through Silicon Vias (TSVs) for package interconnects. The package interconnects are fundamental bottlenecks to achieving high performance and reliability. We have provided electrical modeling and performed simulations on TSV with copper and carbon nanotubes. The results from the CNT-based TSVs were greatly superior to conventional vias with copper.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129376509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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