Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490683
Seunghwan Kim, Kiwon Lee, K. Paik
In this study, the effects of vertical ultrasonic (VUS) bonding parameters such as vibration amplitudes and bonding pressures were investigated and optimized in terms of thermal deformation of TSP polymer substrates, electrical continuity, and pull adhesion strength of anisotropic conductive adhesive (ACA) joints. And the reliability of VUS bonded TSP ACA joints were evaluated at various test conditions. As the vertical ultrasonic vibration was applied, ACA temperatures rapidly increased due to the spontaneous heat generation in the ACA itself and surrounding polymers. The ultrasonic vibration showed significant effects on the peak temperature of the ACA layers, and the bonding pressure affected the heating rates. By adjusting both ultrasonic vibration and bonding pressure, the ACA temperature could be successfully controlled. In terms of thermal deformation, VUS bonding showed no severe thermal deformation of TSPs up to 120°C which is much higher than the Tg of polyethylene terephthalates (PETs) which are the base material of TSPs. In terms of electrical continuity of the ACA joints, VUS bonded TSPs showed stable electrical resistances at 2 MPa bonding pressures, and there were no significant effects of vibration amplitudes and bonding times on contact resistances. At the same time, VUS bonded TSPs showed strong adhesion at the ACA joints with 1 second bonding time at 7.5 um vibration amplitude and 2 MPa bonding pressure. During the FPCB pull test, VUS bonded TSPs showed higher than 3 kgf pull strengths. Therefore, VUS bonding parameters were optimized at 7.5 um vibration amplitude, 2 MPa bonding pressure, and 1 second bonding time in terms of PET thermal deformation, electrical continuity and pull adhesion strength of the TSP ACA joints. With the optimized parameters, various reliability tests were conducted such as thermal shock test, salt spray test, high temperature/high humidity test, high temperature storage test and writing test. After each test, the VUS bonded TSPs showed no significant changes in electrical resistance compared with those of thermo-compression bonding. As a summary, the VUS method can be successfully used in TSPs assembly with no thermal damages, higher speed assembly and good reliability.
{"title":"High speed touch screen panels (TSPs) assembly using anisotropic conductive adhesives (ACAs) vertical ultrasonic bonding method","authors":"Seunghwan Kim, Kiwon Lee, K. Paik","doi":"10.1109/ECTC.2010.5490683","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490683","url":null,"abstract":"In this study, the effects of vertical ultrasonic (VUS) bonding parameters such as vibration amplitudes and bonding pressures were investigated and optimized in terms of thermal deformation of TSP polymer substrates, electrical continuity, and pull adhesion strength of anisotropic conductive adhesive (ACA) joints. And the reliability of VUS bonded TSP ACA joints were evaluated at various test conditions. As the vertical ultrasonic vibration was applied, ACA temperatures rapidly increased due to the spontaneous heat generation in the ACA itself and surrounding polymers. The ultrasonic vibration showed significant effects on the peak temperature of the ACA layers, and the bonding pressure affected the heating rates. By adjusting both ultrasonic vibration and bonding pressure, the ACA temperature could be successfully controlled. In terms of thermal deformation, VUS bonding showed no severe thermal deformation of TSPs up to 120°C which is much higher than the Tg of polyethylene terephthalates (PETs) which are the base material of TSPs. In terms of electrical continuity of the ACA joints, VUS bonded TSPs showed stable electrical resistances at 2 MPa bonding pressures, and there were no significant effects of vibration amplitudes and bonding times on contact resistances. At the same time, VUS bonded TSPs showed strong adhesion at the ACA joints with 1 second bonding time at 7.5 um vibration amplitude and 2 MPa bonding pressure. During the FPCB pull test, VUS bonded TSPs showed higher than 3 kgf pull strengths. Therefore, VUS bonding parameters were optimized at 7.5 um vibration amplitude, 2 MPa bonding pressure, and 1 second bonding time in terms of PET thermal deformation, electrical continuity and pull adhesion strength of the TSP ACA joints. With the optimized parameters, various reliability tests were conducted such as thermal shock test, salt spray test, high temperature/high humidity test, high temperature storage test and writing test. After each test, the VUS bonded TSPs showed no significant changes in electrical resistance compared with those of thermo-compression bonding. As a summary, the VUS method can be successfully used in TSPs assembly with no thermal damages, higher speed assembly and good reliability.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490966
F. Doany, C. Schow, Benjamin G. Lee, A. Rylyakov, C. Jahnes, Y. Kwark, C. Baks, D. Kuchta, J. Kash
A novel, compact 48-channel optical transceiver module has been designed and fabricated. At the heart of the assembly is a “holey” Optochip — a single-chip CMOS transceiver integrated circuit (IC) with 24 receiver and 24 laser driver circuits each with a corresponding through-substrate optical via (hole). The holes enable 24-channel 850-nm VCSEL and photodiode (PD) arrays to be directly flipchip soldered to the CMOS IC with substrate-side optical I/O through the otherwise absorbing bulk silicon substrate. This feature of the holey Optochip not only facilitates direct fiber-coupling to a standard 4 × 12 MMF (multimode fiber) array through a 2-lens optical system, but also maximizes highspeed performance through the close integration of the VCSEL and PD devices with the CMOS amplifier circuits. Furthermore, the holey Optochip is directly compatible with current mass-produced 850-nm VCSELs and photodiodes. These Optochips were packaged into complete modules by flip-chip soldering to high-density, high-speed organic carriers using a process very similar to standard C4 soldering used for electrical ICs. The full assembly of the Optomodule involves further attachment to a pin grid array pluggable connector. Electrical characterization of Optomodules plugged into a test circuit board incorporating the socket half of the connector was carried out and dc electrical characterization showed fully operational 24 transmitter (TX) + 24 receiver (RX) Optomodules with uniform performance for all devices within the module. High-speed characterization of all 48-channels (ch) showed good performance up to 12.5 Gb/s/ch. At 12.5Gb/s/ch, an aggregate data rate 300 Gb/s TX + 300 Gb/s RX is provided by the holey Optomodule.
{"title":"Dense 24 TX + 24 RX fiber-coupled optical module based on a holey CMOS transceiver IC","authors":"F. Doany, C. Schow, Benjamin G. Lee, A. Rylyakov, C. Jahnes, Y. Kwark, C. Baks, D. Kuchta, J. Kash","doi":"10.1109/ECTC.2010.5490966","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490966","url":null,"abstract":"A novel, compact 48-channel optical transceiver module has been designed and fabricated. At the heart of the assembly is a “holey” Optochip — a single-chip CMOS transceiver integrated circuit (IC) with 24 receiver and 24 laser driver circuits each with a corresponding through-substrate optical via (hole). The holes enable 24-channel 850-nm VCSEL and photodiode (PD) arrays to be directly flipchip soldered to the CMOS IC with substrate-side optical I/O through the otherwise absorbing bulk silicon substrate. This feature of the holey Optochip not only facilitates direct fiber-coupling to a standard 4 × 12 MMF (multimode fiber) array through a 2-lens optical system, but also maximizes highspeed performance through the close integration of the VCSEL and PD devices with the CMOS amplifier circuits. Furthermore, the holey Optochip is directly compatible with current mass-produced 850-nm VCSELs and photodiodes. These Optochips were packaged into complete modules by flip-chip soldering to high-density, high-speed organic carriers using a process very similar to standard C4 soldering used for electrical ICs. The full assembly of the Optomodule involves further attachment to a pin grid array pluggable connector. Electrical characterization of Optomodules plugged into a test circuit board incorporating the socket half of the connector was carried out and dc electrical characterization showed fully operational 24 transmitter (TX) + 24 receiver (RX) Optomodules with uniform performance for all devices within the module. High-speed characterization of all 48-channels (ch) showed good performance up to 12.5 Gb/s/ch. At 12.5Gb/s/ch, an aggregate data rate 300 Gb/s TX + 300 Gb/s RX is provided by the holey Optomodule.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123255583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490911
R. Das, F. Egitto, B. Wilson, M. Poliks, V. Markovich
Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Flexibility decreased with increasing number of metal layers. The flexibility of the various flexes was characterized by roll diameter and bend angle. Flex substrates exhibited roll diameter with polyimide dielectric as low as 180 mils for 2 metal layers, and as high as 1300 mils for 6 metal layers. Similarly, bending for 12 metal layers flex with thin and thick dielectric were <1 inch and >1 inch, respectively. Reliability of the rigid-flex was ascertained by IR-reflow, thermal cycling, pressure cooker test (PCT), and solder shock. There was no delamination for Resin coated copper (rigid)-polyimide (flex) samples after IR-reflow, PCT, and solder shock. The paper also describes a novel approach for the fabrication of flexible electronics on PDMS substrates. It was found that with increasing thickness, the flexibility of the polydimethylsiloxane (PDMS) based substrate decreased less due to stretching property of PDMS. The present process evaluates the fabrication of PDMS substrates using different circuit lines and spaces.
{"title":"Development of rigid-flex and multilayer flex for electronic packaging","authors":"R. Das, F. Egitto, B. Wilson, M. Poliks, V. Markovich","doi":"10.1109/ECTC.2010.5490911","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490911","url":null,"abstract":"Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Flexibility decreased with increasing number of metal layers. The flexibility of the various flexes was characterized by roll diameter and bend angle. Flex substrates exhibited roll diameter with polyimide dielectric as low as 180 mils for 2 metal layers, and as high as 1300 mils for 6 metal layers. Similarly, bending for 12 metal layers flex with thin and thick dielectric were <1 inch and >1 inch, respectively. Reliability of the rigid-flex was ascertained by IR-reflow, thermal cycling, pressure cooker test (PCT), and solder shock. There was no delamination for Resin coated copper (rigid)-polyimide (flex) samples after IR-reflow, PCT, and solder shock. The paper also describes a novel approach for the fabrication of flexible electronics on PDMS substrates. It was found that with increasing thickness, the flexibility of the polydimethylsiloxane (PDMS) based substrate decreased less due to stretching property of PDMS. The present process evaluates the fabrication of PDMS substrates using different circuit lines and spaces.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490751
M. Töpper, T. Fischer, T. Baumgartner, H. Reichl
Polymers are a key building block for all WLP and related technologies like IPD (integrated passives devices) and 3D-SiP (system in Package). A couple of different classes of photo-sensitive polymeric materials are available for the integration, for example: Polyimide (PI), Polybenzoxazole (PBO), Benzocyclobuten (BCB), Silicones, Acrylates and Epoxy. A list of commercially available polymers will be compared in this paper with the focus of processing, material properties and reliability. Curing and the resulting shrinkage play an important role due to temperature sensitive devices and the topography of the metallization which have to be passivated. Test structures have been designed to measure planarization with respect to different feature sizes. In addition Cu compatibility is very important to polymer processing to avoid Cu migration. The mechanical properties have a strong influence on the reliability of non-underfilled WLP. There are different failure modes using different polymers for WLP on FR4 boards. Most important material properties are elongation to break and tensile strength. This is much less important for WLP if an underfiller is used.
{"title":"A comparison of thin film polymers for Wafer Level Packaging","authors":"M. Töpper, T. Fischer, T. Baumgartner, H. Reichl","doi":"10.1109/ECTC.2010.5490751","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490751","url":null,"abstract":"Polymers are a key building block for all WLP and related technologies like IPD (integrated passives devices) and 3D-SiP (system in Package). A couple of different classes of photo-sensitive polymeric materials are available for the integration, for example: Polyimide (PI), Polybenzoxazole (PBO), Benzocyclobuten (BCB), Silicones, Acrylates and Epoxy. A list of commercially available polymers will be compared in this paper with the focus of processing, material properties and reliability. Curing and the resulting shrinkage play an important role due to temperature sensitive devices and the topography of the metallization which have to be passivated. Test structures have been designed to measure planarization with respect to different feature sizes. In addition Cu compatibility is very important to polymer processing to avoid Cu migration. The mechanical properties have a strong influence on the reliability of non-underfilled WLP. There are different failure modes using different polymers for WLP on FR4 boards. Most important material properties are elongation to break and tensile strength. This is much less important for WLP if an underfiller is used.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490850
Jian Wen, V. Sarihan, B. Myers, Gary Li
Micro-electro-mechanical systems (MEMS) packaging is becoming increasingly critical and plays a major role in the successful commercialization of MEMS product. The packaging system should eable the MEMS perform the sensing function and at the same time protect it from the environmental disturbance, and help improve product quality to the sub-ppm level. One of our accelerometers in an SOIC package experienced a low ppm occurrence of device fracture. This MEMS package is unique in that the package has to maintain a certain resonance frequency to protect the transducer from sticking or clipping. At the same time, the package has to deliver a reliable and intact transducer with no cracking or output offset. A multidisciplinary approach inclusive of vibration analysis, electrical response determination, stress analysis, and fracture mechanics was used to determine the appropriate die attach material to completely resolve the device fracture issue.
{"title":"A multidisciplinary approach for effective packaging of MEMS accelerometer","authors":"Jian Wen, V. Sarihan, B. Myers, Gary Li","doi":"10.1109/ECTC.2010.5490850","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490850","url":null,"abstract":"Micro-electro-mechanical systems (MEMS) packaging is becoming increasingly critical and plays a major role in the successful commercialization of MEMS product. The packaging system should eable the MEMS perform the sensing function and at the same time protect it from the environmental disturbance, and help improve product quality to the sub-ppm level. One of our accelerometers in an SOIC package experienced a low ppm occurrence of device fracture. This MEMS package is unique in that the package has to maintain a certain resonance frequency to protect the transducer from sticking or clipping. At the same time, the package has to deliver a reliable and intact transducer with no cracking or output offset. A multidisciplinary approach inclusive of vibration analysis, electrical response determination, stress analysis, and fracture mechanics was used to determine the appropriate die attach material to completely resolve the device fracture issue.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121519191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490727
B. Smith, P. Kwok, J. Thompson, A. Mueller, L. Rácz
We examine the thermomechanical tradeoffs in a novel technology for high density interconnect (HDI) substrates. Fabricated from silicon (Si) wafers with planar cavities of highly-filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module fabrication, and operation. We show that improvements in junction-to-ambient sinking offset the heat density increase in such systems and low expansion encapsulants prevent failure during cure. We employ finite element modeling and materials testing to show the effect of wafer design and material selection on the stresses in the module.
{"title":"Demonstration of a novel hybrid silicon-resin high density interconnect (HDI) substrate","authors":"B. Smith, P. Kwok, J. Thompson, A. Mueller, L. Rácz","doi":"10.1109/ECTC.2010.5490727","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490727","url":null,"abstract":"We examine the thermomechanical tradeoffs in a novel technology for high density interconnect (HDI) substrates. Fabricated from silicon (Si) wafers with planar cavities of highly-filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module fabrication, and operation. We show that improvements in junction-to-ambient sinking offset the heat density increase in such systems and low expansion encapsulants prevent failure during cure. We employ finite element modeling and materials testing to show the effect of wafer design and material selection on the stresses in the module.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"491 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122750441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490708
K. Honda, T. Enomoto, A. Nagai, N. Takano
We have developed a novel NCF (Non Conductive Film) which can be applied to the wafer lamination process and shows the excellent bondability & reliability. For lamination processability, we improved the transparency of NCF in order to recognize the dicing pattern or alignment marks on wafer through NCF. As a result, NCF-laminated wafer can be diced simultaneously and smoothly. For the bondability, the use of the high heat-resistant components and the optimization of the hardenability and viscosity made it possible to form the excellent bonding part and fill the narrow gap between chip & substrate without voids even at the high temperature condition (>300 degC for 1s) of Au-Sn eutectic bonding. For the reliability, we found that a kind of antioxidant prevented remarkably the electrochemical migration at finer pitch wiring and we confirmed the good electronic insulation property up to 25 μm pitch. Furthermore, the addition of the flux component into NCF enabled Cu-solder bonding. From these features, this NCF is expected to be a promising material for the high density electronic packages including 3D package with TSV (Through Silicon Via) [1–3].
{"title":"NCF for wafer lamination process in higher density electronic packages","authors":"K. Honda, T. Enomoto, A. Nagai, N. Takano","doi":"10.1109/ECTC.2010.5490708","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490708","url":null,"abstract":"We have developed a novel NCF (Non Conductive Film) which can be applied to the wafer lamination process and shows the excellent bondability & reliability. For lamination processability, we improved the transparency of NCF in order to recognize the dicing pattern or alignment marks on wafer through NCF. As a result, NCF-laminated wafer can be diced simultaneously and smoothly. For the bondability, the use of the high heat-resistant components and the optimization of the hardenability and viscosity made it possible to form the excellent bonding part and fill the narrow gap between chip & substrate without voids even at the high temperature condition (>300 degC for 1s) of Au-Sn eutectic bonding. For the reliability, we found that a kind of antioxidant prevented remarkably the electrochemical migration at finer pitch wiring and we confirmed the good electronic insulation property up to 25 μm pitch. Furthermore, the addition of the flux component into NCF enabled Cu-solder bonding. From these features, this NCF is expected to be a promising material for the high density electronic packages including 3D package with TSV (Through Silicon Via) [1–3].","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"3 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490763
J. Hejase, P. Paladhi, P. Chahal
This paper will examine a new side to packaging: Terahertz (THz) Packaging. The goal of this paper is three fold: 1) characterizing dielectric materials for THz packaging applications; 2) Using these materials in the fabrication of THz passives (integrated and quasi-optical); and 3) Demonstrating non-destructive evaluation of packages using THz. In this manuscript, detailed characteristics of dielectric packaging materials in the THz spectral region are presented along with the theory used for the characterization procedure. THz non destructive evaluation (NDE) of electronics packages is observed in the form of delamination thickness detection and moisture content studies. Using the materials characterized, a planar THz power splitter and a quasi-optical THz bandstop interference filter are demonstrated. Furthermore, the power splitter is used as a THz microfluidic sensor.
{"title":"Terahertz packaging: Study of substrates for novel component designs","authors":"J. Hejase, P. Paladhi, P. Chahal","doi":"10.1109/ECTC.2010.5490763","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490763","url":null,"abstract":"This paper will examine a new side to packaging: Terahertz (THz) Packaging. The goal of this paper is three fold: 1) characterizing dielectric materials for THz packaging applications; 2) Using these materials in the fabrication of THz passives (integrated and quasi-optical); and 3) Demonstrating non-destructive evaluation of packages using THz. In this manuscript, detailed characteristics of dielectric packaging materials in the THz spectral region are presented along with the theory used for the characterization procedure. THz non destructive evaluation (NDE) of electronics packages is observed in the form of delamination thickness detection and moisture content studies. Using the materials characterized, a planar THz power splitter and a quasi-optical THz bandstop interference filter are demonstrated. Furthermore, the power splitter is used as a THz microfluidic sensor.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490922
Rui Li, T. Lim, S. W. Ho, Y. Xiong, D. Pinjala
This paper presents the design of two types of wideband bandpass filters with different bandwidths for millimeter-wave D-band applications. The proposed filters are implemented on a three-layer structure deposited on a 400-µm silicon (Si) bulk with benzocyclobutene (BCB) as the substrate. The characteristics of the basic structures for these two types of bandpass filters, a square ring resonator and a stub-loaded multiple-mode resonator (MMR), are studied. The bandpass filters are implemented and measured, and the measurement results agree with the simulations well and exhibit bandpass filtering responses at 134.3 GHz and 132.8 GHz, with fractional bandwidths of 25.7% and 34.3%, respectively.
{"title":"Design of wideband bandpass filters using Si-BCB technology for millimeter-wave applications","authors":"Rui Li, T. Lim, S. W. Ho, Y. Xiong, D. Pinjala","doi":"10.1109/ECTC.2010.5490922","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490922","url":null,"abstract":"This paper presents the design of two types of wideband bandpass filters with different bandwidths for millimeter-wave D-band applications. The proposed filters are implemented on a three-layer structure deposited on a 400-µm silicon (Si) bulk with benzocyclobutene (BCB) as the substrate. The characteristics of the basic structures for these two types of bandpass filters, a square ring resonator and a stub-loaded multiple-mode resonator (MMR), are studied. The bandpass filters are implemented and measured, and the measurement results agree with the simulations well and exhibit bandpass filtering responses at 134.3 GHz and 132.8 GHz, with fractional bandwidths of 25.7% and 34.3%, respectively.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116619971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490896
P. Sarobol, A. Pedigo, J. Blendell, C. Handwerker, P. Su, Li Li, J. Xue
For electroplated Sn and Sn alloy finishes, one of the reliability concerns remains the risk of whisker growth. Results from recent work have suggested that whiskers are most likely to form in regions of the films where high stress or a stress gradient exists. If strain/stress distribution information can be collected at a grain-by-grain level, correlations between such information and the propensity of whisker growth can be further understood. In this work, we utilized a highly focused X-ray beam from a synchrotron source to perform micro-diffraction on a series of Sn and Sn-containing finishes. The high brightness and small beam size of the X-ray enabled the generation of grain-by-grain orientation map as well as the strain/stress levels in individual grains. The electroplated finishes analyzed included pure Sn, Sn-Cu, and Sn-Cu-Pb finishes with various concentrations of Cu and Pb. Plating current density was also varied for each finish composition and the textures of these finishes were compared. After plating, these finishes were stored at ambient condition and examined regularly for surface defect formation. Once hillock or whisker growth was observed, the areas surrounding the growth were scanned with the X-ray. Additionally, these samples were also analyzed with standard X-ray diffraction and inverse pole figures were generated to compare the texture of the samples. A finite element model was also generated to simulate the texture of the finishes. By implementing the stiffness matrix of the finishes, we were able to explicitly implement the variation of finish texture on a grain-by-grain basis, and thus assess the strain/stress distribution in the finish. The analytical and simulation results from this study suggest that plating process parameters such as current density have a significant impact on the crystallographic texture of the plated finishes. Under similar strain conditions, certain textures would generate higher stresses in the finishes and result in higher levels of whisker growth.
{"title":"A synchrotron micro-diffraction investigation of crystallographic texture of high-Sn alloy films and its effects on whisker growth","authors":"P. Sarobol, A. Pedigo, J. Blendell, C. Handwerker, P. Su, Li Li, J. Xue","doi":"10.1109/ECTC.2010.5490896","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490896","url":null,"abstract":"For electroplated Sn and Sn alloy finishes, one of the reliability concerns remains the risk of whisker growth. Results from recent work have suggested that whiskers are most likely to form in regions of the films where high stress or a stress gradient exists. If strain/stress distribution information can be collected at a grain-by-grain level, correlations between such information and the propensity of whisker growth can be further understood. In this work, we utilized a highly focused X-ray beam from a synchrotron source to perform micro-diffraction on a series of Sn and Sn-containing finishes. The high brightness and small beam size of the X-ray enabled the generation of grain-by-grain orientation map as well as the strain/stress levels in individual grains. The electroplated finishes analyzed included pure Sn, Sn-Cu, and Sn-Cu-Pb finishes with various concentrations of Cu and Pb. Plating current density was also varied for each finish composition and the textures of these finishes were compared. After plating, these finishes were stored at ambient condition and examined regularly for surface defect formation. Once hillock or whisker growth was observed, the areas surrounding the growth were scanned with the X-ray. Additionally, these samples were also analyzed with standard X-ray diffraction and inverse pole figures were generated to compare the texture of the samples. A finite element model was also generated to simulate the texture of the finishes. By implementing the stiffness matrix of the finishes, we were able to explicitly implement the variation of finish texture on a grain-by-grain basis, and thus assess the strain/stress distribution in the finish. The analytical and simulation results from this study suggest that plating process parameters such as current density have a significant impact on the crystallographic texture of the plated finishes. Under similar strain conditions, certain textures would generate higher stresses in the finishes and result in higher levels of whisker growth.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116752494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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