Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490737
Ye Zhang, Yangjian Xu, Y. Liu, A. Schoenberg
The shear test under high strain rate is becoming a popular approach to investigate the fracture behaviour of a thermally attached solder ball under different strain rates. However, despite a substantial number of experimental tests being conducted recently, only a few numerical simulation works have been published. The lack of high performance computational analysis methods applicable to the evaluation of such a complex material and mechanical behaviour in solder interconnection, has yielded questionable accuracy of the simulation based on experimental observation. In this study, the experimental results regarding effects of shear loading speed are illustrated, and then three-dimensional explicit finite element analysis is employed to study dynamic responses of solder joints under ball impact testing. Through a three-dimensional explicit element analysis incorporated with a cohesive model, fracturing and fragmentation mechanisms, transient fracturing of the solder joint subjected to high speed impact test is investigated
{"title":"The experimental and numerical investigation on shear behaviour of solder ball in a wafer level chip scale package","authors":"Ye Zhang, Yangjian Xu, Y. Liu, A. Schoenberg","doi":"10.1109/ECTC.2010.5490737","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490737","url":null,"abstract":"The shear test under high strain rate is becoming a popular approach to investigate the fracture behaviour of a thermally attached solder ball under different strain rates. However, despite a substantial number of experimental tests being conducted recently, only a few numerical simulation works have been published. The lack of high performance computational analysis methods applicable to the evaluation of such a complex material and mechanical behaviour in solder interconnection, has yielded questionable accuracy of the simulation based on experimental observation. In this study, the experimental results regarding effects of shear loading speed are illustrated, and then three-dimensional explicit finite element analysis is employed to study dynamic responses of solder joints under ball impact testing. Through a three-dimensional explicit element analysis incorporated with a cohesive model, fracturing and fragmentation mechanisms, transient fracturing of the solder joint subjected to high speed impact test is investigated","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490948
Jing Shi, D. Popovic, N. Nettleton, T. Sze, D. Douglas, H. Thacker, J. Cunningham, K. Furuta, R. Kojima, Koichi Hirose, Kuopin Hwang
Proximity communication (PxC) technology has attracted great attention in recent years for its potential in low power, high bandwidth multi-chip module applications. In our previously demonstrated PxC MCM package, a 3-chip sub-assembly with two Active chips communicated through a Bridge chip and was flip-chip bonded to the substrate. The Bridge and Active chips overlap, and are face-to face bonded with silicone-based adhesive. The low pin count Bridge chip (face-up) relied on the bonded Au wire to deliver power and low speed I/Os. The parasitic inductance of the bondwires limited bandwidth on the Bridge, which motivated an alternative way to power the face-up Bridge chip. In this paper, we report chip-to-chip bonding using Anisotropic Conductive Film (ACF) as the dielectric adhesive between PxC channels. ACF provided direct vertical conductive path to power the Bridge chip. In addition, the introduction of conductive particles could increase the effective dielectric constant of the adhesive which benefits capacitively- signal coupling for proximity communications. The bonding experiment was carried out using a two-stage alignment and bonding/cure process at Sony Chemical & Information Device Corporation. Physical characterizations such as SAT, SEM, EDX were carried out to investigate bond line, alignment and quality of the adhesive interfaces. The effect of the floating metallic particles inside the ACF material on the local capacitive channels was simulated using a commercial FEM solver Q3D Extractor from ANSYS. We also tested conductive channel continuity through boundary scan-chain test of the Island chips. The initial results indicates that ACF sandwiched between two chips formed a uniform, void free bondline.
{"title":"Direct chip powering and enhancement of proximity communication through Anisotropic Conductive adhesive chip-to-chip bonding","authors":"Jing Shi, D. Popovic, N. Nettleton, T. Sze, D. Douglas, H. Thacker, J. Cunningham, K. Furuta, R. Kojima, Koichi Hirose, Kuopin Hwang","doi":"10.1109/ECTC.2010.5490948","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490948","url":null,"abstract":"Proximity communication (PxC) technology has attracted great attention in recent years for its potential in low power, high bandwidth multi-chip module applications. In our previously demonstrated PxC MCM package, a 3-chip sub-assembly with two Active chips communicated through a Bridge chip and was flip-chip bonded to the substrate. The Bridge and Active chips overlap, and are face-to face bonded with silicone-based adhesive. The low pin count Bridge chip (face-up) relied on the bonded Au wire to deliver power and low speed I/Os. The parasitic inductance of the bondwires limited bandwidth on the Bridge, which motivated an alternative way to power the face-up Bridge chip. In this paper, we report chip-to-chip bonding using Anisotropic Conductive Film (ACF) as the dielectric adhesive between PxC channels. ACF provided direct vertical conductive path to power the Bridge chip. In addition, the introduction of conductive particles could increase the effective dielectric constant of the adhesive which benefits capacitively- signal coupling for proximity communications. The bonding experiment was carried out using a two-stage alignment and bonding/cure process at Sony Chemical & Information Device Corporation. Physical characterizations such as SAT, SEM, EDX were carried out to investigate bond line, alignment and quality of the adhesive interfaces. The effect of the floating metallic particles inside the ACF material on the local capacitive channels was simulated using a commercial FEM solver Q3D Extractor from ANSYS. We also tested conductive channel continuity through boundary scan-chain test of the Island chips. The initial results indicates that ACF sandwiched between two chips formed a uniform, void free bondline.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"293 1‐2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113966900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490842
V. D. Khanna, S. M. Sri-Jayantha
Balancing the level of substrate warp at reflow with other sources contributing to C4 non-wets is an important problem. To address this, a methodology to predict the probability of non-wets during the chip attach process of an organic package has been developed. A technique for quantifying the convex or concave warp of a substrate in the form of a Shape Inversion (SI) plot is introduced. Geometrical factors that influence non-wets such as C4 height, the pad's relative location, collapsed solder height etc. are described and their individual contributions to the non-wet conditions are computed. Combining these contributions onto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrate and the results compared with the actual yield observed during chip assembly.
{"title":"Methodology for predicting C4 non-wets during the chip attach process","authors":"V. D. Khanna, S. M. Sri-Jayantha","doi":"10.1109/ECTC.2010.5490842","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490842","url":null,"abstract":"Balancing the level of substrate warp at reflow with other sources contributing to C4 non-wets is an important problem. To address this, a methodology to predict the probability of non-wets during the chip attach process of an organic package has been developed. A technique for quantifying the convex or concave warp of a substrate in the form of a Shape Inversion (SI) plot is introduced. Geometrical factors that influence non-wets such as C4 height, the pad's relative location, collapsed solder height etc. are described and their individual contributions to the non-wet conditions are computed. Combining these contributions onto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrate and the results compared with the actual yield observed during chip assembly.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131401426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490663
Se-Hoon Park, Jongin Ryu, J. C. Kim, N. Kang, Jong Chul Park, Young-Ho Kim
In this study, the research of embedded active and passive package is carried out for miniaturized wireless module. We fabricated very small RF module which one bare chip (0.3mm × 0.5mm, SPDT switch IC) and three 0603(0.6mm × 0.3mm, MLCC) passive devices were buried into within 1.85mm × 1.5mm substrate. Used materials were compatible with PCB process such as polymer laminating, dry film patterning, electroless-electrolytic copper plating and atmospheric plasma treatment. We studied low pressure bonding process using rheology dependence of polymer on temperature to prevent fracture or crack from embedding chips into PCB. The embedded chip and passives were electrically interconnected by small laser via(30µm) and Cu pattern plating process after atmospheric pressure plasma treatment, which revealed an effect on filling of micro via and shape of fine pattern. The interconnection between chip pad and Cu were evaluated by SEM image, which shows Cu pattern of PCB and pad of passive was interconnected without intermetallic formation. However, intermetallic, Cu-Sn-Ni, formed between passive electrode and plated Cu layer, and molten Sn is segregated along the wall of via hole after reflow. DSC (Differenntial Scanning Calorimetry) analysis was employed to calculate and optimize the amount of curing. Polymer showed maximum 90° peel strength (~0.7kgf/cm) with Cu pattern when Cu is plated on polymer after pre-curing was 80~90% completed. The RF characterization of embedded chip PCB was evaluated by measuring s-parameters (S11; return loss and S21; insertion loss). Return loss was below 20dB up to 4GHz. As a results, the embedded chip module is able to be applied for 2~5 GHz frequency application (Bluetooth and WiFi) with small size and good performance.
{"title":"Fabrication and characterization of embedded active and passive device for wireless application","authors":"Se-Hoon Park, Jongin Ryu, J. C. Kim, N. Kang, Jong Chul Park, Young-Ho Kim","doi":"10.1109/ECTC.2010.5490663","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490663","url":null,"abstract":"In this study, the research of embedded active and passive package is carried out for miniaturized wireless module. We fabricated very small RF module which one bare chip (0.3mm × 0.5mm, SPDT switch IC) and three 0603(0.6mm × 0.3mm, MLCC) passive devices were buried into within 1.85mm × 1.5mm substrate. Used materials were compatible with PCB process such as polymer laminating, dry film patterning, electroless-electrolytic copper plating and atmospheric plasma treatment. We studied low pressure bonding process using rheology dependence of polymer on temperature to prevent fracture or crack from embedding chips into PCB. The embedded chip and passives were electrically interconnected by small laser via(30µm) and Cu pattern plating process after atmospheric pressure plasma treatment, which revealed an effect on filling of micro via and shape of fine pattern. The interconnection between chip pad and Cu were evaluated by SEM image, which shows Cu pattern of PCB and pad of passive was interconnected without intermetallic formation. However, intermetallic, Cu-Sn-Ni, formed between passive electrode and plated Cu layer, and molten Sn is segregated along the wall of via hole after reflow. DSC (Differenntial Scanning Calorimetry) analysis was employed to calculate and optimize the amount of curing. Polymer showed maximum 90° peel strength (~0.7kgf/cm) with Cu pattern when Cu is plated on polymer after pre-curing was 80~90% completed. The RF characterization of embedded chip PCB was evaluated by measuring s-parameters (S11; return loss and S21; insertion loss). Return loss was below 20dB up to 4GHz. As a results, the embedded chip module is able to be applied for 2~5 GHz frequency application (Bluetooth and WiFi) with small size and good performance.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131552904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490887
M. Töpper, I. Ndip, R. Erxleben, L. Brusberg, N. Nissen, H. Schröder, H. Yamamoto, Guido Todt, H. Reichl
Interposers for SiP will become more and more important for advanced electronic systems. But through substrate vias are essential for the 3-D integration. Being a standard for laminate based materials this is much more complex for Si-wafers: High speed etching has to be combined with complex electrical isolation, diffusion barriers and void-free Cu-filling. Without doubt this can be solved in lab-scale but for high production scale cost is a tremendous barrier. Glass wafers with W-plugs have been intensively investigated in this paper. A new acronym has been posted to high-light this technology: TGV for Through Glass Vias. The results of modeling and simulation of TGV at RF/Microwave frequencies showed a very good compromise between wafer thickness, TGV-shape and via diameter for vertical metal plugs with 100 μm diameters in 500 μm thick glass wafer still very stable for thin film wafer processing without costly temporary wafer bonding processes. Therefore the HermeS® from Schott was chosen as the basis for a prototype of a bidirectional 4 × 10 Gbps electro-optical transceiver module. Thin film RDL and bumping of these wafers was possible without any modifications to Si-wafer. First thermal cycles showed very promising results for the reliability of this concept.
{"title":"3-D Thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer","authors":"M. Töpper, I. Ndip, R. Erxleben, L. Brusberg, N. Nissen, H. Schröder, H. Yamamoto, Guido Todt, H. Reichl","doi":"10.1109/ECTC.2010.5490887","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490887","url":null,"abstract":"Interposers for SiP will become more and more important for advanced electronic systems. But through substrate vias are essential for the 3-D integration. Being a standard for laminate based materials this is much more complex for Si-wafers: High speed etching has to be combined with complex electrical isolation, diffusion barriers and void-free Cu-filling. Without doubt this can be solved in lab-scale but for high production scale cost is a tremendous barrier. Glass wafers with W-plugs have been intensively investigated in this paper. A new acronym has been posted to high-light this technology: TGV for Through Glass Vias. The results of modeling and simulation of TGV at RF/Microwave frequencies showed a very good compromise between wafer thickness, TGV-shape and via diameter for vertical metal plugs with 100 μm diameters in 500 μm thick glass wafer still very stable for thin film wafer processing without costly temporary wafer bonding processes. Therefore the HermeS® from Schott was chosen as the basis for a prototype of a bidirectional 4 × 10 Gbps electro-optical transceiver module. Thin film RDL and bumping of these wafers was possible without any modifications to Si-wafer. First thermal cycles showed very promising results for the reliability of this concept.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131612461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490747
Zongyuan Liu, Kai Wang, Xiaobing Luo, Sheng Liu
High spatial color uniformity is realized by fabricating high power white light-emitting diodes (LEDs) with hemispherical YAG: Ce phosphor film. An injection molding process is developed to produce the phosphor film. By better control of the process, homogenous distribution of the phosphor particles is achieved. The color uniformity can be as high as 80%–90%. Comparing with white LEDs fabricated by traditional phosphor dispensing method and commercial samples with conformal phosphor coating, improvements of spatial color uniformity are around 36%–43% and 6%–8%, respectively, by the hemispherical phosphor.
{"title":"Realization of high spatial color uniformity for white light-emitting diodes by remote hemispherical YAG: Ce phosphor film","authors":"Zongyuan Liu, Kai Wang, Xiaobing Luo, Sheng Liu","doi":"10.1109/ECTC.2010.5490747","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490747","url":null,"abstract":"High spatial color uniformity is realized by fabricating high power white light-emitting diodes (LEDs) with hemispherical YAG: Ce phosphor film. An injection molding process is developed to produce the phosphor film. By better control of the process, homogenous distribution of the phosphor particles is achieved. The color uniformity can be as high as 80%–90%. Comparing with white LEDs fabricated by traditional phosphor dispensing method and commercial samples with conformal phosphor coating, improvements of spatial color uniformity are around 36%–43% and 6%–8%, respectively, by the hemispherical phosphor.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128148803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490784
M. Tentzeris, R. Vyas, V. Lakafosis, A. Traille, A. Rida, G. Shaker
In this talk, inkjet-printed flexible antennas, RF electronics and sensors fabricated on paper and other polymer (e.g. LCP) substrates are introduced as a system-level solution for ultra-low-cost mass production of UHF Radio Frequency Identification (RFID) Tags and Wireless Sensor Nodes (WSN) in an approach that could be easily extended to other microwave and wireless applications. A compact inkjet-printed UHF “passive-RFID” antenna using the classic T-match approach and designed to match IC's complex impedance, is presented as a demonstrating prototype for this technology. In addition, the authors briefly touch up the state-of-the-art area of fully-integrated wireless sensor modules on paper and show the first ever 2D sensor integration with an RFID tag module on paper, as well as the possibility of a 3D multilayer paper-based RF/microwave structures, that could potentially set the foundation for the truly convergent wireless sensor ad-hoc networks of the future. Plus, the authors present benchmarking results for various scavenging approaches involving RF, kinetic and thermal energy. Various challenges of packaging, passives, antennas, sensors and power sources integration are investigated in terms of ruggedness, reliability and flexing performance for space, automotive, "smart-skin" and wearable applications. This is the first time a complete 3D "green" system-on-paper including vertical interconnects and silver epoxy for the attachment of IC's will be presented for operability in frequencies in excess of 900 MHz.
{"title":"Inkjet-printed system-on-paper/polymer “green” RFID and wireless sensors","authors":"M. Tentzeris, R. Vyas, V. Lakafosis, A. Traille, A. Rida, G. Shaker","doi":"10.1109/ECTC.2010.5490784","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490784","url":null,"abstract":"In this talk, inkjet-printed flexible antennas, RF electronics and sensors fabricated on paper and other polymer (e.g. LCP) substrates are introduced as a system-level solution for ultra-low-cost mass production of UHF Radio Frequency Identification (RFID) Tags and Wireless Sensor Nodes (WSN) in an approach that could be easily extended to other microwave and wireless applications. A compact inkjet-printed UHF “passive-RFID” antenna using the classic T-match approach and designed to match IC's complex impedance, is presented as a demonstrating prototype for this technology. In addition, the authors briefly touch up the state-of-the-art area of fully-integrated wireless sensor modules on paper and show the first ever 2D sensor integration with an RFID tag module on paper, as well as the possibility of a 3D multilayer paper-based RF/microwave structures, that could potentially set the foundation for the truly convergent wireless sensor ad-hoc networks of the future. Plus, the authors present benchmarking results for various scavenging approaches involving RF, kinetic and thermal energy. Various challenges of packaging, passives, antennas, sensors and power sources integration are investigated in terms of ruggedness, reliability and flexing performance for space, automotive, \"smart-skin\" and wearable applications. This is the first time a complete 3D \"green\" system-on-paper including vertical interconnects and silver epoxy for the attachment of IC's will be presented for operability in frequencies in excess of 900 MHz.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490965
H. Thacker, Ying Luo, Jing Shi, I. Shubin, J. Lexau, Xuezhe Zheng, Guoliang Li, Jin Yao, Joannes M. Costa, T. Pinguet, A. Mekis, P. Dong, S. Liao, D. Feng, M. Asghari, R. Ho, K. Raj, James G. Mitchell, A. Krishnamoorthy, J. Cunningham
Silicon photonics holds tremendous promise as an energy and bandwidth efficient interconnect technology for chip-to-chip and within-chip communications in high-performance computing systems. In this paper, we present a low-parasitic microsolder-based flip-chip integration method used to integrate silicon photonic modulators and photodetectors with high-speed VLSI circuits using chips fabricated on vastly different technology platforms. Both the hybrid-integrated silicon photonic transmit (Tx) and receive (Rx) components were tested to demonstrate record sub-picojoule-per-bit performance at 5 Gbps.
{"title":"Flip-chip integrated silicon photonic bridge chips for sub-picojoule per bit optical links","authors":"H. Thacker, Ying Luo, Jing Shi, I. Shubin, J. Lexau, Xuezhe Zheng, Guoliang Li, Jin Yao, Joannes M. Costa, T. Pinguet, A. Mekis, P. Dong, S. Liao, D. Feng, M. Asghari, R. Ho, K. Raj, James G. Mitchell, A. Krishnamoorthy, J. Cunningham","doi":"10.1109/ECTC.2010.5490965","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490965","url":null,"abstract":"Silicon photonics holds tremendous promise as an energy and bandwidth efficient interconnect technology for chip-to-chip and within-chip communications in high-performance computing systems. In this paper, we present a low-parasitic microsolder-based flip-chip integration method used to integrate silicon photonic modulators and photodetectors with high-speed VLSI circuits using chips fabricated on vastly different technology platforms. Both the hybrid-integrated silicon photonic transmit (Tx) and receive (Rx) components were tested to demonstrate record sub-picojoule-per-bit performance at 5 Gbps.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134585580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490672
Sunghae Jung, Myunglae Lee, J. Moon
In this paper, the design, fabrication technology, and experimental evaluation of the RF frequency performance of a new type of solder paste via filled through-wafer interconnects in silicon substrates are presented
本文介绍了一种新型硅衬底填满晶圆互连锡膏的设计、制造工艺和射频性能的实验评价
{"title":"RF MEMS wafer-level packaging using solder paste by via filling process","authors":"Sunghae Jung, Myunglae Lee, J. Moon","doi":"10.1109/ECTC.2010.5490672","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490672","url":null,"abstract":"In this paper, the design, fabrication technology, and experimental evaluation of the RF frequency performance of a new type of solder paste via filled through-wafer interconnects in silicon substrates are presented","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490956
I. Kang, Gi-Jo Jung, Byoung-Yool Jeon, J. Yoo, Seong-Hun Jeong
Recently, System in Package (SiP) technology is rapidly evolved from a narrow set of applications to high volume applications on electronics markets, like small modules for mobile phone applications. Embedding technology is one of the solutions by embedding one or more chips into another chip or a substrate. In this study, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level flip-chip bonding technology, wafer level molding for under-filling and encapsulation by molding compound without any special substrate have been developed, including redistribution, solder and Cu bumping, thinning and ball mounting technology. Firstly to verify and optimize structure and materials through stress simulation for molded dies, maximum stress and its location have been confirmed and correlated with the result of reliability evaluation using molded die sample. The structure and materials for WL-eSiP has been optimized through molded die samples with evaluation of the reliability tests of MSL2a, PCT (121 °C/ 100%RH/ 2atm), TC (−40/125 °C) and HTS (150°C) in terms of various die size, dielectric and mold materials. Using the results achieved above, WL-eSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliabilities for verifying process and ensuring package reliability. Mother chip of 4mm × 4mm and daughter chip of 2.95mm × 2.31mm size have been designed in daisy chain pattern to be electrically interconnected each other. First of all, whole manufacturing process steps of wafer level embedded system in package (WL-eSiP) has been verified and developed, with redistribution, high aspect-ratio copper bumping, wafer level flip-chip bonding, wafer level molding, silicon and mold thinning and ball mounting technologies. Then, WL-eSiP has been fabricated for evaluation of package level reliability, MSL3, PCT (121°C/100%RH/ 2atm), TC (-40/125°C) and HTS (150°C) and all items have been passed. For the board level reliability test, daisy chain substrate has been designed and fabricated for TC (−40/125°C) and drop (1500G/ 0.5ms) tests. Besides, in order to increase the mother chip size from 16 mm2 to 36 mm2 for the expansion of application of WL-eSiP, stress improvement on each process step has been done through warpage and curvature evaluation on wafer level.
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