Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490655
J. Roberts, S. Hussain, M. Rahim, M. Motalab, J. Suhling, R. Jaeger, P. Lall, Ron Zhang
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.
{"title":"Characterization of microprocessor chip stress distributions during component packaging and thermal cycling","authors":"J. Roberts, S. Hussain, M. Rahim, M. Motalab, J. Suhling, R. Jaeger, P. Lall, Ron Zhang","doi":"10.1109/ECTC.2010.5490655","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490655","url":null,"abstract":"On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490643
L. Di Cioccio, P. Gueguen, Etienne Grouiller, L. Vandroux, V. Delaye, M. Rivoire, J. Lugand, L. Clavelier
Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.
{"title":"Vertical metal interconnect thanks to tungsten direct bonding","authors":"L. Di Cioccio, P. Gueguen, Etienne Grouiller, L. Vandroux, V. Delaye, M. Rivoire, J. Lugand, L. Clavelier","doi":"10.1109/ECTC.2010.5490643","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490643","url":null,"abstract":"Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116431111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490745
Pin J. Wang, Chu-Hsuan Sha, Chin C. Lee
After many experiments in developing fluxless Ag-In joints, we realize that the success of producing a joint relates to microstructure of the Ag layer. Ag with small grains results in rapid growth of solid Ag2In intermetallic compounds through grain boundary diffusion. Thus, a joint is not obtained because of lack of molten phase, (L). To coarsen Ag grains, an annealing step is added to the Ag-plated Cu substrate. This step makes Ag grains 200 times coarser compared to the as-plated Ag. The coarsened microstructure slows down the Ag2In growth. Consequently, the (L) phase stays at molten state with sufficient time to react with the Ag layer on Si chip to produce a joint. Nearly perfect joints are produced on Ag-plated Cu substrates. The resulting joints consist of pure Ag, Ag-rich solid solution, Ag2In, and Ag3In. The melting temperature exceeds 650°C. Using the present process, high temperature joints of high thermal conductivity are made between Si chips and Cu substrates at low bonding temperature (200°C). We foresee the Ag-In system as an important system to explore for various fluxless bonding applications. This system provides the possibilities of producing joints of wide composition choices and wide melting temperature range. Present study provides preliminary but useful information on how the microstructure of Ag affects the bonding results.
{"title":"Effect of Ag grain size on high temperature joint formation in Ag-In system","authors":"Pin J. Wang, Chu-Hsuan Sha, Chin C. Lee","doi":"10.1109/ECTC.2010.5490745","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490745","url":null,"abstract":"After many experiments in developing fluxless Ag-In joints, we realize that the success of producing a joint relates to microstructure of the Ag layer. Ag with small grains results in rapid growth of solid Ag2In intermetallic compounds through grain boundary diffusion. Thus, a joint is not obtained because of lack of molten phase, (L). To coarsen Ag grains, an annealing step is added to the Ag-plated Cu substrate. This step makes Ag grains 200 times coarser compared to the as-plated Ag. The coarsened microstructure slows down the Ag2In growth. Consequently, the (L) phase stays at molten state with sufficient time to react with the Ag layer on Si chip to produce a joint. Nearly perfect joints are produced on Ag-plated Cu substrates. The resulting joints consist of pure Ag, Ag-rich solid solution, Ag2In, and Ag3In. The melting temperature exceeds 650°C. Using the present process, high temperature joints of high thermal conductivity are made between Si chips and Cu substrates at low bonding temperature (200°C). We foresee the Ag-In system as an important system to explore for various fluxless bonding applications. This system provides the possibilities of producing joints of wide composition choices and wide melting temperature range. Present study provides preliminary but useful information on how the microstructure of Ag affects the bonding results.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124029965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490921
W. Feng, Yongzhi He, F. Shi
High power LEDs for lighting application can be implemented with dies. Multiple LEDs are usually connected in series to sustain high power supply voltage like AC 110V due to low LED forward voltage. AC-DC converter is often required for LED arrays working under an AC power supply. But the AC-DC converter brings power consumption overhead and degrades the overall system efficiency as much as 15%. In this work, a high power ceramic COB (Chip On Board) LED array packaging technology capable of working under AC 110V is developed. A total of 40 LEDs are used in the ceramic COB LEDs array to allow it work directly under AC 110V power supply. A special powering method is designed and dedicated to the COB LED array. The special powering method ensures both high light output and high LEDs array reliability especially under supply voltage variations. The measured COB LEDs current vs. AC supply voltage variation is shown in Fig.1 An extremely high driving efficiency (>98%) at the max power and a high power factor are achieved due to the elimination of the AC-DC converter. The electrical efficiency over LEDs forward current is plotted in Fig.2. The structure and top view of COB LED packaging is shown in Fig.3 and Fig.4. The COB package dimension is 68mm by 28mm. With 150mA LEDs forward current, the measured total power is 20W. The max LEDs forward current for this design is 700mA and the max power is 95W. The cross section of the PCB design is shown in Fig.5. Since AC-DC converter reliability is becoming the bottleneck of the high power LED lighting system, the presented ceramic COB LEDs array package with the special powering circuit reliability is enhanced due to the elimination of AC-DC converter. The system reliability is performed and shown in Fig.6. There is no performance degradation of both the ceramic COB LED and control circuit for 1000 hours. Long term reliability test of the system is still under testing and will be presented.
{"title":"Packaging and AC powering of LED array","authors":"W. Feng, Yongzhi He, F. Shi","doi":"10.1109/ECTC.2010.5490921","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490921","url":null,"abstract":"High power LEDs for lighting application can be implemented with dies. Multiple LEDs are usually connected in series to sustain high power supply voltage like AC 110V due to low LED forward voltage. AC-DC converter is often required for LED arrays working under an AC power supply. But the AC-DC converter brings power consumption overhead and degrades the overall system efficiency as much as 15%. In this work, a high power ceramic COB (Chip On Board) LED array packaging technology capable of working under AC 110V is developed. A total of 40 LEDs are used in the ceramic COB LEDs array to allow it work directly under AC 110V power supply. A special powering method is designed and dedicated to the COB LED array. The special powering method ensures both high light output and high LEDs array reliability especially under supply voltage variations. The measured COB LEDs current vs. AC supply voltage variation is shown in Fig.1 An extremely high driving efficiency (>98%) at the max power and a high power factor are achieved due to the elimination of the AC-DC converter. The electrical efficiency over LEDs forward current is plotted in Fig.2. The structure and top view of COB LED packaging is shown in Fig.3 and Fig.4. The COB package dimension is 68mm by 28mm. With 150mA LEDs forward current, the measured total power is 20W. The max LEDs forward current for this design is 700mA and the max power is 95W. The cross section of the PCB design is shown in Fig.5. Since AC-DC converter reliability is becoming the bottleneck of the high power LED lighting system, the presented ceramic COB LEDs array package with the special powering circuit reliability is enhanced due to the elimination of AC-DC converter. The system reliability is performed and shown in Fig.6. There is no performance degradation of both the ceramic COB LED and control circuit for 1000 hours. Long term reliability test of the system is still under testing and will be presented.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"59 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490937
Kiwon Lee, K. Paik
In this study, in order to improve the electrical properties and the reliability of ACF joints, we propose the simultaneous fluxless solder joining and adhesive bonding technology. This technology utilizes fluxless soldering within an adhesive matrix on metal electrodes combined with room temperature ultrasonic (U/S) ACF bonding technique advantages. According to the experimental results, the temperature of the solder ACF joints showed rapid heating rates up to 400 °C/s and peak values above 250°C by applying ultrasonic vibration. The ACF temperature could be precisely controlled ranging from 75°C to 260°C by adjusting U/S vibration amplitudes from 4 um to 13 um. At above the melting temperatures of solder particles, U/S bonded solder ACF joints showed higher than 80% soldering ratios and no void formation with optimized U/S parameters. The soldering ratio at the solder ACF joints increased as the ACF temperature increased and it was presumably due to the viscosity decrease of the ACF adhesive matrix. On the other hand, thermocompression (T/C) bonded solder ACF joints showed poor soldering ratios lower than 30% and severe void formation at above 200°C. At the same time, U/S bonded solder ACF joints showed 30% reduced electrical contact resistances and twice better reliability in an unbiased autoclave test (121°C, 2 atm, 100%RH) compared with conventional ACF joints. Significance of this result is that fluxless solder joining and adhesive bonding can be simultaneously achieved within 5 seconds by using solder ACFs combined with the room temperature U/S bonding technique.
{"title":"High power and fine pitch assembly using solder Anisotropic Conductive Films (ACFs) combined with ultrasonic bonding technique","authors":"Kiwon Lee, K. Paik","doi":"10.1109/ECTC.2010.5490937","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490937","url":null,"abstract":"In this study, in order to improve the electrical properties and the reliability of ACF joints, we propose the simultaneous fluxless solder joining and adhesive bonding technology. This technology utilizes fluxless soldering within an adhesive matrix on metal electrodes combined with room temperature ultrasonic (U/S) ACF bonding technique advantages. According to the experimental results, the temperature of the solder ACF joints showed rapid heating rates up to 400 °C/s and peak values above 250°C by applying ultrasonic vibration. The ACF temperature could be precisely controlled ranging from 75°C to 260°C by adjusting U/S vibration amplitudes from 4 um to 13 um. At above the melting temperatures of solder particles, U/S bonded solder ACF joints showed higher than 80% soldering ratios and no void formation with optimized U/S parameters. The soldering ratio at the solder ACF joints increased as the ACF temperature increased and it was presumably due to the viscosity decrease of the ACF adhesive matrix. On the other hand, thermocompression (T/C) bonded solder ACF joints showed poor soldering ratios lower than 30% and severe void formation at above 200°C. At the same time, U/S bonded solder ACF joints showed 30% reduced electrical contact resistances and twice better reliability in an unbiased autoclave test (121°C, 2 atm, 100%RH) compared with conventional ACF joints. Significance of this result is that fluxless solder joining and adhesive bonding can be simultaneously achieved within 5 seconds by using solder ACFs combined with the room temperature U/S bonding technique.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490696
J. Hsu, Sam Yang, Wei-Da Guo, R. Lee, Tung-Yang Chen
A systematic design method by using channel factorial design is proposed to meet the low-cost DDRII system solution with quad-flat-package (QFP) and two-layer printed circuit board. The channel characteristic was analyzed through one numerical transformation between time and frequency domains to figure out the time-variant waveform on the corresponding spectrum for potential radiated emission issues. By using the factorial analysis, the critical electrical parameters could be clearly list down and optimized in the pre-design analysis. This methodology could be usefully applied in the electrical physical constraint setup and budget control on the design phase. We can make a right compromise among the different design electrical factors with the corresponding penalties to robustly function up to DDRII 800Mbps in this low-cost system.
{"title":"High-speed parallel interface implementation with low-cost system solution by using signal integrity factorial design","authors":"J. Hsu, Sam Yang, Wei-Da Guo, R. Lee, Tung-Yang Chen","doi":"10.1109/ECTC.2010.5490696","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490696","url":null,"abstract":"A systematic design method by using channel factorial design is proposed to meet the low-cost DDRII system solution with quad-flat-package (QFP) and two-layer printed circuit board. The channel characteristic was analyzed through one numerical transformation between time and frequency domains to figure out the time-variant waveform on the corresponding spectrum for potential radiated emission issues. By using the factorial analysis, the critical electrical parameters could be clearly list down and optimized in the pre-design analysis. This methodology could be usefully applied in the electrical physical constraint setup and budget control on the design phase. We can make a right compromise among the different design electrical factors with the corresponding penalties to robustly function up to DDRII 800Mbps in this low-cost system.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126222462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490843
Kyoung-Lim Suk, Jong-Soo Kim, K. Paik
Various chip-on-2-metal flex (2-metal COF) packaging methods using such as ACF and NCF adhesives, and AuSn metallurgical bonding methods, were investigated in terms of electrical characteristics, flip chip joint quality, and reliability performances. 2-metal flex substrate and test chip were designed to include different pitches, 35 um, 25 um, and 20 um pitch. Thermal cycling test (TC test, −40 °C ~ +125 °C, 1000 cycles), and high temperature storage test (HTS test, 125 °C, 1000 hrs) were conducted to verify reliability of the 2-metal COF packages by various bonding methods. All the COF packages showed good TC and HTS reliability, whereas electrically shorted joints were observed during reliability tests only at the 20 um pitch of ACF joints. Therefore, for less than 20 um pitch of 2-metal COF packages, NCF adhesives bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for larger than 25 um pitch applications.
{"title":"Studies on various 2-metal chip-on-flex (COF) packaging methods","authors":"Kyoung-Lim Suk, Jong-Soo Kim, K. Paik","doi":"10.1109/ECTC.2010.5490843","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490843","url":null,"abstract":"Various chip-on-2-metal flex (2-metal COF) packaging methods using such as ACF and NCF adhesives, and AuSn metallurgical bonding methods, were investigated in terms of electrical characteristics, flip chip joint quality, and reliability performances. 2-metal flex substrate and test chip were designed to include different pitches, 35 um, 25 um, and 20 um pitch. Thermal cycling test (TC test, −40 °C ~ +125 °C, 1000 cycles), and high temperature storage test (HTS test, 125 °C, 1000 hrs) were conducted to verify reliability of the 2-metal COF packages by various bonding methods. All the COF packages showed good TC and HTS reliability, whereas electrically shorted joints were observed during reliability tests only at the 20 um pitch of ACF joints. Therefore, for less than 20 um pitch of 2-metal COF packages, NCF adhesives bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for larger than 25 um pitch applications.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127753601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490905
B. Guenin, Jing Shi
Proximity Communication is a technology that enables high-bandwidth chip-to-chip signaling using dense arrays of metal pads that are capacitively coupled to the corresponding pads on the neighboring chip. To successfully deploy Proximity Communication requires limiting chip x-y misalignment and separation to be less than 8 µm and maintaining these tolerances over many temperature cycles. This paper examines these requirements in light of test results and detailed mechanical modeling to both understand the performance of existing package designs and to identify design modifications that lead to improved performance.
{"title":"Mechanical analysis and reliability enhancement of a Proximity Communication flip chip package","authors":"B. Guenin, Jing Shi","doi":"10.1109/ECTC.2010.5490905","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490905","url":null,"abstract":"Proximity Communication is a technology that enables high-bandwidth chip-to-chip signaling using dense arrays of metal pads that are capacitively coupled to the corresponding pads on the neighboring chip. To successfully deploy Proximity Communication requires limiting chip x-y misalignment and separation to be less than 8 µm and maintaining these tolerances over many temperature cycles. This paper examines these requirements in light of test results and detailed mechanical modeling to both understand the performance of existing package designs and to identify design modifications that lead to improved performance.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127370550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490690
N. Na, Tao Wang, Scot Baumgartner, R. Mandrekar, Yaping Zhou
This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.
{"title":"Link analysis and design of high speed storage buses in backplane and cabling environments","authors":"N. Na, Tao Wang, Scot Baumgartner, R. Mandrekar, Yaping Zhou","doi":"10.1109/ECTC.2010.5490690","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490690","url":null,"abstract":"This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127402253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.5781/KWJS.2011.29.1.099
Seung-Jae Jo, Ah-Reum Lee, C. Kang
Joint strength between solder ball and pad on the substrate is one of the major factors which have effects on the electronic device reliability. To improve the strength of the solder joint, the efforts evaluation surface cleaning, heat treatment and change of solder composition have been in progress. This paper discussed a solder ball joint strength improvement using low frequency hydrogen radical surface treatment and focused on the effects of surface treatment conditions on the interfacial reaction and the shear strength of the solder ball. The shear strength between the solder ball and the pad increased about 30% in comparison with no treatment under the same reflow condition. Especially, at a treatment time of 5minutes, the shear strength considerably increased by 70% and the fracture mode of the shear test changed from interfacial fracture to the solder fracture.
{"title":"Improvement of the solder joint strength in a SAC 305 solder ball to a ENIG substrate using LF hydrogen radical treatment","authors":"Seung-Jae Jo, Ah-Reum Lee, C. Kang","doi":"10.5781/KWJS.2011.29.1.099","DOIUrl":"https://doi.org/10.5781/KWJS.2011.29.1.099","url":null,"abstract":"Joint strength between solder ball and pad on the substrate is one of the major factors which have effects on the electronic device reliability. To improve the strength of the solder joint, the efforts evaluation surface cleaning, heat treatment and change of solder composition have been in progress. This paper discussed a solder ball joint strength improvement using low frequency hydrogen radical surface treatment and focused on the effects of surface treatment conditions on the interfacial reaction and the shear strength of the solder ball. The shear strength between the solder ball and the pad increased about 30% in comparison with no treatment under the same reflow condition. Especially, at a treatment time of 5minutes, the shear strength considerably increased by 70% and the fracture mode of the shear test changed from interfacial fracture to the solder fracture.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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