Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490739
O. Hildreth, C. Álvarez, C. Wong
This paper demonstrates the use of tungsten as a viable, low cost catalyst for Metal-assisted Chemical Etching (MaCE) of silicon to create high aspect ratio nanostructures in silicon. The effect of etchant composition and etching time is reported along with Scanning Electron Microscope (SEM) and Atomic Force Microscopy (AFM) images confirming that tungsten acted as a catalyst for MaCE.
{"title":"Tungsten as a CMOS compatible catalyst for the Metal-assisted Chemical Etching of silicon to create 2D and 3D nanostructures","authors":"O. Hildreth, C. Álvarez, C. Wong","doi":"10.1109/ECTC.2010.5490739","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490739","url":null,"abstract":"This paper demonstrates the use of tungsten as a viable, low cost catalyst for Metal-assisted Chemical Etching (MaCE) of silicon to create high aspect ratio nanostructures in silicon. The effect of etchant composition and etching time is reported along with Scanning Electron Microscope (SEM) and Atomic Force Microscopy (AFM) images confirming that tungsten acted as a catalyst for MaCE.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122072016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490921
W. Feng, Yongzhi He, F. Shi
High power LEDs for lighting application can be implemented with dies. Multiple LEDs are usually connected in series to sustain high power supply voltage like AC 110V due to low LED forward voltage. AC-DC converter is often required for LED arrays working under an AC power supply. But the AC-DC converter brings power consumption overhead and degrades the overall system efficiency as much as 15%. In this work, a high power ceramic COB (Chip On Board) LED array packaging technology capable of working under AC 110V is developed. A total of 40 LEDs are used in the ceramic COB LEDs array to allow it work directly under AC 110V power supply. A special powering method is designed and dedicated to the COB LED array. The special powering method ensures both high light output and high LEDs array reliability especially under supply voltage variations. The measured COB LEDs current vs. AC supply voltage variation is shown in Fig.1 An extremely high driving efficiency (>98%) at the max power and a high power factor are achieved due to the elimination of the AC-DC converter. The electrical efficiency over LEDs forward current is plotted in Fig.2. The structure and top view of COB LED packaging is shown in Fig.3 and Fig.4. The COB package dimension is 68mm by 28mm. With 150mA LEDs forward current, the measured total power is 20W. The max LEDs forward current for this design is 700mA and the max power is 95W. The cross section of the PCB design is shown in Fig.5. Since AC-DC converter reliability is becoming the bottleneck of the high power LED lighting system, the presented ceramic COB LEDs array package with the special powering circuit reliability is enhanced due to the elimination of AC-DC converter. The system reliability is performed and shown in Fig.6. There is no performance degradation of both the ceramic COB LED and control circuit for 1000 hours. Long term reliability test of the system is still under testing and will be presented.
{"title":"Packaging and AC powering of LED array","authors":"W. Feng, Yongzhi He, F. Shi","doi":"10.1109/ECTC.2010.5490921","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490921","url":null,"abstract":"High power LEDs for lighting application can be implemented with dies. Multiple LEDs are usually connected in series to sustain high power supply voltage like AC 110V due to low LED forward voltage. AC-DC converter is often required for LED arrays working under an AC power supply. But the AC-DC converter brings power consumption overhead and degrades the overall system efficiency as much as 15%. In this work, a high power ceramic COB (Chip On Board) LED array packaging technology capable of working under AC 110V is developed. A total of 40 LEDs are used in the ceramic COB LEDs array to allow it work directly under AC 110V power supply. A special powering method is designed and dedicated to the COB LED array. The special powering method ensures both high light output and high LEDs array reliability especially under supply voltage variations. The measured COB LEDs current vs. AC supply voltage variation is shown in Fig.1 An extremely high driving efficiency (>98%) at the max power and a high power factor are achieved due to the elimination of the AC-DC converter. The electrical efficiency over LEDs forward current is plotted in Fig.2. The structure and top view of COB LED packaging is shown in Fig.3 and Fig.4. The COB package dimension is 68mm by 28mm. With 150mA LEDs forward current, the measured total power is 20W. The max LEDs forward current for this design is 700mA and the max power is 95W. The cross section of the PCB design is shown in Fig.5. Since AC-DC converter reliability is becoming the bottleneck of the high power LED lighting system, the presented ceramic COB LEDs array package with the special powering circuit reliability is enhanced due to the elimination of AC-DC converter. The system reliability is performed and shown in Fig.6. There is no performance degradation of both the ceramic COB LED and control circuit for 1000 hours. Long term reliability test of the system is still under testing and will be presented.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"59 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490764
A. Roesler, J. Schare, Chad Hettler, D. Abel, G. Slama, D. Schofield
This paper discusses a new approach to making hybrid power electronic circuits by combining a low-temperature (850°C to 950°C) co-fired ceramic (LTCC) substrate, planar LTCC ferrite transformers/inductors and integrated passive components into a multilayer monolithic package using a ferrite-based LTCC material system. A ferrite tape functions as the base material for this LTCC system. The material system includes physically and chemically compatible dielectric paste, dielectric tape and conductor materials which can be co-fired with the base ferrite LTCC tape to create sintered devices with excellent magnetic coupling, high permeability (~400), high resistivity (> 1012 Ω·cm) and good saturation (~0.3 T). The co-fired ferrite and dielectric materials can be used as a substrate for attaching or housing semiconductor components and other discrete devices that are part of the power electronics system. Furthermore, the ability to co-fire the ferrite with dielectric and conductor materials allows for the incorporation of embedded passives in the multilayer structure to create hybrid power electronic circuits. Overall this thick film material set offers a unique approach to making hybrid power electronics and could potentially allow a size reduction for many commercial dc-dc converter and other power electronic circuits.
{"title":"Integrated power electronics using a ferrite-based low-temperature co-fired ceramic materials system","authors":"A. Roesler, J. Schare, Chad Hettler, D. Abel, G. Slama, D. Schofield","doi":"10.1109/ECTC.2010.5490764","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490764","url":null,"abstract":"This paper discusses a new approach to making hybrid power electronic circuits by combining a low-temperature (850°C to 950°C) co-fired ceramic (LTCC) substrate, planar LTCC ferrite transformers/inductors and integrated passive components into a multilayer monolithic package using a ferrite-based LTCC material system. A ferrite tape functions as the base material for this LTCC system. The material system includes physically and chemically compatible dielectric paste, dielectric tape and conductor materials which can be co-fired with the base ferrite LTCC tape to create sintered devices with excellent magnetic coupling, high permeability (~400), high resistivity (> 1012 Ω·cm) and good saturation (~0.3 T). The co-fired ferrite and dielectric materials can be used as a substrate for attaching or housing semiconductor components and other discrete devices that are part of the power electronics system. Furthermore, the ability to co-fire the ferrite with dielectric and conductor materials allows for the incorporation of embedded passives in the multilayer structure to create hybrid power electronic circuits. Overall this thick film material set offers a unique approach to making hybrid power electronics and could potentially allow a size reduction for many commercial dc-dc converter and other power electronic circuits.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490745
Pin J. Wang, Chu-Hsuan Sha, Chin C. Lee
After many experiments in developing fluxless Ag-In joints, we realize that the success of producing a joint relates to microstructure of the Ag layer. Ag with small grains results in rapid growth of solid Ag2In intermetallic compounds through grain boundary diffusion. Thus, a joint is not obtained because of lack of molten phase, (L). To coarsen Ag grains, an annealing step is added to the Ag-plated Cu substrate. This step makes Ag grains 200 times coarser compared to the as-plated Ag. The coarsened microstructure slows down the Ag2In growth. Consequently, the (L) phase stays at molten state with sufficient time to react with the Ag layer on Si chip to produce a joint. Nearly perfect joints are produced on Ag-plated Cu substrates. The resulting joints consist of pure Ag, Ag-rich solid solution, Ag2In, and Ag3In. The melting temperature exceeds 650°C. Using the present process, high temperature joints of high thermal conductivity are made between Si chips and Cu substrates at low bonding temperature (200°C). We foresee the Ag-In system as an important system to explore for various fluxless bonding applications. This system provides the possibilities of producing joints of wide composition choices and wide melting temperature range. Present study provides preliminary but useful information on how the microstructure of Ag affects the bonding results.
{"title":"Effect of Ag grain size on high temperature joint formation in Ag-In system","authors":"Pin J. Wang, Chu-Hsuan Sha, Chin C. Lee","doi":"10.1109/ECTC.2010.5490745","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490745","url":null,"abstract":"After many experiments in developing fluxless Ag-In joints, we realize that the success of producing a joint relates to microstructure of the Ag layer. Ag with small grains results in rapid growth of solid Ag2In intermetallic compounds through grain boundary diffusion. Thus, a joint is not obtained because of lack of molten phase, (L). To coarsen Ag grains, an annealing step is added to the Ag-plated Cu substrate. This step makes Ag grains 200 times coarser compared to the as-plated Ag. The coarsened microstructure slows down the Ag2In growth. Consequently, the (L) phase stays at molten state with sufficient time to react with the Ag layer on Si chip to produce a joint. Nearly perfect joints are produced on Ag-plated Cu substrates. The resulting joints consist of pure Ag, Ag-rich solid solution, Ag2In, and Ag3In. The melting temperature exceeds 650°C. Using the present process, high temperature joints of high thermal conductivity are made between Si chips and Cu substrates at low bonding temperature (200°C). We foresee the Ag-In system as an important system to explore for various fluxless bonding applications. This system provides the possibilities of producing joints of wide composition choices and wide melting temperature range. Present study provides preliminary but useful information on how the microstructure of Ag affects the bonding results.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124029965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490963
T. Sugimoto, Y. Hashimoto, K. Yamamoto, M. Kurihara, M. Oda, J. Sakai, H. Ono, T. Akagawa, K. Yashiki, H. Hatayama, N. Suzuki, M. Tsuji, I. Ogura, H. Kouta, K. Kurata
We have developed 12-channel × 20-Gbps optical transmitter/receiver modules with 9 × 14-mm footprints. To achieve stable optical coupling efficiency, we also developed a precise multi-chip mounting technique. The three dies of 4-channel vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD) arrays are mounted at the same time. The accuracy of the Z-axis can be controlled by monitoring the dies' positions for the optical reference plane. The coupling losses were less than 1.5 dB in the 12-channel transmitter/receiver modules. The standard deviations of the coupling losses were less than 1.0 dB in all samples. Error-free transmissions at a data rate of 20 Gbps were also demonstrated. A reliability test indicated that the modules are repairable and reliable.
{"title":"12-Channel × 20-Gbps on-board parallel optical modules using multi-chip visual alignment technique","authors":"T. Sugimoto, Y. Hashimoto, K. Yamamoto, M. Kurihara, M. Oda, J. Sakai, H. Ono, T. Akagawa, K. Yashiki, H. Hatayama, N. Suzuki, M. Tsuji, I. Ogura, H. Kouta, K. Kurata","doi":"10.1109/ECTC.2010.5490963","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490963","url":null,"abstract":"We have developed 12-channel × 20-Gbps optical transmitter/receiver modules with 9 × 14-mm footprints. To achieve stable optical coupling efficiency, we also developed a precise multi-chip mounting technique. The three dies of 4-channel vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD) arrays are mounted at the same time. The accuracy of the Z-axis can be controlled by monitoring the dies' positions for the optical reference plane. The coupling losses were less than 1.5 dB in the 12-channel transmitter/receiver modules. The standard deviations of the coupling losses were less than 1.0 dB in all samples. Error-free transmissions at a data rate of 20 Gbps were also demonstrated. A reliability test indicated that the modules are repairable and reliable.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128991946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490722
R. Saha, N. Fritz, S. Bidstrup-Allen, P. Kohl
Air-gap structures are of interest in a range of microelectronic applications especially in microelectromechanical systems (MEMS). In this work, we investigate the application of an unique trimaterial for MEMS packaging composed of polypropylene carbonate (PPC) as a sacrificial material, a photosensitive, hybrid inorganic/organic dielectric epoxycyclohexyl polyhedral oligomeric silsesquioxanes (POSS) as the overcoat material, and Al/Cr-Cu thin metal film as a hermetic seal. POSS was used both for patterning the PPC over the structures as well as a stable overcoat material thus reducing the complexity of the fabrication process. A wide range of device sizes and structures (from 20 × 100 µm to 600 × 1000 µm) were fabricated and the processing protocol was found to be compliant over these size/structure variations. Metal adhesion on the overcoat was substantially improved by using low power oxygen plasma for short durations. Cavity-strength was evaluated for different metals and thicknesses. An increase of 5.6 times in cavity-strength was observed for a thicker (3X) Al metal film. Current work is focused on implementing the wafer-level air-cavity package into a lead frame packaged MEMS device through injection and compression molding techniques.
{"title":"Three dimensional air-gap structures for MEMS packaging","authors":"R. Saha, N. Fritz, S. Bidstrup-Allen, P. Kohl","doi":"10.1109/ECTC.2010.5490722","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490722","url":null,"abstract":"Air-gap structures are of interest in a range of microelectronic applications especially in microelectromechanical systems (MEMS). In this work, we investigate the application of an unique trimaterial for MEMS packaging composed of polypropylene carbonate (PPC) as a sacrificial material, a photosensitive, hybrid inorganic/organic dielectric epoxycyclohexyl polyhedral oligomeric silsesquioxanes (POSS) as the overcoat material, and Al/Cr-Cu thin metal film as a hermetic seal. POSS was used both for patterning the PPC over the structures as well as a stable overcoat material thus reducing the complexity of the fabrication process. A wide range of device sizes and structures (from 20 × 100 µm to 600 × 1000 µm) were fabricated and the processing protocol was found to be compliant over these size/structure variations. Metal adhesion on the overcoat was substantially improved by using low power oxygen plasma for short durations. Cavity-strength was evaluated for different metals and thicknesses. An increase of 5.6 times in cavity-strength was observed for a thicker (3X) Al metal film. Current work is focused on implementing the wafer-level air-cavity package into a lead frame packaged MEMS device through injection and compression molding techniques.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129264757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490690
N. Na, Tao Wang, Scot Baumgartner, R. Mandrekar, Yaping Zhou
This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.
{"title":"Link analysis and design of high speed storage buses in backplane and cabling environments","authors":"N. Na, Tao Wang, Scot Baumgartner, R. Mandrekar, Yaping Zhou","doi":"10.1109/ECTC.2010.5490690","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490690","url":null,"abstract":"This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127402253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490905
B. Guenin, Jing Shi
Proximity Communication is a technology that enables high-bandwidth chip-to-chip signaling using dense arrays of metal pads that are capacitively coupled to the corresponding pads on the neighboring chip. To successfully deploy Proximity Communication requires limiting chip x-y misalignment and separation to be less than 8 µm and maintaining these tolerances over many temperature cycles. This paper examines these requirements in light of test results and detailed mechanical modeling to both understand the performance of existing package designs and to identify design modifications that lead to improved performance.
{"title":"Mechanical analysis and reliability enhancement of a Proximity Communication flip chip package","authors":"B. Guenin, Jing Shi","doi":"10.1109/ECTC.2010.5490905","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490905","url":null,"abstract":"Proximity Communication is a technology that enables high-bandwidth chip-to-chip signaling using dense arrays of metal pads that are capacitively coupled to the corresponding pads on the neighboring chip. To successfully deploy Proximity Communication requires limiting chip x-y misalignment and separation to be less than 8 µm and maintaining these tolerances over many temperature cycles. This paper examines these requirements in light of test results and detailed mechanical modeling to both understand the performance of existing package designs and to identify design modifications that lead to improved performance.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127370550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490843
Kyoung-Lim Suk, Jong-Soo Kim, K. Paik
Various chip-on-2-metal flex (2-metal COF) packaging methods using such as ACF and NCF adhesives, and AuSn metallurgical bonding methods, were investigated in terms of electrical characteristics, flip chip joint quality, and reliability performances. 2-metal flex substrate and test chip were designed to include different pitches, 35 um, 25 um, and 20 um pitch. Thermal cycling test (TC test, −40 °C ~ +125 °C, 1000 cycles), and high temperature storage test (HTS test, 125 °C, 1000 hrs) were conducted to verify reliability of the 2-metal COF packages by various bonding methods. All the COF packages showed good TC and HTS reliability, whereas electrically shorted joints were observed during reliability tests only at the 20 um pitch of ACF joints. Therefore, for less than 20 um pitch of 2-metal COF packages, NCF adhesives bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for larger than 25 um pitch applications.
{"title":"Studies on various 2-metal chip-on-flex (COF) packaging methods","authors":"Kyoung-Lim Suk, Jong-Soo Kim, K. Paik","doi":"10.1109/ECTC.2010.5490843","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490843","url":null,"abstract":"Various chip-on-2-metal flex (2-metal COF) packaging methods using such as ACF and NCF adhesives, and AuSn metallurgical bonding methods, were investigated in terms of electrical characteristics, flip chip joint quality, and reliability performances. 2-metal flex substrate and test chip were designed to include different pitches, 35 um, 25 um, and 20 um pitch. Thermal cycling test (TC test, −40 °C ~ +125 °C, 1000 cycles), and high temperature storage test (HTS test, 125 °C, 1000 hrs) were conducted to verify reliability of the 2-metal COF packages by various bonding methods. All the COF packages showed good TC and HTS reliability, whereas electrically shorted joints were observed during reliability tests only at the 20 um pitch of ACF joints. Therefore, for less than 20 um pitch of 2-metal COF packages, NCF adhesives bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for larger than 25 um pitch applications.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127753601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490672
Sunghae Jung, Myunglae Lee, J. Moon
In this paper, the design, fabrication technology, and experimental evaluation of the RF frequency performance of a new type of solder paste via filled through-wafer interconnects in silicon substrates are presented
本文介绍了一种新型硅衬底填满晶圆互连锡膏的设计、制造工艺和射频性能的实验评价
{"title":"RF MEMS wafer-level packaging using solder paste by via filling process","authors":"Sunghae Jung, Myunglae Lee, J. Moon","doi":"10.1109/ECTC.2010.5490672","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490672","url":null,"abstract":"In this paper, the design, fabrication technology, and experimental evaluation of the RF frequency performance of a new type of solder paste via filled through-wafer interconnects in silicon substrates are presented","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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