Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490820
B. Dang, P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, J. Knickerbocker
This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput at low cost. Using pulsed ultraviolet (UV) radiation from excimer lasers, device wafers as thin as 50µm can be released from the temporary mechanical handler wafer in less than 1min. Bonding, adhesive, debonding and post debond clean processes were demonstrated. CMOS circuit test vehicles were shown to be compatible with this temporary bonding and debonding processes.
{"title":"CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration","authors":"B. Dang, P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, J. Knickerbocker","doi":"10.1109/ECTC.2010.5490820","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490820","url":null,"abstract":"This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput at low cost. Using pulsed ultraviolet (UV) radiation from excimer lasers, device wafers as thin as 50µm can be released from the temporary mechanical handler wafer in less than 1min. Bonding, adhesive, debonding and post debond clean processes were demonstrated. CMOS circuit test vehicles were shown to be compatible with this temporary bonding and debonding processes.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124925976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490920
W. Woods, H. Ding, Guoan Wang, A. Joseph
On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.
{"title":"Novel on-chip Through-Silicon-Via Wilkinson power divider","authors":"W. Woods, H. Ding, Guoan Wang, A. Joseph","doi":"10.1109/ECTC.2010.5490920","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490920","url":null,"abstract":"On-chip Wilkinson power dividers are used in MMW circuit designs such as phased array antenna systems. This paper presents a novel on-chip MMW Through-Silicon-Via (TSV) Wilkinson power divider. HFSS simulations of the TSV Wilkinson power divider in a 130 nm BiCMOS technology revealed insertion loss per λ/4 “arm” of 0.9 dB at 60 GHz with both return loss and isolation better than 18 dB at 60 GHz and good matching in both signal phase and amplitude at the two outputs.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490654
J. Agar, Katy J. Lin, Rongwei Zhang, J. Durden, K. Moon, C. Wong
Future electronics will undoubtedly require natural integration at the system, device and package level in the form of a functional, flexible package. Functional, flexible electronics expand the functionality of devices allowing morphological-electronic response for ergonomic and natural interfaces between the device and its surroundings. Recent technological successes have been able to fabricate functional, flexible electronics, however have all failed to develop a package capable of meeting the stringent cost, reliability and performance required of consumer electronics. We demonstrate the application of electrically conductive adhesive technology to produce low cost, flexible electronics without metallization. We have shown the capability of fabrication of highly conductive Poly(dimethlysiloxane) (PDMS) (ρ~7×10−4 Ω•cm) by incorporation of 80 wt% bimodal distribution of micron sized silver flakes. PDMS is both the ideal substrate and composite matrix material due to its unique properties; PDMS is optically transparent, viscoelastic, chemically and thermally stable, highly flexible, hydrophobic and can easily be molded with high resolution and aspect ratio. These unique properties of PDMS allow for high resolution molds to be prepared from photolithographically defined substrates. Screen printing of electrically conductive PDMS into these molds with micro-sized features creates a low cost, flexible electronic package. We have coined this package PDMS-in-PDMS. We show that PDMS ECA can be prepared by curing a novel formulation of PDMS at curing temperatures of 150 °C for 15 minutes. Upon curing, the ECA undergoes a transition from insulating to conductive. TMA results have shown that this transition is due to ECA shrinkage >20%. Furthermore, we show simultaneous conductivity and tensile strain measurements to show the electrical properties of PDMS ECA are unaffected by tensile strains of >40%. We show the feasibility of this technology to create low cost, flexible devices without the need for metallization.
{"title":"Novel PDMS(silicone)-in-PDMS(silicone): Low cost flexible electronics without metallization","authors":"J. Agar, Katy J. Lin, Rongwei Zhang, J. Durden, K. Moon, C. Wong","doi":"10.1109/ECTC.2010.5490654","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490654","url":null,"abstract":"Future electronics will undoubtedly require natural integration at the system, device and package level in the form of a functional, flexible package. Functional, flexible electronics expand the functionality of devices allowing morphological-electronic response for ergonomic and natural interfaces between the device and its surroundings. Recent technological successes have been able to fabricate functional, flexible electronics, however have all failed to develop a package capable of meeting the stringent cost, reliability and performance required of consumer electronics. We demonstrate the application of electrically conductive adhesive technology to produce low cost, flexible electronics without metallization. We have shown the capability of fabrication of highly conductive Poly(dimethlysiloxane) (PDMS) (ρ~7×10−4 Ω•cm) by incorporation of 80 wt% bimodal distribution of micron sized silver flakes. PDMS is both the ideal substrate and composite matrix material due to its unique properties; PDMS is optically transparent, viscoelastic, chemically and thermally stable, highly flexible, hydrophobic and can easily be molded with high resolution and aspect ratio. These unique properties of PDMS allow for high resolution molds to be prepared from photolithographically defined substrates. Screen printing of electrically conductive PDMS into these molds with micro-sized features creates a low cost, flexible electronic package. We have coined this package PDMS-in-PDMS. We show that PDMS ECA can be prepared by curing a novel formulation of PDMS at curing temperatures of 150 °C for 15 minutes. Upon curing, the ECA undergoes a transition from insulating to conductive. TMA results have shown that this transition is due to ECA shrinkage >20%. Furthermore, we show simultaneous conductivity and tensile strain measurements to show the electrical properties of PDMS ECA are unaffected by tensile strains of >40%. We show the feasibility of this technology to create low cost, flexible devices without the need for metallization.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490655
J. Roberts, S. Hussain, M. Rahim, M. Motalab, J. Suhling, R. Jaeger, P. Lall, Ron Zhang
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.
{"title":"Characterization of microprocessor chip stress distributions during component packaging and thermal cycling","authors":"J. Roberts, S. Hussain, M. Rahim, M. Motalab, J. Suhling, R. Jaeger, P. Lall, Ron Zhang","doi":"10.1109/ECTC.2010.5490655","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490655","url":null,"abstract":"On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490713
Dong Wook Kim, J. K. J. Lee, Myung-June Lee, S. Pai, Stan Chen, F. Kuo
Eutectic PbSn solder joints assembled with CuSOP and ENEPIG surface finished substrates were tested at three different temperatures and input currents to predict EM life. Estimated EM life of CuSOP with PbSn solder system is 3 to 4 X longer than that of ENEPIG surface finish. Both EM failures in solder bumps are caused by void formation at the current crowding area and propagation mechanism, however, they exhibited two distinct failure modes. The Eutectic bump with ENEPIG finish failed due to the UBM over-consumption as a result of reaction of Ni with Sn while the EM failure of bumps assembled with CuSOP was caused by the crack created between bulk and Ni3Sn4 IMC. Nevertheless, the UBM was kept intact in the latter case. The difference of UBM consumption rate induced by Cu influx from the substrate is identified as the main reason of this performance difference. The failure mechanisms of both EM failures were proposed and discussed in details.
{"title":"Evaluation of electromigration (EM) life of ENEPIG and CuSOP surface finishes with various solder bump materials","authors":"Dong Wook Kim, J. K. J. Lee, Myung-June Lee, S. Pai, Stan Chen, F. Kuo","doi":"10.1109/ECTC.2010.5490713","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490713","url":null,"abstract":"Eutectic PbSn solder joints assembled with CuSOP and ENEPIG surface finished substrates were tested at three different temperatures and input currents to predict EM life. Estimated EM life of CuSOP with PbSn solder system is 3 to 4 X longer than that of ENEPIG surface finish. Both EM failures in solder bumps are caused by void formation at the current crowding area and propagation mechanism, however, they exhibited two distinct failure modes. The Eutectic bump with ENEPIG finish failed due to the UBM over-consumption as a result of reaction of Ni with Sn while the EM failure of bumps assembled with CuSOP was caused by the crack created between bulk and Ni3Sn4 IMC. Nevertheless, the UBM was kept intact in the latter case. The difference of UBM consumption rate induced by Cu influx from the substrate is identified as the main reason of this performance difference. The failure mechanisms of both EM failures were proposed and discussed in details.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116074869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490943
Zhaoqing Chen
A receiver macro modeling method is proposed. It includes the Mpilog macro model and the filter-preamplifier model which consists of small signal model followed by the hyperbolic-tangent function nonlinear post-processing. By using the directional junction model, we make use of the Mpilog model for receiver input port DC and nonlinear reflection properties, and make use of the small-signal/hyperbolic-tangent model for the output port of the preamplifier. Each model works at its own condition without unwanted interfering to each other. The assembled receiver macro model can be used in packaging system transient simulations directly. A practical modeling procedure in detail is described in the paper. The comparison between the proposed model and the original transistor-level model are given to evaluate the accuracy and simulation speed. Several application examples are also shown as test cases including high-end server packaging system transient simulations taking into account the crosstalk from the adjacent aggressor channels.
{"title":"Receiver macro modeling including DC, filter, and preamplifier nonlinear properties for packaging system transient simulations","authors":"Zhaoqing Chen","doi":"10.1109/ECTC.2010.5490943","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490943","url":null,"abstract":"A receiver macro modeling method is proposed. It includes the Mpilog macro model and the filter-preamplifier model which consists of small signal model followed by the hyperbolic-tangent function nonlinear post-processing. By using the directional junction model, we make use of the Mpilog model for receiver input port DC and nonlinear reflection properties, and make use of the small-signal/hyperbolic-tangent model for the output port of the preamplifier. Each model works at its own condition without unwanted interfering to each other. The assembled receiver macro model can be used in packaging system transient simulations directly. A practical modeling procedure in detail is described in the paper. The comparison between the proposed model and the original transistor-level model are given to evaluate the accuracy and simulation speed. Several application examples are also shown as test cases including high-end server packaging system transient simulations taking into account the crosstalk from the adjacent aggressor channels.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116618050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490772
S. Meyer, H. Wohlrabe, K. Wolter
Quality is major competitive advantages in today's business environment. Engineering tasks encompasses the assurance of quality and reliability. Therefore, one goal is the prediction and modeling of quality and later on reliability of systems, subsystems and components. An approach of quality and reliability assurance uses failure prevention and process control, which by itself is based on quality data and technological understanding. The bases for quality and reliability prediction are information about used materials, design parameters and process parameters as well as the underlying relationships. Analyzing these data for underlying relationships between control parameters (materials and process setups), monitoring parameters (such as humidity) and target variables is one approach to assure quality output. Within this paper neural networks for analyzing relationships are investigated. Two types of neural networks are investigated which are namely back propagation networks (BPNN) and secondly radial basis function networks (RBFNN). The test objects are BGA solder joints which are manufactured using different process setups and materials. As quality measure the ratio of voids in a solder joint is used. The criterion for good prediction quality is the ability of generalization of the depicted models when applying new data to it.
{"title":"Neural network modeling to predict quality and reliability for BGA solder joints","authors":"S. Meyer, H. Wohlrabe, K. Wolter","doi":"10.1109/ECTC.2010.5490772","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490772","url":null,"abstract":"Quality is major competitive advantages in today's business environment. Engineering tasks encompasses the assurance of quality and reliability. Therefore, one goal is the prediction and modeling of quality and later on reliability of systems, subsystems and components. An approach of quality and reliability assurance uses failure prevention and process control, which by itself is based on quality data and technological understanding. The bases for quality and reliability prediction are information about used materials, design parameters and process parameters as well as the underlying relationships. Analyzing these data for underlying relationships between control parameters (materials and process setups), monitoring parameters (such as humidity) and target variables is one approach to assure quality output. Within this paper neural networks for analyzing relationships are investigated. Two types of neural networks are investigated which are namely back propagation networks (BPNN) and secondly radial basis function networks (RBFNN). The test objects are BGA solder joints which are manufactured using different process setups and materials. As quality measure the ratio of voids in a solder joint is used. The criterion for good prediction quality is the ability of generalization of the depicted models when applying new data to it.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490643
L. Di Cioccio, P. Gueguen, Etienne Grouiller, L. Vandroux, V. Delaye, M. Rivoire, J. Lugand, L. Clavelier
Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.
{"title":"Vertical metal interconnect thanks to tungsten direct bonding","authors":"L. Di Cioccio, P. Gueguen, Etienne Grouiller, L. Vandroux, V. Delaye, M. Rivoire, J. Lugand, L. Clavelier","doi":"10.1109/ECTC.2010.5490643","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490643","url":null,"abstract":"Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116431111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490956
I. Kang, Gi-Jo Jung, Byoung-Yool Jeon, J. Yoo, Seong-Hun Jeong
Recently, System in Package (SiP) technology is rapidly evolved from a narrow set of applications to high volume applications on electronics markets, like small modules for mobile phone applications. Embedding technology is one of the solutions by embedding one or more chips into another chip or a substrate. In this study, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level flip-chip bonding technology, wafer level molding for under-filling and encapsulation by molding compound without any special substrate have been developed, including redistribution, solder and Cu bumping, thinning and ball mounting technology. Firstly to verify and optimize structure and materials through stress simulation for molded dies, maximum stress and its location have been confirmed and correlated with the result of reliability evaluation using molded die sample. The structure and materials for WL-eSiP has been optimized through molded die samples with evaluation of the reliability tests of MSL2a, PCT (121 °C/ 100%RH/ 2atm), TC (−40/125 °C) and HTS (150°C) in terms of various die size, dielectric and mold materials. Using the results achieved above, WL-eSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliabilities for verifying process and ensuring package reliability. Mother chip of 4mm × 4mm and daughter chip of 2.95mm × 2.31mm size have been designed in daisy chain pattern to be electrically interconnected each other. First of all, whole manufacturing process steps of wafer level embedded system in package (WL-eSiP) has been verified and developed, with redistribution, high aspect-ratio copper bumping, wafer level flip-chip bonding, wafer level molding, silicon and mold thinning and ball mounting technologies. Then, WL-eSiP has been fabricated for evaluation of package level reliability, MSL3, PCT (121°C/100%RH/ 2atm), TC (-40/125°C) and HTS (150°C) and all items have been passed. For the board level reliability test, daisy chain substrate has been designed and fabricated for TC (−40/125°C) and drop (1500G/ 0.5ms) tests. Besides, in order to increase the mother chip size from 16 mm2 to 36 mm2 for the expansion of application of WL-eSiP, stress improvement on each process step has been done through warpage and curvature evaluation on wafer level.
{"title":"Wafer level embedded System in Package (WL-eSiP) for mobile applications","authors":"I. Kang, Gi-Jo Jung, Byoung-Yool Jeon, J. Yoo, Seong-Hun Jeong","doi":"10.1109/ECTC.2010.5490956","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490956","url":null,"abstract":"Recently, System in Package (SiP) technology is rapidly evolved from a narrow set of applications to high volume applications on electronics markets, like small modules for mobile phone applications. Embedding technology is one of the solutions by embedding one or more chips into another chip or a substrate. In this study, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level flip-chip bonding technology, wafer level molding for under-filling and encapsulation by molding compound without any special substrate have been developed, including redistribution, solder and Cu bumping, thinning and ball mounting technology. Firstly to verify and optimize structure and materials through stress simulation for molded dies, maximum stress and its location have been confirmed and correlated with the result of reliability evaluation using molded die sample. The structure and materials for WL-eSiP has been optimized through molded die samples with evaluation of the reliability tests of MSL2a, PCT (121 °C/ 100%RH/ 2atm), TC (−40/125 °C) and HTS (150°C) in terms of various die size, dielectric and mold materials. Using the results achieved above, WL-eSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliabilities for verifying process and ensuring package reliability. Mother chip of 4mm × 4mm and daughter chip of 2.95mm × 2.31mm size have been designed in daisy chain pattern to be electrically interconnected each other. First of all, whole manufacturing process steps of wafer level embedded system in package (WL-eSiP) has been verified and developed, with redistribution, high aspect-ratio copper bumping, wafer level flip-chip bonding, wafer level molding, silicon and mold thinning and ball mounting technologies. Then, WL-eSiP has been fabricated for evaluation of package level reliability, MSL3, PCT (121°C/100%RH/ 2atm), TC (-40/125°C) and HTS (150°C) and all items have been passed. For the board level reliability test, daisy chain substrate has been designed and fabricated for TC (−40/125°C) and drop (1500G/ 0.5ms) tests. Besides, in order to increase the mother chip size from 16 mm2 to 36 mm2 for the expansion of application of WL-eSiP, stress improvement on each process step has been done through warpage and curvature evaluation on wafer level.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114711879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490907
P. Lall, R. Vaidya, V. More, K. Goebel, J. Suhling
Electronic systems are often stored for long periods prior to deployment in the intended environment. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subsequent to deployment. Prognostication of accrued damage and assessment of residual life is extremely critical for ultra-high reliability systems in which the cost of failure is too high. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. The methodology has been demonstrated on area-array ball-grid array test assemblies with Sn3Ag0.5Cu interconnects subjected to thermal aging at 125°C and thermal cycling from −55 to 125°C for various lengths of time and cycles. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Assemblies have been prognosticated to assess the error with interrogation of system state and assessment of residual life. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.
{"title":"Assessment of residual damage in leadfree electronics subjected to multiple thermal environments of thermal aging and thermal cycling","authors":"P. Lall, R. Vaidya, V. More, K. Goebel, J. Suhling","doi":"10.1109/ECTC.2010.5490907","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490907","url":null,"abstract":"Electronic systems are often stored for long periods prior to deployment in the intended environment. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subsequent to deployment. Prognostication of accrued damage and assessment of residual life is extremely critical for ultra-high reliability systems in which the cost of failure is too high. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. The methodology has been demonstrated on area-array ball-grid array test assemblies with Sn3Ag0.5Cu interconnects subjected to thermal aging at 125°C and thermal cycling from −55 to 125°C for various lengths of time and cycles. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Assemblies have been prognosticated to assess the error with interrogation of system state and assessment of residual life. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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