Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490713
Dong Wook Kim, J. K. J. Lee, Myung-June Lee, S. Pai, Stan Chen, F. Kuo
Eutectic PbSn solder joints assembled with CuSOP and ENEPIG surface finished substrates were tested at three different temperatures and input currents to predict EM life. Estimated EM life of CuSOP with PbSn solder system is 3 to 4 X longer than that of ENEPIG surface finish. Both EM failures in solder bumps are caused by void formation at the current crowding area and propagation mechanism, however, they exhibited two distinct failure modes. The Eutectic bump with ENEPIG finish failed due to the UBM over-consumption as a result of reaction of Ni with Sn while the EM failure of bumps assembled with CuSOP was caused by the crack created between bulk and Ni3Sn4 IMC. Nevertheless, the UBM was kept intact in the latter case. The difference of UBM consumption rate induced by Cu influx from the substrate is identified as the main reason of this performance difference. The failure mechanisms of both EM failures were proposed and discussed in details.
{"title":"Evaluation of electromigration (EM) life of ENEPIG and CuSOP surface finishes with various solder bump materials","authors":"Dong Wook Kim, J. K. J. Lee, Myung-June Lee, S. Pai, Stan Chen, F. Kuo","doi":"10.1109/ECTC.2010.5490713","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490713","url":null,"abstract":"Eutectic PbSn solder joints assembled with CuSOP and ENEPIG surface finished substrates were tested at three different temperatures and input currents to predict EM life. Estimated EM life of CuSOP with PbSn solder system is 3 to 4 X longer than that of ENEPIG surface finish. Both EM failures in solder bumps are caused by void formation at the current crowding area and propagation mechanism, however, they exhibited two distinct failure modes. The Eutectic bump with ENEPIG finish failed due to the UBM over-consumption as a result of reaction of Ni with Sn while the EM failure of bumps assembled with CuSOP was caused by the crack created between bulk and Ni3Sn4 IMC. Nevertheless, the UBM was kept intact in the latter case. The difference of UBM consumption rate induced by Cu influx from the substrate is identified as the main reason of this performance difference. The failure mechanisms of both EM failures were proposed and discussed in details.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116074869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490820
B. Dang, P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, J. Knickerbocker
This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput at low cost. Using pulsed ultraviolet (UV) radiation from excimer lasers, device wafers as thin as 50µm can be released from the temporary mechanical handler wafer in less than 1min. Bonding, adhesive, debonding and post debond clean processes were demonstrated. CMOS circuit test vehicles were shown to be compatible with this temporary bonding and debonding processes.
{"title":"CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration","authors":"B. Dang, P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, J. Knickerbocker","doi":"10.1109/ECTC.2010.5490820","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490820","url":null,"abstract":"This paper reports a thin wafer handling technology that is compatible to CMOS processing conditions to enable 3D integration and assembly with high throughput at low cost. Using pulsed ultraviolet (UV) radiation from excimer lasers, device wafers as thin as 50µm can be released from the temporary mechanical handler wafer in less than 1min. Bonding, adhesive, debonding and post debond clean processes were demonstrated. CMOS circuit test vehicles were shown to be compatible with this temporary bonding and debonding processes.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124925976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490907
P. Lall, R. Vaidya, V. More, K. Goebel, J. Suhling
Electronic systems are often stored for long periods prior to deployment in the intended environment. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subsequent to deployment. Prognostication of accrued damage and assessment of residual life is extremely critical for ultra-high reliability systems in which the cost of failure is too high. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. The methodology has been demonstrated on area-array ball-grid array test assemblies with Sn3Ag0.5Cu interconnects subjected to thermal aging at 125°C and thermal cycling from −55 to 125°C for various lengths of time and cycles. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Assemblies have been prognosticated to assess the error with interrogation of system state and assessment of residual life. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.
{"title":"Assessment of residual damage in leadfree electronics subjected to multiple thermal environments of thermal aging and thermal cycling","authors":"P. Lall, R. Vaidya, V. More, K. Goebel, J. Suhling","doi":"10.1109/ECTC.2010.5490907","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490907","url":null,"abstract":"Electronic systems are often stored for long periods prior to deployment in the intended environment. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subsequent to deployment. Prognostication of accrued damage and assessment of residual life is extremely critical for ultra-high reliability systems in which the cost of failure is too high. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. The methodology has been demonstrated on area-array ball-grid array test assemblies with Sn3Ag0.5Cu interconnects subjected to thermal aging at 125°C and thermal cycling from −55 to 125°C for various lengths of time and cycles. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Assemblies have been prognosticated to assess the error with interrogation of system state and assessment of residual life. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490739
O. Hildreth, C. Álvarez, C. Wong
This paper demonstrates the use of tungsten as a viable, low cost catalyst for Metal-assisted Chemical Etching (MaCE) of silicon to create high aspect ratio nanostructures in silicon. The effect of etchant composition and etching time is reported along with Scanning Electron Microscope (SEM) and Atomic Force Microscopy (AFM) images confirming that tungsten acted as a catalyst for MaCE.
{"title":"Tungsten as a CMOS compatible catalyst for the Metal-assisted Chemical Etching of silicon to create 2D and 3D nanostructures","authors":"O. Hildreth, C. Álvarez, C. Wong","doi":"10.1109/ECTC.2010.5490739","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490739","url":null,"abstract":"This paper demonstrates the use of tungsten as a viable, low cost catalyst for Metal-assisted Chemical Etching (MaCE) of silicon to create high aspect ratio nanostructures in silicon. The effect of etchant composition and etching time is reported along with Scanning Electron Microscope (SEM) and Atomic Force Microscopy (AFM) images confirming that tungsten acted as a catalyst for MaCE.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122072016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490936
Yinghui Wang, T. Suga
The influence of bonding atmosphere was investigated for the wafer bonding at 25~200°C using a surface activated bonding method. The results of the analysis of activated Si surfaces under different vacuum background and the residual gases in vacuum before and after Ar fast atom beam irradiation is reported. Based on the analysis, bonding of Si wafers in nitrogen atmosphere is demonstrated with showing the effect of the timing of nitrogen introduction into the bonding chamber. The bonding energy of the bonded Si-Si wafer may reach 2 J/m2 under the vacuum pressure of 5 × 10−5 Pa and N2 atmosphere by controlling the exposure time and the residual gas of water to less than 5 × 10−4 Pa-s. Using Au or Cu thin-films can reduce the influence of bonding atmosphere. Bond interfaces with few voids can be achieved, which is benefit on diffusion and plastic deformation of the Au or Cu thin-films.
{"title":"Influence of bonding atmosphere on low-temperature wafer bonding","authors":"Yinghui Wang, T. Suga","doi":"10.1109/ECTC.2010.5490936","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490936","url":null,"abstract":"The influence of bonding atmosphere was investigated for the wafer bonding at 25~200°C using a surface activated bonding method. The results of the analysis of activated Si surfaces under different vacuum background and the residual gases in vacuum before and after Ar fast atom beam irradiation is reported. Based on the analysis, bonding of Si wafers in nitrogen atmosphere is demonstrated with showing the effect of the timing of nitrogen introduction into the bonding chamber. The bonding energy of the bonded Si-Si wafer may reach 2 J/m2 under the vacuum pressure of 5 × 10−5 Pa and N2 atmosphere by controlling the exposure time and the residual gas of water to less than 5 × 10−4 Pa-s. Using Au or Cu thin-films can reduce the influence of bonding atmosphere. Bond interfaces with few voids can be achieved, which is benefit on diffusion and plastic deformation of the Au or Cu thin-films.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122167234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490649
Minghui Sun, Zhiyong Xiao, Y. Chai, Yuan Li, P. Chan
In this study, we investigated the inductance properties of as-grown horizontal MWNT arrays with different length and width combinations. Statistical data processing was employed to explore the relationship between kinetic inductance and dimension of CNT arrays. We have experimentally confirmed that kinetic inductance forward scales with the length of CNTs and reversely scales with the number of CNTs in parallel. This work provides a systematic experimental study of CNT kinetic inductance and provides useful data for further investigating the possibility of using CNT-based inductors in RFIC.
{"title":"Inductance properties of silicon-in-grown horizontal carbon nanotubes","authors":"Minghui Sun, Zhiyong Xiao, Y. Chai, Yuan Li, P. Chan","doi":"10.1109/ECTC.2010.5490649","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490649","url":null,"abstract":"In this study, we investigated the inductance properties of as-grown horizontal MWNT arrays with different length and width combinations. Statistical data processing was employed to explore the relationship between kinetic inductance and dimension of CNT arrays. We have experimentally confirmed that kinetic inductance forward scales with the length of CNTs and reversely scales with the number of CNTs in parallel. This work provides a systematic experimental study of CNT kinetic inductance and provides useful data for further investigating the possibility of using CNT-based inductors in RFIC.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":" 41","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113947133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490772
S. Meyer, H. Wohlrabe, K. Wolter
Quality is major competitive advantages in today's business environment. Engineering tasks encompasses the assurance of quality and reliability. Therefore, one goal is the prediction and modeling of quality and later on reliability of systems, subsystems and components. An approach of quality and reliability assurance uses failure prevention and process control, which by itself is based on quality data and technological understanding. The bases for quality and reliability prediction are information about used materials, design parameters and process parameters as well as the underlying relationships. Analyzing these data for underlying relationships between control parameters (materials and process setups), monitoring parameters (such as humidity) and target variables is one approach to assure quality output. Within this paper neural networks for analyzing relationships are investigated. Two types of neural networks are investigated which are namely back propagation networks (BPNN) and secondly radial basis function networks (RBFNN). The test objects are BGA solder joints which are manufactured using different process setups and materials. As quality measure the ratio of voids in a solder joint is used. The criterion for good prediction quality is the ability of generalization of the depicted models when applying new data to it.
{"title":"Neural network modeling to predict quality and reliability for BGA solder joints","authors":"S. Meyer, H. Wohlrabe, K. Wolter","doi":"10.1109/ECTC.2010.5490772","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490772","url":null,"abstract":"Quality is major competitive advantages in today's business environment. Engineering tasks encompasses the assurance of quality and reliability. Therefore, one goal is the prediction and modeling of quality and later on reliability of systems, subsystems and components. An approach of quality and reliability assurance uses failure prevention and process control, which by itself is based on quality data and technological understanding. The bases for quality and reliability prediction are information about used materials, design parameters and process parameters as well as the underlying relationships. Analyzing these data for underlying relationships between control parameters (materials and process setups), monitoring parameters (such as humidity) and target variables is one approach to assure quality output. Within this paper neural networks for analyzing relationships are investigated. Two types of neural networks are investigated which are namely back propagation networks (BPNN) and secondly radial basis function networks (RBFNN). The test objects are BGA solder joints which are manufactured using different process setups and materials. As quality measure the ratio of voids in a solder joint is used. The criterion for good prediction quality is the ability of generalization of the depicted models when applying new data to it.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490722
R. Saha, N. Fritz, S. Bidstrup-Allen, P. Kohl
Air-gap structures are of interest in a range of microelectronic applications especially in microelectromechanical systems (MEMS). In this work, we investigate the application of an unique trimaterial for MEMS packaging composed of polypropylene carbonate (PPC) as a sacrificial material, a photosensitive, hybrid inorganic/organic dielectric epoxycyclohexyl polyhedral oligomeric silsesquioxanes (POSS) as the overcoat material, and Al/Cr-Cu thin metal film as a hermetic seal. POSS was used both for patterning the PPC over the structures as well as a stable overcoat material thus reducing the complexity of the fabrication process. A wide range of device sizes and structures (from 20 × 100 µm to 600 × 1000 µm) were fabricated and the processing protocol was found to be compliant over these size/structure variations. Metal adhesion on the overcoat was substantially improved by using low power oxygen plasma for short durations. Cavity-strength was evaluated for different metals and thicknesses. An increase of 5.6 times in cavity-strength was observed for a thicker (3X) Al metal film. Current work is focused on implementing the wafer-level air-cavity package into a lead frame packaged MEMS device through injection and compression molding techniques.
{"title":"Three dimensional air-gap structures for MEMS packaging","authors":"R. Saha, N. Fritz, S. Bidstrup-Allen, P. Kohl","doi":"10.1109/ECTC.2010.5490722","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490722","url":null,"abstract":"Air-gap structures are of interest in a range of microelectronic applications especially in microelectromechanical systems (MEMS). In this work, we investigate the application of an unique trimaterial for MEMS packaging composed of polypropylene carbonate (PPC) as a sacrificial material, a photosensitive, hybrid inorganic/organic dielectric epoxycyclohexyl polyhedral oligomeric silsesquioxanes (POSS) as the overcoat material, and Al/Cr-Cu thin metal film as a hermetic seal. POSS was used both for patterning the PPC over the structures as well as a stable overcoat material thus reducing the complexity of the fabrication process. A wide range of device sizes and structures (from 20 × 100 µm to 600 × 1000 µm) were fabricated and the processing protocol was found to be compliant over these size/structure variations. Metal adhesion on the overcoat was substantially improved by using low power oxygen plasma for short durations. Cavity-strength was evaluated for different metals and thicknesses. An increase of 5.6 times in cavity-strength was observed for a thicker (3X) Al metal film. Current work is focused on implementing the wafer-level air-cavity package into a lead frame packaged MEMS device through injection and compression molding techniques.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129264757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490764
A. Roesler, J. Schare, Chad Hettler, D. Abel, G. Slama, D. Schofield
This paper discusses a new approach to making hybrid power electronic circuits by combining a low-temperature (850°C to 950°C) co-fired ceramic (LTCC) substrate, planar LTCC ferrite transformers/inductors and integrated passive components into a multilayer monolithic package using a ferrite-based LTCC material system. A ferrite tape functions as the base material for this LTCC system. The material system includes physically and chemically compatible dielectric paste, dielectric tape and conductor materials which can be co-fired with the base ferrite LTCC tape to create sintered devices with excellent magnetic coupling, high permeability (~400), high resistivity (> 1012 Ω·cm) and good saturation (~0.3 T). The co-fired ferrite and dielectric materials can be used as a substrate for attaching or housing semiconductor components and other discrete devices that are part of the power electronics system. Furthermore, the ability to co-fire the ferrite with dielectric and conductor materials allows for the incorporation of embedded passives in the multilayer structure to create hybrid power electronic circuits. Overall this thick film material set offers a unique approach to making hybrid power electronics and could potentially allow a size reduction for many commercial dc-dc converter and other power electronic circuits.
{"title":"Integrated power electronics using a ferrite-based low-temperature co-fired ceramic materials system","authors":"A. Roesler, J. Schare, Chad Hettler, D. Abel, G. Slama, D. Schofield","doi":"10.1109/ECTC.2010.5490764","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490764","url":null,"abstract":"This paper discusses a new approach to making hybrid power electronic circuits by combining a low-temperature (850°C to 950°C) co-fired ceramic (LTCC) substrate, planar LTCC ferrite transformers/inductors and integrated passive components into a multilayer monolithic package using a ferrite-based LTCC material system. A ferrite tape functions as the base material for this LTCC system. The material system includes physically and chemically compatible dielectric paste, dielectric tape and conductor materials which can be co-fired with the base ferrite LTCC tape to create sintered devices with excellent magnetic coupling, high permeability (~400), high resistivity (> 1012 Ω·cm) and good saturation (~0.3 T). The co-fired ferrite and dielectric materials can be used as a substrate for attaching or housing semiconductor components and other discrete devices that are part of the power electronics system. Furthermore, the ability to co-fire the ferrite with dielectric and conductor materials allows for the incorporation of embedded passives in the multilayer structure to create hybrid power electronic circuits. Overall this thick film material set offers a unique approach to making hybrid power electronics and could potentially allow a size reduction for many commercial dc-dc converter and other power electronic circuits.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490767
P. Su, Boaz Khan, Min Ding
Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.
{"title":"An evaluation of die crack risk of over-molded packages due to external impact","authors":"P. Su, Boaz Khan, Min Ding","doi":"10.1109/ECTC.2010.5490767","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490767","url":null,"abstract":"Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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