Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490700
K. Moon, D. Staiculescu, S. Kim, Z. Liu, H. Chan, V. Sundaram, R. Tummala, C. Wong
Adhesives used for mechanical bonding and electrical/thermal transport in high performance electronic packages require high adhesion strength and electrical properties at elevated temperatures. Adhesion strengths of electrically/thermally conductive adhesives on Ni, Cu and Sn surfaces at room temperature and elevated temperature (100 °C) were studied. Their high temperature adhesion strengths on those metal surfaces were improved by surface pretreatment with an adhesion promoter (AP). The Tg > 100 °C and the low coefficient of thermal expansion (CTE) of the ECA help maintain the low thermal coefficient of resistance (TCR) at 100 °C similar to that of bulk silver. High frequency properties of the ECA at an elevated temperature are presented and show great stability of the insertion loss in the 1 to 8 GHz frequency range. Also, the ECA shows good high frequency performance compared with Cu.
{"title":"Adhesion and RF properties of electrically conductive adhesives","authors":"K. Moon, D. Staiculescu, S. Kim, Z. Liu, H. Chan, V. Sundaram, R. Tummala, C. Wong","doi":"10.1109/ECTC.2010.5490700","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490700","url":null,"abstract":"Adhesives used for mechanical bonding and electrical/thermal transport in high performance electronic packages require high adhesion strength and electrical properties at elevated temperatures. Adhesion strengths of electrically/thermally conductive adhesives on Ni, Cu and Sn surfaces at room temperature and elevated temperature (100 °C) were studied. Their high temperature adhesion strengths on those metal surfaces were improved by surface pretreatment with an adhesion promoter (AP). The Tg > 100 °C and the low coefficient of thermal expansion (CTE) of the ECA help maintain the low thermal coefficient of resistance (TCR) at 100 °C similar to that of bulk silver. High frequency properties of the ECA at an elevated temperature are presented and show great stability of the insertion loss in the 1 to 8 GHz frequency range. Also, the ECA shows good high frequency performance compared with Cu.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"44 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490878
K. Mori, K. Kikuchi, D. Ohshima, Y. Nakashima, S. Yamamichi
We have previously reported the technology for embedding a 1500-pin microprocessor chip in a thin LSI package using a rigid Cu plate. The reliabilities of this seamless package with the direct interconnection between the LSI chip and substrate wiring have now been evaluated at the package and board levels. The package passed all the LSI function tests at the package level even after 2000 thermal cycles. The microstructure of the interconnect, evaluated using electron backscatter diffraction and transmission electron microscopy, showed a high interconnect reliability. The reliability at the board level was evaluated using the thermal cycles testing, the shadow-moiré method and strain gauge measurement with the package mounted on a system board. Thanks to the Cu plate, the warpage and strain characteristics are excellent, resulting in uniform stress distribution. Therefore, this seamless packaging technology is promising for the fabrication of thin, highly reliable LSI packages for replacing flip chip ball grid array packages.
{"title":"Reliability of thin seamless package with embedded high-pin-count LSI chip","authors":"K. Mori, K. Kikuchi, D. Ohshima, Y. Nakashima, S. Yamamichi","doi":"10.1109/ECTC.2010.5490878","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490878","url":null,"abstract":"We have previously reported the technology for embedding a 1500-pin microprocessor chip in a thin LSI package using a rigid Cu plate. The reliabilities of this seamless package with the direct interconnection between the LSI chip and substrate wiring have now been evaluated at the package and board levels. The package passed all the LSI function tests at the package level even after 2000 thermal cycles. The microstructure of the interconnect, evaluated using electron backscatter diffraction and transmission electron microscopy, showed a high interconnect reliability. The reliability at the board level was evaluated using the thermal cycles testing, the shadow-moiré method and strain gauge measurement with the package mounted on a system board. Thanks to the Cu plate, the warpage and strain characteristics are excellent, resulting in uniform stress distribution. Therefore, this seamless packaging technology is promising for the fabrication of thin, highly reliable LSI packages for replacing flip chip ball grid array packages.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"27 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132374537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490766
M. W. Lee, Jin Young Kim, Jae Dong Kim, Choonheung Lee
In this paper, the FEM based various parametric studies such as packaging material and structural effects, under bump metallization and passivation structures and material property effects on the low k layer are investigated for the flip-chip packaging with Cu pillar interconnection. The results showed that the stress of the low k layer is directly concerned wirh the CTE mismatch between low k die and substrate constrained by Cu pillar and maximized at the bump near the die corner after flip chip attach process before underfill. The stress contour shows that the low k area is affected by both tensile stress and compressive stress. The experimentally inspected low k damaged area showed half moon shape which reveals the failure mode is closely related with the tensile stress near the Al to Cu pillar interface. The comparison results show that the Cu pillar has 20% higher stress than lead free solder and 40% than eutectic solder case. The structural DOE shows that the reducing flip-chip die and substrate thickness and also reducing passivation opening cases showed effective for reducing low k stress after flip chip attach. After underfill and mold or MUF only process, stress change of low k layer showed good agreement to the CTE variation of underfill or MUF which means thermal expansion of underfill / MUF is governing factor for low k stress for the after assembly. Compared with CUF, MUF which has lower CTE than CUF showed relatively lower stress on the low k layer. By applying optimized structure and material properties of package, UBM and passivation layers, the stress of the low k layer can be reduced to the relatively safe level where the stress is lower than the eutectic solder applied case of the reference structure.
{"title":"Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping","authors":"M. W. Lee, Jin Young Kim, Jae Dong Kim, Choonheung Lee","doi":"10.1109/ECTC.2010.5490766","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490766","url":null,"abstract":"In this paper, the FEM based various parametric studies such as packaging material and structural effects, under bump metallization and passivation structures and material property effects on the low k layer are investigated for the flip-chip packaging with Cu pillar interconnection. The results showed that the stress of the low k layer is directly concerned wirh the CTE mismatch between low k die and substrate constrained by Cu pillar and maximized at the bump near the die corner after flip chip attach process before underfill. The stress contour shows that the low k area is affected by both tensile stress and compressive stress. The experimentally inspected low k damaged area showed half moon shape which reveals the failure mode is closely related with the tensile stress near the Al to Cu pillar interface. The comparison results show that the Cu pillar has 20% higher stress than lead free solder and 40% than eutectic solder case. The structural DOE shows that the reducing flip-chip die and substrate thickness and also reducing passivation opening cases showed effective for reducing low k stress after flip chip attach. After underfill and mold or MUF only process, stress change of low k layer showed good agreement to the CTE variation of underfill or MUF which means thermal expansion of underfill / MUF is governing factor for low k stress for the after assembly. Compared with CUF, MUF which has lower CTE than CUF showed relatively lower stress on the low k layer. By applying optimized structure and material properties of package, UBM and passivation layers, the stress of the low k layer can be reduced to the relatively safe level where the stress is lower than the eutectic solder applied case of the reference structure.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132447680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490938
D. Frye, R. Guino, S. Gupta, M. Sano, K. Sato, K. Iida
Flip chip bonding requires a device to be flipped and attached to the bond pads or traces on the substrate. For lower pitch devices with large bond pads, this was accomplished using gravity reflow followed by capillary underfill (CUF). For fine-pitch devices mounted close to each other on a substrate, CUF has not been as effective as the use of a Non-conductive paste (NCP) during Thermal Compression Bonding (TCB). The NCP provides reliability during post bonding testing and ensures a strong die to substrate bonding. The authors will describe the formulation of a new NCP that provides fast, reliable bonding for Copper Pillar and Gold Gold bonding.
{"title":"Gold-Gold Interconnects to Copper Pillar using fast Thermal Compression Bonding using Non-conductive paste","authors":"D. Frye, R. Guino, S. Gupta, M. Sano, K. Sato, K. Iida","doi":"10.1109/ECTC.2010.5490938","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490938","url":null,"abstract":"Flip chip bonding requires a device to be flipped and attached to the bond pads or traces on the substrate. For lower pitch devices with large bond pads, this was accomplished using gravity reflow followed by capillary underfill (CUF). For fine-pitch devices mounted close to each other on a substrate, CUF has not been as effective as the use of a Non-conductive paste (NCP) during Thermal Compression Bonding (TCB). The NCP provides reliability during post bonding testing and ensures a strong die to substrate bonding. The authors will describe the formulation of a new NCP that provides fast, reliable bonding for Copper Pillar and Gold Gold bonding.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131954557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490657
I. Nnebe, Soojae Park, C. Feger
Finite element models are greatly relied on by the packaging community to predict stresses that develop within microelectronic packages. While of great value, model predictions do not always accurately predict or explain package failures. Particularly, there has been much discussion about which models best describe the behavior of polymeric composites such as the underfill. Additionally, current models do not account for material heterogeneity and non-perfect geometries which are conditions commonly seen in real packages. How such imperfections impact local stresses that often drive failure is unknown. We therefore present a method of directly measuring local stresses in the underfill region using carbon nanotubes as sensors and show how this method can be used to improve finite element models and to assess the impact of conditions that are difficult to model.
{"title":"Direct measurement of local stress in first-level flip-chip organic packages","authors":"I. Nnebe, Soojae Park, C. Feger","doi":"10.1109/ECTC.2010.5490657","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490657","url":null,"abstract":"Finite element models are greatly relied on by the packaging community to predict stresses that develop within microelectronic packages. While of great value, model predictions do not always accurately predict or explain package failures. Particularly, there has been much discussion about which models best describe the behavior of polymeric composites such as the underfill. Additionally, current models do not account for material heterogeneity and non-perfect geometries which are conditions commonly seen in real packages. How such imperfections impact local stresses that often drive failure is unknown. We therefore present a method of directly measuring local stresses in the underfill region using carbon nanotubes as sensors and show how this method can be used to improve finite element models and to assess the impact of conditions that are difficult to model.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132020612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490898
L. D. Chen, M. Huang, S. M. Zhou
In this study, the line-type Cu/Sn/Cu and Cu/Sn/Ni interconnects were used to determine the growth kinetics of interfacial intermetallic compounds (IMCs) under electromigration (EM), and the current crowding effect and thermomigration are expected to be avoided in this line-type interconnects because of their symmetric structure. The Cu/Sn/Cu interconnect was under the current density of 5.0×103 A/cm2 at 100 °C and 150 °C, and the Cu/Sn/Ni interconnect was under the same current density at 150 °C. For the purpose of comparison, the Cu/Sn/Cu and Cu/Sn/Ni interconnects were aged at the same temperatures for the same durations. In the case of Cu/Sn/Cu interconnect, the same types of IMCs, Cu6Sn5 and Cu3Sn, formed at the Sn/Cu interface, which was independent of electric current. EM caused a polarity effect, i.e., the interfacial IMCs on the anode side were significantly thicker than those on the cathode side. The growth kinetics of the interfacial IMCs on the anode side during EM were significantly enhanced compared with that of the aging (the no-current case), and still followed a t1/2 law with time. The temperature was one of the critical factors that influenced the EM. The effect of EM became more significant at higher temperature under the same current density. The growth behavior of the interfacial IMCs on the cathode sides was complicated. When the initial interfacial IMCs were very thin, the inward atomic fluxes were larger than the outward fluxes and thus the interfacial IMCs grew. After the IMCs reached a critical thickness, the inward atomic fluxes were less than the outward fluxes and thus the thickness of the interfacial IMCs decreased. In the case of Cu/Sn/Ni interconnects, Ni3Sn4 and Cu6Sn5 IMCs formed at the as-soldered Sn/Ni and Sn/Cu interfaces, respectively. The Cu content in the IMCs at the Sn/Ni interface increased with the increasing aging time, and the original Ni3Sn4 IMC at the Sn/Ni interface transformed into (Cu0.56Ni0.44)6Sn5 after aging at 150 °C for 200h; while the IMC at the Sn/Cu interface remained Cu6Sn5, which contained less than 0.5 at% Ni even after aging at 150 °C for 200h. When electrons flowed from Cu side to Ni side in the Cu/Sn/Ni interconnects during EM at 150 °C, the original interfacial Ni3Sn4 IMC at the Sn/Ni interface (anode side) had already transformed into (CuNi)6Sn5 type after EM for 100h. After EM for 200h, (Cu0.60Ni0.40)6Sn5 formed at the Sn/Ni interface and Cu6Sn5 (containing less than 0.1 at% Ni) formed at the Sn/Cu interface. When the direction of electron flow was reversed, after EM at 150 °C for 200h, the types of IMCs remained unchanged, i.e., Ni3Sn4 (containing 2 at% Cu
{"title":"Effect of electromigration on intermetallic compound formation in line-type Cu/Sn/Cu and Cu/Sn/Ni interconnects","authors":"L. D. Chen, M. Huang, S. M. Zhou","doi":"10.1109/ECTC.2010.5490898","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490898","url":null,"abstract":"In this study, the line-type Cu/Sn/Cu and Cu/Sn/Ni interconnects were used to determine the growth kinetics of interfacial intermetallic compounds (IMCs) under electromigration (EM), and the current crowding effect and thermomigration are expected to be avoided in this line-type interconnects because of their symmetric structure. The Cu/Sn/Cu interconnect was under the current density of 5.0×10<sup>3</sup> A/cm<sup>2</sup> at 100 °C and 150 °C, and the Cu/Sn/Ni interconnect was under the same current density at 150 °C. For the purpose of comparison, the Cu/Sn/Cu and Cu/Sn/Ni interconnects were aged at the same temperatures for the same durations. In the case of Cu/Sn/Cu interconnect, the same types of IMCs, Cu<inf>6</inf>Sn<inf>5</inf> and Cu<inf>3</inf>Sn, formed at the Sn/Cu interface, which was independent of electric current. EM caused a polarity effect, i.e., the interfacial IMCs on the anode side were significantly thicker than those on the cathode side. The growth kinetics of the interfacial IMCs on the anode side during EM were significantly enhanced compared with that of the aging (the no-current case), and still followed a t<sup>1/2</sup> law with time. The temperature was one of the critical factors that influenced the EM. The effect of EM became more significant at higher temperature under the same current density. The growth behavior of the interfacial IMCs on the cathode sides was complicated. When the initial interfacial IMCs were very thin, the inward atomic fluxes were larger than the outward fluxes and thus the interfacial IMCs grew. After the IMCs reached a critical thickness, the inward atomic fluxes were less than the outward fluxes and thus the thickness of the interfacial IMCs decreased. In the case of Cu/Sn/Ni interconnects, Ni<inf>3</inf>Sn<inf>4</inf> and Cu<inf>6</inf>Sn<inf>5</inf> IMCs formed at the as-soldered Sn/Ni and Sn/Cu interfaces, respectively. The Cu content in the IMCs at the Sn/Ni interface increased with the increasing aging time, and the original Ni<inf>3</inf>Sn<inf>4</inf> IMC at the Sn/Ni interface transformed into (Cu<inf>0.56</inf>Ni<inf>0.44</inf>)<inf>6</inf>Sn<inf>5</inf> after aging at 150 °C for 200h; while the IMC at the Sn/Cu interface remained Cu<inf>6</inf>Sn<inf>5</inf>, which contained less than 0.5 at% Ni even after aging at 150 °C for 200h. When electrons flowed from Cu side to Ni side in the Cu/Sn/Ni interconnects during EM at 150 °C, the original interfacial Ni<inf>3</inf>Sn<inf>4</inf> IMC at the Sn/Ni interface (anode side) had already transformed into (CuNi)<inf>6</inf>Sn<inf>5</inf> type after EM for 100h. After EM for 200h, (Cu<inf>0.60</inf>Ni<inf>0.40</inf>)<inf>6</inf>Sn<inf>5</inf> formed at the Sn/Ni interface and Cu<inf>6</inf>Sn<inf>5</inf> (containing less than 0.1 at% Ni) formed at the Sn/Cu interface. When the direction of electron flow was reversed, after EM at 150 °C for 200h, the types of IMCs remained unchanged, i.e., Ni<inf>3</inf>Sn<inf>4</inf> (containing 2 at% Cu","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132154551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490706
H. Shin, J. Song, Jin Yu
Nano-interconnection technology is expected to replace some part of solder bump technology of electronic packaging in near future. Metallic nanowires (NWs) are one of the candidates for the electrical interconnection materials. In this study, as a well-known material for the interconnection in the electronic packaging, Sn was selected for the application to nano-interconnection technology. Since the physical properties of Sn NWs are important for the interconnection applications, we have already reported the size-dependency of melting behaviors and lattice parameters of single crystalline Sn NWs. In this study, the effects of the NW microstructure and the kinds of templates, which were used for the growth of Sn NWs, on the lattice parameter were investigated. Results showed that the single crystalline Sn NWs were elongated along the longitudinal direction up to 0.64 % depending upon their microstructures and kinds of the templates. The nanowire elongation was gradually reduced when the NW microstructure were single crystalline, granular, and bamboolike structures, in sequence.
{"title":"Lattice deformation of Sn nanowires for the application to nano-interconnection technology","authors":"H. Shin, J. Song, Jin Yu","doi":"10.1109/ECTC.2010.5490706","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490706","url":null,"abstract":"Nano-interconnection technology is expected to replace some part of solder bump technology of electronic packaging in near future. Metallic nanowires (NWs) are one of the candidates for the electrical interconnection materials. In this study, as a well-known material for the interconnection in the electronic packaging, Sn was selected for the application to nano-interconnection technology. Since the physical properties of Sn NWs are important for the interconnection applications, we have already reported the size-dependency of melting behaviors and lattice parameters of single crystalline Sn NWs. In this study, the effects of the NW microstructure and the kinds of templates, which were used for the growth of Sn NWs, on the lattice parameter were investigated. Results showed that the single crystalline Sn NWs were elongated along the longitudinal direction up to 0.64 % depending upon their microstructures and kinds of the templates. The nanowire elongation was gradually reduced when the NW microstructure were single crystalline, granular, and bamboolike structures, in sequence.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130262185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490823
M. K. Chowdhury, Li Sun, S. Cunningham, A. Malshe
The purpose of this paper is to present new findings in process variability for wet chemical etching and subsequent plasma cleaning of mechanically punched micro vias fabricated in liquid crystal polymer (LCP) substrate. It was observed that the micro-mechanical punching process tends to form a LCP burr inside the through via, and form a copper burr on the bottom copper layer. The bottom copper layer is pre-laminated in ULTRALAM 3850, supplied by Rogers Corporation. An experimental procedure was designed to remove LCP and copper burr by chemical etching method. It was found that the conventional method of etching polymeric materials by strong base like KOH or NaOH does not work for LCP due to its high chemical resistance. Hence, the LCP surface had to be functionalized by using a strong oxidizer (NaKMnO4) before starting conventional chemical etching by a strong base solution. A systematic approach has been developed to etch out the LCP and copper burr formation during the punching process. After examining three different experimental matrices it was found that a sequential treatment by oxidizer (NaKMnO4), etchant (NaOH), and neutralizer (3%H2SO4 + 3%H2O2) gave the best results during the etching process. Considerable improvements were made on LCP and copper burr removal process using the wet chemical treatments including the development of an oxygen plasma treatment to clean the carbonated LCP debris produced during chemical etching. It was found that a subsequent oxygen plasma treatment after the wet chemical processes provided the cleanest through vias for interconnection on LCP substrates.
{"title":"Investigation of chemical de-burring and subsequent plasma cleaning of mechanically punched micro via array fabricated in LCP substrate","authors":"M. K. Chowdhury, Li Sun, S. Cunningham, A. Malshe","doi":"10.1109/ECTC.2010.5490823","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490823","url":null,"abstract":"The purpose of this paper is to present new findings in process variability for wet chemical etching and subsequent plasma cleaning of mechanically punched micro vias fabricated in liquid crystal polymer (LCP) substrate. It was observed that the micro-mechanical punching process tends to form a LCP burr inside the through via, and form a copper burr on the bottom copper layer. The bottom copper layer is pre-laminated in ULTRALAM 3850, supplied by Rogers Corporation. An experimental procedure was designed to remove LCP and copper burr by chemical etching method. It was found that the conventional method of etching polymeric materials by strong base like KOH or NaOH does not work for LCP due to its high chemical resistance. Hence, the LCP surface had to be functionalized by using a strong oxidizer (NaKMnO4) before starting conventional chemical etching by a strong base solution. A systematic approach has been developed to etch out the LCP and copper burr formation during the punching process. After examining three different experimental matrices it was found that a sequential treatment by oxidizer (NaKMnO4), etchant (NaOH), and neutralizer (3%H2SO4 + 3%H2O2) gave the best results during the etching process. Considerable improvements were made on LCP and copper burr removal process using the wet chemical treatments including the development of an oxygen plasma treatment to clean the carbonated LCP debris produced during chemical etching. It was found that a subsequent oxygen plasma treatment after the wet chemical processes provided the cleanest through vias for interconnection on LCP substrates.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127943428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490916
T. Braun, K. Becker, L. Böttcher, J. Bauer, T. Thomas, M. Koch, R. Kahle, A. Ostmann, R. Aschenbrenner, H. Reichl, M. Bründel, J. Haag, U. Scholz
The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effective technology for embedding on a medium size scale as known e.g. from MAP (molded array packaging) molding (typically with sizes up to 60 × 60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8” or even up to 12”. Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems (MAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is demonstrated by the fabrication of a Land Grid Array (LGA) type package with two embedded dies. First step is a high precision die placement on an intermediate carrier. For embedding, both compression molding and transfer molding are used and directly compared with regards to material properties, processing, resulting die shift and warpage after molding. Reliability testing including MSL testing, temperature cycling, and humidity storage has been performed with LGA packages manufactured using the different technologies. The reliability potential and failure modes are intensively discussed and backed by destructive and non destructive failure analysis. Finally, an outlook for the integration of through mold vias into RCC redistribution process flow is given showing also the potential for package stacking.
{"title":"Large area embedding for heterogeneous system integration","authors":"T. Braun, K. Becker, L. Böttcher, J. Bauer, T. Thomas, M. Koch, R. Kahle, A. Ostmann, R. Aschenbrenner, H. Reichl, M. Bründel, J. Haag, U. Scholz","doi":"10.1109/ECTC.2010.5490916","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490916","url":null,"abstract":"The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effective technology for embedding on a medium size scale as known e.g. from MAP (molded array packaging) molding (typically with sizes up to 60 × 60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8” or even up to 12”. Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems (MAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is demonstrated by the fabrication of a Land Grid Array (LGA) type package with two embedded dies. First step is a high precision die placement on an intermediate carrier. For embedding, both compression molding and transfer molding are used and directly compared with regards to material properties, processing, resulting die shift and warpage after molding. Reliability testing including MSL testing, temperature cycling, and humidity storage has been performed with LGA packages manufactured using the different technologies. The reliability potential and failure modes are intensively discussed and backed by destructive and non destructive failure analysis. Finally, an outlook for the integration of through mold vias into RCC redistribution process flow is given showing also the potential for package stacking.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"7 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490902
Gyujei Lee, H.-Y Son, J. Hong, Kwang-yoo Byun, D. Kwon
Most TSVs filled with plated copper offer many reliability problems. When subjected to thermal-cycled plating processes, the very large CTE (coefficient of thermal expansion) mismatch between the copper and the silicon/dielectric generates enormous interfacial thermal stress. In addition, the incoherency of differently grown copper grains plated under various processing conditions produces significant residual stress at grain boundaries that can be high enough to cause delamination or interfacial fracture. Many technologies have been developed for measuring residual stress, but they are too bulky to use at TSV microscales or yield averaged results inappropriate for the local assessment of TSV interfaces. Nanoinstrumented indentation testing, on the other hand, has many advantages in the micropartial characterization of residual stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure micropartial residual stress of TSV interfaces through nanoinstrumented indentation testing. To verify our measured outputs, we observed cross-sectional TSV morphologies for metallurgical analysis.
{"title":"Quantification of micropartial residual stress for mechanical characterization of TSV through nanoinstrumented indentation testing","authors":"Gyujei Lee, H.-Y Son, J. Hong, Kwang-yoo Byun, D. Kwon","doi":"10.1109/ECTC.2010.5490902","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490902","url":null,"abstract":"Most TSVs filled with plated copper offer many reliability problems. When subjected to thermal-cycled plating processes, the very large CTE (coefficient of thermal expansion) mismatch between the copper and the silicon/dielectric generates enormous interfacial thermal stress. In addition, the incoherency of differently grown copper grains plated under various processing conditions produces significant residual stress at grain boundaries that can be high enough to cause delamination or interfacial fracture. Many technologies have been developed for measuring residual stress, but they are too bulky to use at TSV microscales or yield averaged results inappropriate for the local assessment of TSV interfaces. Nanoinstrumented indentation testing, on the other hand, has many advantages in the micropartial characterization of residual stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure micropartial residual stress of TSV interfaces through nanoinstrumented indentation testing. To verify our measured outputs, we observed cross-sectional TSV morphologies for metallurgical analysis.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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