Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490709
H. Liu, K. Wang, K. Aasmundtveit, N. Hoivik
A fluxless Cu/Sn SLID bonding process was demonstrated by using intermetallic Cu3Sn layer as the oxidation barrier for Cu interconnects. Oxidation behavior of intermetallic Cu3Sn was confirmed by aging Cu and multilayer Cu/Cu3Sn films at elevated temperatures in ambient air, and measuring the oxidation level by energy dispersive x-ray microscopy (EDX). The strength of bonded interconnects were characterized by shear testing, and found to be comparable to conventionally SLID bonded interconnects. Furthermore, the interdiffusion process of elemental Cu and Sn in the bonding region is discussed.
{"title":"Intermetallic Cu3Sn as oxidation barrier for fluxless Cu-Sn bonding","authors":"H. Liu, K. Wang, K. Aasmundtveit, N. Hoivik","doi":"10.1109/ECTC.2010.5490709","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490709","url":null,"abstract":"A fluxless Cu/Sn SLID bonding process was demonstrated by using intermetallic Cu3Sn layer as the oxidation barrier for Cu interconnects. Oxidation behavior of intermetallic Cu3Sn was confirmed by aging Cu and multilayer Cu/Cu3Sn films at elevated temperatures in ambient air, and measuring the oxidation level by energy dispersive x-ray microscopy (EDX). The strength of bonded interconnects were characterized by shear testing, and found to be comparable to conventionally SLID bonded interconnects. Furthermore, the interdiffusion process of elemental Cu and Sn in the bonding region is discussed.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122069466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490908
L. England
As microelectronic packages migrate to smaller and thinner form factors, WLCSP packaging is becoming more prevalent in the industry. In certain applications, overall WLCSP package heights are restricted to a maximum of 300um. In these situations, electroplated solder mini-bumps can be used to reduce the solder bump height to the sub-100um range. This in turn allows the use of manageable Si wafer thickness for processing. The downside of the electroplated mini-bump structures is the reduced package standoff after surface mounting, which can reduce solder joint reliability. When electroplating Pb-free solder, the composition is typically limited to a binary alloy composition. This reduces the flexibility a vendor has over the control of mechanical properties through solder alloy selection. In addition, the use of these bump structures at high temperatures can be detrimental since any intermetallic compound growth that may occur will represent a much larger volume percentage of the overall solder joint when compared to a larger bump size. This study focuses on the solder joint reliability of WLCSP devices with electroplated Sn-2.5Ag bumps. The bump size is 80um height × 120um diameter on a Cu/Ni UBM stack. Drop testing and thermal cycle testing was performed on 4×4 ball array daisy chain devices following JEDEC testing specifications, and Weibull lifetime estimation plots were created. In addition, Sn-Ni intermetallic compound (IMC) growth was characterized. Board mounted samples were aged at 125°C and 150°C for over 1000hrs. Cross sections were performed in roughly 168hr intervals in order to measure the resulting IMC layer thickness. IMC growth over time was fitted using a power relationship, and the diffusion rate constant and activation energy was calculated. It was found that thermal aging at 125°C resulted in very little IMC growth, while increasing the aging temperature to 150°C resulted in severe IMC growth. The high stress applied to the solder joint from the rapid IMC growth in the small bump area caused cracking of the UBM layer shortly after 500hrs of aging, which resulted in catastrophic failure after roughly 1000hrs. The results show that the Sn-2.5Ag mini-bump structure is quite robust through mechanical stressing of the solder joints. Depending on the final application temperature, they are an adequate interconnect structure to obtain ultra-low package thicknesses.
{"title":"Solder joint reliability performance of electroplated SnAg mini-bumps for WLCSP applications","authors":"L. England","doi":"10.1109/ECTC.2010.5490908","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490908","url":null,"abstract":"As microelectronic packages migrate to smaller and thinner form factors, WLCSP packaging is becoming more prevalent in the industry. In certain applications, overall WLCSP package heights are restricted to a maximum of 300um. In these situations, electroplated solder mini-bumps can be used to reduce the solder bump height to the sub-100um range. This in turn allows the use of manageable Si wafer thickness for processing. The downside of the electroplated mini-bump structures is the reduced package standoff after surface mounting, which can reduce solder joint reliability. When electroplating Pb-free solder, the composition is typically limited to a binary alloy composition. This reduces the flexibility a vendor has over the control of mechanical properties through solder alloy selection. In addition, the use of these bump structures at high temperatures can be detrimental since any intermetallic compound growth that may occur will represent a much larger volume percentage of the overall solder joint when compared to a larger bump size. This study focuses on the solder joint reliability of WLCSP devices with electroplated Sn-2.5Ag bumps. The bump size is 80um height × 120um diameter on a Cu/Ni UBM stack. Drop testing and thermal cycle testing was performed on 4×4 ball array daisy chain devices following JEDEC testing specifications, and Weibull lifetime estimation plots were created. In addition, Sn-Ni intermetallic compound (IMC) growth was characterized. Board mounted samples were aged at 125°C and 150°C for over 1000hrs. Cross sections were performed in roughly 168hr intervals in order to measure the resulting IMC layer thickness. IMC growth over time was fitted using a power relationship, and the diffusion rate constant and activation energy was calculated. It was found that thermal aging at 125°C resulted in very little IMC growth, while increasing the aging temperature to 150°C resulted in severe IMC growth. The high stress applied to the solder joint from the rapid IMC growth in the small bump area caused cracking of the UBM layer shortly after 500hrs of aging, which resulted in catastrophic failure after roughly 1000hrs. The results show that the Sn-2.5Ag mini-bump structure is quite robust through mechanical stressing of the solder joints. Depending on the final application temperature, they are an adequate interconnect structure to obtain ultra-low package thicknesses.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122138935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490836
C. Huyghebaert, J. Van Olmen, O. Chukwudi, J. Coenen, A. Jourdain, M. Van Cauwenberghe, Rahul Agarwahl, A. Phommahaxay, M. Stucchi, P. Soussan
Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200mm wafers [1]. The top tier dies are thinned down to 25μm and bonded to the landing wafer by Cu-Cu thermo-compression [2]. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining.
最近，imec首次展示了通过在200mm晶圆上使用Cu Through Silicon Vias (TSV)进行die-to-die堆叠而获得的3D集成电路。将顶层晶片减薄至25μm，并通过Cu-Cu热压缩[2]与落地晶片粘合。然而，通往大批量生产的道路仍有待确立。在本文中，我们报告了基本的集成问题，并讨论了进一步优化过程的可能解决方案。所提出的解决方案的实施大大提高了Cu-Cu连接的电产率。
{"title":"Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias","authors":"C. Huyghebaert, J. Van Olmen, O. Chukwudi, J. Coenen, A. Jourdain, M. Van Cauwenberghe, Rahul Agarwahl, A. Phommahaxay, M. Stucchi, P. Soussan","doi":"10.1109/ECTC.2010.5490836","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490836","url":null,"abstract":"Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200mm wafers [1]. The top tier dies are thinned down to 25μm and bonded to the landing wafer by Cu-Cu thermo-compression [2]. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128624632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490793
M. Schneider, Christian Herbold, K. Messerschmidt, K. Trampert, J. Brandner
We present a high power density UV-LED module for a wavelength of 395 nm with an optical power density of 13.1 W/cm2. The module consists of 98 densely packed LED chips adhesively bonded to an Al2O3-ceramic board. Thermal simulations and measurements as well as optical measurements were conducted. The module was cooled by a forced air heat sink for the characterization experiments. A surface micro cooler with water as a coolant is proposed to improve thermal performance of the module. To drive the LED module, we developed an efficient current source powered directly from AC mains supply with integrated power factor correction using a single switching component.
{"title":"High power UV-LED-clusters on ceramic substrates","authors":"M. Schneider, Christian Herbold, K. Messerschmidt, K. Trampert, J. Brandner","doi":"10.1109/ECTC.2010.5490793","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490793","url":null,"abstract":"We present a high power density UV-LED module for a wavelength of 395 nm with an optical power density of 13.1 W/cm2. The module consists of 98 densely packed LED chips adhesively bonded to an Al2O3-ceramic board. Thermal simulations and measurements as well as optical measurements were conducted. The module was cooled by a forced air heat sink for the characterization experiments. A surface micro cooler with water as a coolant is proposed to improve thermal performance of the module. To drive the LED module, we developed an efficient current source powered directly from AC mains supply with integrated power factor correction using a single switching component.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128934733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490768
Po-Jen Cheng, C. Chung, T. Pai, D. Y. Chen
In this study, Cu pillar bump is firstly built on FCCSP with 65 nm low k chip. 7 DOE cells are designed to evaluate the effects of Cu pillar height, Cu pillar diameter, PI opening size and PI material on package reliability performance. No obvious failure is found after package assembly and long-term reliability test. The packages are still in good shape even though the reliability test is expanded to 3x test durations With the experiences of Cu pillar bump on 65 nm low k chip, Cu pillar bump is again built on FCBGA package with 45 nm ELK chip. White bump defect is found after chip bond via CSAM inspection, failure analysis shows that the white bump phenomenon is due to crack occurs inside ELK layer. A local heating bond tool (thermal compression bond) is used to improve ELK crack, test results illustrate ELK crack still exists, however the failure rate reduces from original 30%~50% to 5%~20%. Simulation analysis is conducted to study the effect of PI opening size and UBM size on stress concentration at ELK layer. Small PI opening size can reduce stress distribution at ELK layer. On the contrary, relatively large PI opening size and large UBM size also show positive effect on ELK crack. Assembly process and reliability test are conducted again to validate simulation results, experiment data is consistent with simulation result.
{"title":"A challenge of 45 nm extreme low-k chip using Cu pillar bump as 1st interconnection","authors":"Po-Jen Cheng, C. Chung, T. Pai, D. Y. Chen","doi":"10.1109/ECTC.2010.5490768","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490768","url":null,"abstract":"In this study, Cu pillar bump is firstly built on FCCSP with 65 nm low k chip. 7 DOE cells are designed to evaluate the effects of Cu pillar height, Cu pillar diameter, PI opening size and PI material on package reliability performance. No obvious failure is found after package assembly and long-term reliability test. The packages are still in good shape even though the reliability test is expanded to 3x test durations With the experiences of Cu pillar bump on 65 nm low k chip, Cu pillar bump is again built on FCBGA package with 45 nm ELK chip. White bump defect is found after chip bond via CSAM inspection, failure analysis shows that the white bump phenomenon is due to crack occurs inside ELK layer. A local heating bond tool (thermal compression bond) is used to improve ELK crack, test results illustrate ELK crack still exists, however the failure rate reduces from original 30%~50% to 5%~20%. Simulation analysis is conducted to study the effect of PI opening size and UBM size on stress concentration at ELK layer. Small PI opening size can reduce stress distribution at ELK layer. On the contrary, relatively large PI opening size and large UBM size also show positive effect on ELK crack. Assembly process and reliability test are conducted again to validate simulation results, experiment data is consistent with simulation result.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129120915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490697
P. Gueguen, L. Di Cioccio, P. Morfouli, M. Zussy, J. Dechamp, L. Bally, L. Clavelier
3D technology will be the next step for the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Cu/SiO2 patterned surface might be one of the possible techniques to address it. In this work, direct patterned Cu/SiO2 surfaces bonding at room temperature, atmospheric pressure and ambient air is demonstrated. High alignment and bonding quality is achieved for both Wafer to Wafer (WtW) and Die to Wafer (DtW) bonding. Electrical characterizations of Cu/Cu contacts are presented for multiple contact areas and post bonding annealing temperature. The specific contact resistance is lowered down to ρc =47 mΩ.μm2 for 3×3μm2 Cu/Cu contacts on Kelvin structures.
{"title":"Copper direct bonding: An innovative 3D interconnect","authors":"P. Gueguen, L. Di Cioccio, P. Morfouli, M. Zussy, J. Dechamp, L. Bally, L. Clavelier","doi":"10.1109/ECTC.2010.5490697","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490697","url":null,"abstract":"3D technology will be the next step for the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Cu/SiO<sub>2</sub> patterned surface might be one of the possible techniques to address it. In this work, direct patterned Cu/SiO<sub>2</sub> surfaces bonding at room temperature, atmospheric pressure and ambient air is demonstrated. High alignment and bonding quality is achieved for both Wafer to Wafer (WtW) and Die to Wafer (DtW) bonding. Electrical characterizations of Cu/Cu contacts are presented for multiple contact areas and post bonding annealing temperature. The specific contact resistance is lowered down to ρ<sub>c</sub> =47 mΩ.μm<sup>2</sup> for 3×3μm<sup>2</sup> Cu/Cu contacts on Kelvin structures.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490906
Hai Liu, Qirong Chen, Zhenqing Zhao, Qian Wang, Jianfeng Zeng, Jonghyun Chae, Jaisung Lee
Au-Ag alloy wire is a low cost wire bonding solution instead of gold wire for IC packaging. Comparing with copper wire, Au-Ag wire has better productivity because it does not need protective gas and it is softer. The main issue of Au-Ag alloy wire bonding is its reliability in humidity environment. In present study, the bond parameters effect on PCT reliability was investigated. The correlation between the IMC profile and PCT lifetime was established. The IMC characteristic length was defined to express the relationship quantitatively. Meanwhile, The Au-Ag-Al IMC growth equation was obtained through HTS. It is found that the IMC growth rate is slower one order of magnitude than 99.99% gold wire.
{"title":"Reliability of Au-Ag alloy wire bonding","authors":"Hai Liu, Qirong Chen, Zhenqing Zhao, Qian Wang, Jianfeng Zeng, Jonghyun Chae, Jaisung Lee","doi":"10.1109/ECTC.2010.5490906","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490906","url":null,"abstract":"Au-Ag alloy wire is a low cost wire bonding solution instead of gold wire for IC packaging. Comparing with copper wire, Au-Ag wire has better productivity because it does not need protective gas and it is softer. The main issue of Au-Ag alloy wire bonding is its reliability in humidity environment. In present study, the bond parameters effect on PCT reliability was investigated. The correlation between the IMC profile and PCT lifetime was established. The IMC characteristic length was defined to express the relationship quantitatively. Meanwhile, The Au-Ag-Al IMC growth equation was obtained through HTS. It is found that the IMC growth rate is slower one order of magnitude than 99.99% gold wire.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490854
T. Eckert, M. Kruger, W. Müller, N. Nissen, H. Reichl
In this paper, we discuss lifetime prediction for flip chips under temperature and vibration loading in terms of the failure mechanisms related to solder joint fatigue. Our approach does not need additional data from the experiment but can be used in the design stage. For lifetime prediction solder fatigue coefficients from the literature and results from Finite Element Analysis (FEA) are processed by a MATLAB-routine. The predictions are compared to range of in-house experiments on combined loading. In the experimental setup, a statistically relevant number of specimens with single bump in-situ resistance monitoring are used to address the statistical scatter of the lifetime. Therefore, statements on the statistical distribution of solder joint failure in combined loading tests can be formulated. A laser vibrometer is used to determine exact accelerations and deflections of the Printed Circuit Board (PCB). In the failure analysis, ion-etched cross sections of the failed solder bumps are prepared. The features of microstructural transformation and crack-paths are discussed for temperature cycling-only, vibration-only, and combined load experiments. Finally, the model prediction is compared to the experimentally determined solder joint lifetimes and the ranges of good agreement are discussed as well as the range with less agreement.
{"title":"Investigation of the solder joint fatigue life in combined vibration and thermal cycling tests","authors":"T. Eckert, M. Kruger, W. Müller, N. Nissen, H. Reichl","doi":"10.1109/ECTC.2010.5490854","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490854","url":null,"abstract":"In this paper, we discuss lifetime prediction for flip chips under temperature and vibration loading in terms of the failure mechanisms related to solder joint fatigue. Our approach does not need additional data from the experiment but can be used in the design stage. For lifetime prediction solder fatigue coefficients from the literature and results from Finite Element Analysis (FEA) are processed by a MATLAB-routine. The predictions are compared to range of in-house experiments on combined loading. In the experimental setup, a statistically relevant number of specimens with single bump in-situ resistance monitoring are used to address the statistical scatter of the lifetime. Therefore, statements on the statistical distribution of solder joint failure in combined loading tests can be formulated. A laser vibrometer is used to determine exact accelerations and deflections of the Printed Circuit Board (PCB). In the failure analysis, ion-etched cross sections of the failed solder bumps are prepared. The features of microstructural transformation and crack-paths are discussed for temperature cycling-only, vibration-only, and combined load experiments. Finally, the model prediction is compared to the experimentally determined solder joint lifetimes and the ranges of good agreement are discussed as well as the range with less agreement.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121106179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490740
H. Li, E. Liao, X. Pang, H. Yu, X. Yu, J. Y. Sun
One of challenge for the 3D integration by the TSV approach is the electroplating. Electroplating quality and time are important parameters for TSV cost and application. Solid Cu filling TSV (Through Si Via) with via diameter 20 μm and 65μm depth is achieved by the DC (directly current) electroplating within 40 minutes on 8 inch wafer.
采用TSV方法进行三维集成的挑战之一是电镀。电镀质量和电镀时间是影响TSV成本和应用的重要参数。通过在8英寸晶圆上进行直流电镀，在40分钟内实现了直径为20 μm、深度为65μm的固体Cu填充TSV (Through Si Via)。
{"title":"Fast electroplating TSV process development for the via-last approach","authors":"H. Li, E. Liao, X. Pang, H. Yu, X. Yu, J. Y. Sun","doi":"10.1109/ECTC.2010.5490740","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490740","url":null,"abstract":"One of challenge for the 3D integration by the TSV approach is the electroplating. Electroplating quality and time are important parameters for TSV cost and application. Solid Cu filling TSV (Through Si Via) with via diameter 20 μm and 65μm depth is achieved by the DC (directly current) electroplating within 40 minutes on 8 inch wafer.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121272914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/ECTC.2010.5490796
Z. Cai, Yifei Zhang, J. Suhling, P. Lall, R. Johnson, M. Bozack
The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that large degradations occur in the material properties (stiffness and strength) and creep behavior of Sn-Ag-Cu (SAC) lead free solders during aging. These effects are universally detrimental to reliability and are exacerbated as the aging temperature and aging time increases. Conversely, changes due to aging have been shown to be relatively small in conventional Sn-Pb solders. Aging effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. In the current investigation, we have extended our previous studies to include a full test matrix of aging temperatures and SAC lead free solder alloys. In an attempt to reduce the aging induced degradation of the material behavior of SAC solders, we are also exploring various doped SAC-X alloys. These materials are SAC solders that have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn, etc.) has become widespread to enhance shock/drop reliability, wetting, and other properties; and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on solder samples that were aged for various durations (0–6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Four “standard” SAC alloys have been examined in this work including SAC105, SAC205, SAC305, and SAC405. This selection has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). The doped SAC solder materials being considered in our ongoing studies include SAC0307-X, SAC105-X, and SAC305-X. In this work, we will concentrate on presenting the results for SAC0307-X (SAC-X), where X is 0.1%Bi. This alloy has been proposed as a lower cost SAC variation suitable for enhancing drop reliability. For all of the solders, variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. Our findings show that the doped SAC-X alloy illustrates reduced degradations with aging for all of the aging temperatures considered. The stress-strain and creep mechanical properties of SAC-X are better than those of SAC105 after short durations of aging, and approach those of SAC205 with longer aging times. After long
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