2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)最新文献
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463295
S. Vigne, C. Tassetti, T. Alava, R. Mahieu, M. Gely, B. Desloges, C. Moulin, L. Duraffourg, F. Progent
This work shows the optimization, both by simulations and experimentally of the ion source optics of a miniaturized time-of-flight mass spectrometer. The simulations are used to speed up the experiments and make them more efficient in finding optimal working points. The experimental points agree well with simulations. The ion source is used finally as a linear micro time-of-flight mass spectrometer. Simple gas mixtures are identified efficiently using this system.
{"title":"Optimization of the transmission yield of the ion optics on a micro mass spectrometer: Simulations and experimental results","authors":"S. Vigne, C. Tassetti, T. Alava, R. Mahieu, M. Gely, B. Desloges, C. Moulin, L. Duraffourg, F. Progent","doi":"10.1109/EUROSIME.2016.7463295","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463295","url":null,"abstract":"This work shows the optimization, both by simulations and experimentally of the ion source optics of a miniaturized time-of-flight mass spectrometer. The simulations are used to speed up the experiments and make them more efficient in finding optimal working points. The experimental points agree well with simulations. The ion source is used finally as a linear micro time-of-flight mass spectrometer. Simple gas mixtures are identified efficiently using this system.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121989968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463314
Paula López, A. J. G. Loureiro, E. Ferro, V. Brea, B. Rivas‐Murias
Computer-aided design (CAD) simulation tools offer the advantage of integrating both thermal and electrical simulations facilitating the study of new materials and structures. In this work, we demonstrate the possibility of using conventional electron devices simulation tools to study the thermoelectrical properties of non-typical semiconductor materials, which allows to do predictive parametric analysis of novel device structures without costly experiments. This is illustrated without loss of generality for scandium nitride and strontium titanate. The simulated results are in good agreement with those reported in the literature.
{"title":"Study of the thermoelectric properties of non-typical semiconductor materials with conventional CAD tools","authors":"Paula López, A. J. G. Loureiro, E. Ferro, V. Brea, B. Rivas‐Murias","doi":"10.1109/EUROSIME.2016.7463314","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463314","url":null,"abstract":"Computer-aided design (CAD) simulation tools offer the advantage of integrating both thermal and electrical simulations facilitating the study of new materials and structures. In this work, we demonstrate the possibility of using conventional electron devices simulation tools to study the thermoelectrical properties of non-typical semiconductor materials, which allows to do predictive parametric analysis of novel device structures without costly experiments. This is illustrated without loss of generality for scandium nitride and strontium titanate. The simulated results are in good agreement with those reported in the literature.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463323
S. Stoyanov, G. Tourloukis, T. Tilford, C. Bailey
3D printing technologies provide one of the most efficient methods for product design, prototyping and manufacture in a cost-effective, high-throughput, mass-customisation and energy efficient manner. One growing application of 3D printing includes the fabrication, packaging and integration of electronic structures and components. This paper presents modelling methodologies and toolsets that can be used to address some of the present design-for-reliability challenges related to 3D inkjet-printed electronics. The use of advanced capabilities in finite element modelling is proposed and employed in order to predict the mechanical behaviour of cured ink-based materials when deposited sequentially layer-by-layer. Such build-up approach can lead to structural weakness and dimensional inaccuracy in the third dimension due to cure shrinkage. In addition, effects of different process and material parameters on the stress induced in silver ink printed conductive lines under thermal load are analysed. This analysis uses integrated finite element based design-of-simulations approach and response surface modelling. The geometric design of the investigated printed structure are found to be less influential compared with the mechanical properties of the cured insulating material and the magnitude of the temperature load to which the structure is exposed.
{"title":"Modelling methodologies for assessment of 3D inkjet-printed electronics","authors":"S. Stoyanov, G. Tourloukis, T. Tilford, C. Bailey","doi":"10.1109/EUROSIME.2016.7463323","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463323","url":null,"abstract":"3D printing technologies provide one of the most efficient methods for product design, prototyping and manufacture in a cost-effective, high-throughput, mass-customisation and energy efficient manner. One growing application of 3D printing includes the fabrication, packaging and integration of electronic structures and components. This paper presents modelling methodologies and toolsets that can be used to address some of the present design-for-reliability challenges related to 3D inkjet-printed electronics. The use of advanced capabilities in finite element modelling is proposed and employed in order to predict the mechanical behaviour of cured ink-based materials when deposited sequentially layer-by-layer. Such build-up approach can lead to structural weakness and dimensional inaccuracy in the third dimension due to cure shrinkage. In addition, effects of different process and material parameters on the stress induced in silver ink printed conductive lines under thermal load are analysed. This analysis uses integrated finite element based design-of-simulations approach and response surface modelling. The geometric design of the investigated printed structure are found to be less influential compared with the mechanical properties of the cured insulating material and the magnitude of the temperature load to which the structure is exposed.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463357
V. Rochus, R. Jansen, J. Goyvaerts, G. Vandenboch, B. van de Voort, P. Neutens, J. Callaghan, H. Tilmans, X. Rottenberg
This paper presents the design of Micro-Opto-Mechanical Pressure Sensors (MOMPS), which can exhibit much improved sensitivity and noise performance compared to their piezoelectric and capacitive counterparts. As the output intensity variation depends on multiple design parameters, such as the radius of the membrane, the position of the waveguide, the wavelength and the phase variation due to the opto-mechanical coupling, we first derive an analytical model which allows to predict the response of the total system. We then use a Finite Element opto-mechanical model to evaluate the variation of the effective refractive index due to the modification of the optical material properties created by mechanical stress as well as to the waveguide shape deformation. Finally, the sensitivity of the device for a single loop MOMPS and for spiral loops configuration is analyzed.
{"title":"Design of a MZI Micro-Opto-Mechanical Pressure Sensor for a SiN photonics platform","authors":"V. Rochus, R. Jansen, J. Goyvaerts, G. Vandenboch, B. van de Voort, P. Neutens, J. Callaghan, H. Tilmans, X. Rottenberg","doi":"10.1109/EUROSIME.2016.7463357","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463357","url":null,"abstract":"This paper presents the design of Micro-Opto-Mechanical Pressure Sensors (MOMPS), which can exhibit much improved sensitivity and noise performance compared to their piezoelectric and capacitive counterparts. As the output intensity variation depends on multiple design parameters, such as the radius of the membrane, the position of the waveguide, the wavelength and the phase variation due to the opto-mechanical coupling, we first derive an analytical model which allows to predict the response of the total system. We then use a Finite Element opto-mechanical model to evaluate the variation of the effective refractive index due to the modification of the optical material properties created by mechanical stress as well as to the waveguide shape deformation. Finally, the sensitivity of the device for a single loop MOMPS and for spiral loops configuration is analyzed.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126602028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463298
P. Gardes, F. Roqueta, M. Diatta, P. Martinez, F. Lauron, E. Bouyssou, P. Poveda
For the last decade, paraelectric BaxSr1-xTiO3 (BST) thin films have been especially studied to fabricate MIM capacitor for capacitance tuning applications. This paper describes the mechanisms of cracks apparition under BST stacked MIMIM capacitors (Metal Insulator Metal Insulator Metal) built on silicon substrate. The methodology used in this study to have a further understanding of this phenomenon is to investigate 2D process simulations, based on an elastic model. Hence, it could be evidenced that the gap between the extreme stress levels induced by an annealing performed at the end of the capacitor manufacturing is the main contributor in the crack formation. Then, the change from silicon to a sapphire substrate was implemented to avoid cracks in the real process integration. Finally, the capacitor devices could be tested and were demonstrated to exhibit better electrical specifications.
在过去的十年中，对准电BaxSr1-xTiO3 (BST)薄膜进行了专门的研究，以制造用于电容调谐应用的MIM电容器。本文研究了基于硅衬底的BST叠置电容(Metal Insulator Metal Insulator Metal)产生裂纹的机理。为了进一步理解这一现象，本研究采用了基于弹性模型的二维过程模拟方法。因此，可以证明，在电容器制造结束时进行的退火引起的极端应力水平之间的差距是裂纹形成的主要原因。然后，实现了从硅衬底到蓝宝石衬底的变化，以避免在实际的工艺集成中出现裂缝。最后，电容器器件可以进行测试，并被证明具有更好的电气规格。
{"title":"Thermo-mechanical simulation to optimize the integration of a BST stacked MIMIM capacitor","authors":"P. Gardes, F. Roqueta, M. Diatta, P. Martinez, F. Lauron, E. Bouyssou, P. Poveda","doi":"10.1109/EUROSIME.2016.7463298","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463298","url":null,"abstract":"For the last decade, paraelectric BaxSr1-xTiO3 (BST) thin films have been especially studied to fabricate MIM capacitor for capacitance tuning applications. This paper describes the mechanisms of cracks apparition under BST stacked MIMIM capacitors (Metal Insulator Metal Insulator Metal) built on silicon substrate. The methodology used in this study to have a further understanding of this phenomenon is to investigate 2D process simulations, based on an elastic model. Hence, it could be evidenced that the gap between the extreme stress levels induced by an annealing performed at the end of the capacitor manufacturing is the main contributor in the crack formation. Then, the change from silicon to a sapphire substrate was implemented to avoid cracks in the real process integration. Finally, the capacitor devices could be tested and were demonstrated to exhibit better electrical specifications.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463404
J. Albrecht, G. M. Reuther, J. Brueckner, J. Auersperg, S. Rzepka, R. Pufall
Wire bonding as well as wafer probing can lead to oxide layer cracking. In combination with metal migration electrical failures may occur. Loading conditions comparable to the wire bonding process can be achieved using a nanoindenter. In this work a spherical tip has been used at first to determine material properties of the silicon nitride film and also to attain cracking of the film material. Based on the experimental results a finite element model using ABAQUS standardTM was established representing the experimentally observed load-displacement behavior. The introduction of the extended finite element method as well as the cohesive surface approach allow to describe different failure modes. The results of these investigations can be used to avoid failures like oxide layer cracking during wire bonding or during the wafer testing process.
{"title":"Risk assessment of bond pad stacks: Combined utilization of nanoindentation and FE-modeling","authors":"J. Albrecht, G. M. Reuther, J. Brueckner, J. Auersperg, S. Rzepka, R. Pufall","doi":"10.1109/EUROSIME.2016.7463404","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463404","url":null,"abstract":"Wire bonding as well as wafer probing can lead to oxide layer cracking. In combination with metal migration electrical failures may occur. Loading conditions comparable to the wire bonding process can be achieved using a nanoindenter. In this work a spherical tip has been used at first to determine material properties of the silicon nitride film and also to attain cracking of the film material. Based on the experimental results a finite element model using ABAQUS standardTM was established representing the experimentally observed load-displacement behavior. The introduction of the extended finite element method as well as the cohesive surface approach allow to describe different failure modes. The results of these investigations can be used to avoid failures like oxide layer cracking during wire bonding or during the wafer testing process.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123771845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463297
Hong-liang Ke, Qiang Sun, Jian Zhao, Hongxin Zhang, L. Jing, Yao Wang, Jian-cheng Hao
For estimating the junction temperature (Tj) of LED lamp, the Tj of LED module powering by rated current (135mA DC) and working in the thermal environment of LED lamp is measured with traditional forward voltage method in experiment 1. To calculate the Tj of LED lamp in actual working conditions (220V AC), a correction factor is introduced into the original model to process the deviation of output currents of LED driver electronics, as demonstrated in experiment 2. Compared with the surface temperature of LED obtained by infrared imaging method, the result in experiment 2 can effectively reflect the change in Tj of LED lamp under different ambient temperatures, which differs the surface temperature by 3~4°C. While due to a significant effect on the thermal environment of LED lamp introduced by LED driver electronics, the result in experiment 1 is approximately 9~10°C lower than that in experiment 2.
{"title":"Junction temperature estimation for LED lamp with forward voltage method","authors":"Hong-liang Ke, Qiang Sun, Jian Zhao, Hongxin Zhang, L. Jing, Yao Wang, Jian-cheng Hao","doi":"10.1109/EUROSIME.2016.7463297","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463297","url":null,"abstract":"For estimating the junction temperature (Tj) of LED lamp, the Tj of LED module powering by rated current (135mA DC) and working in the thermal environment of LED lamp is measured with traditional forward voltage method in experiment 1. To calculate the Tj of LED lamp in actual working conditions (220V AC), a correction factor is introduced into the original model to process the deviation of output currents of LED driver electronics, as demonstrated in experiment 2. Compared with the surface temperature of LED obtained by infrared imaging method, the result in experiment 2 can effectively reflect the change in Tj of LED lamp under different ambient temperatures, which differs the surface temperature by 3~4°C. While due to a significant effect on the thermal environment of LED lamp introduced by LED driver electronics, the result in experiment 1 is approximately 9~10°C lower than that in experiment 2.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125097950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463368
M. Stiebing, E. Lortscher, W. Steller, D. Vogel, M. Wolf, T. Brunschwiler, B. Wunderle
With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a pathway to provide electrical connections for signaling and power-delivery through 3D-stacked silicon (Si) microstructures. TSVs and related structures such as, e.g., interconnects and redistribution lines, however, induce stress in their proximity, namely upon electrochemical deposition and subsequent annealing, the latter due to the large mismatch in the coefficient of thermal expansion between Si and the TSV-filling materials used. Stress-induced crowding and relaxation of the Si lattice can cause a variety of issues ranging from active-device performance degradation, interfacial delamination or interconnect failures to cracking of the entire Si microstructures at stress hotspots upon assembly or operation. Employing a novel dual-shell Si interposer concept with both power delivery and signaling through TSVs, we aim at removing the heat dissipated from the active components sitting on top of one interposer shell through embedded liquid-cooling cavities, a strategy that generically enables true 3D stacking but may also induce additional stress. In the current paper, we reduce system complexity and first investigate, both experimentally and theoretically the TSV-induced stress profiles in one Si interposer half before introducing cooling cavities and sealing structures. After each processing step, the residual and non-thermal stress profile around the TSV is determined using a confocal Raman microscope with sub-micrometer spot-size acting as a local strain gauge. These measurements are conducted under ultra-silent conditions, revealing an unprecedented resolution of 0.01 cm-1, corresponding to approx. 4.3 MPa of stress in crystalline Si. A detailed comparison of measurements and finite element analysis (with the later taking into account geometry and material properties) is provided, revealing both a good qualitative and quantitative correlation between theory and experiment. We also show that athermal stress after copper deposition can be minimized during an annealing step.
{"title":"Stress investigations in 3D-integrated silicon microstructures","authors":"M. Stiebing, E. Lortscher, W. Steller, D. Vogel, M. Wolf, T. Brunschwiler, B. Wunderle","doi":"10.1109/EUROSIME.2016.7463368","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463368","url":null,"abstract":"With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a pathway to provide electrical connections for signaling and power-delivery through 3D-stacked silicon (Si) microstructures. TSVs and related structures such as, e.g., interconnects and redistribution lines, however, induce stress in their proximity, namely upon electrochemical deposition and subsequent annealing, the latter due to the large mismatch in the coefficient of thermal expansion between Si and the TSV-filling materials used. Stress-induced crowding and relaxation of the Si lattice can cause a variety of issues ranging from active-device performance degradation, interfacial delamination or interconnect failures to cracking of the entire Si microstructures at stress hotspots upon assembly or operation. Employing a novel dual-shell Si interposer concept with both power delivery and signaling through TSVs, we aim at removing the heat dissipated from the active components sitting on top of one interposer shell through embedded liquid-cooling cavities, a strategy that generically enables true 3D stacking but may also induce additional stress. In the current paper, we reduce system complexity and first investigate, both experimentally and theoretically the TSV-induced stress profiles in one Si interposer half before introducing cooling cavities and sealing structures. After each processing step, the residual and non-thermal stress profile around the TSV is determined using a confocal Raman microscope with sub-micrometer spot-size acting as a local strain gauge. These measurements are conducted under ultra-silent conditions, revealing an unprecedented resolution of 0.01 cm-1, corresponding to approx. 4.3 MPa of stress in crystalline Si. A detailed comparison of measurements and finite element analysis (with the later taking into account geometry and material properties) is provided, revealing both a good qualitative and quantitative correlation between theory and experiment. We also show that athermal stress after copper deposition can be minimized during an annealing step.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128134809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463317
C. Qian, Y. Li, Jiajie Fan, Xuejun Fan, Jiajia Fu, Lixia Zhao, Guoqi Zhang
In this study, an electro-optical simulation method is developed to simulate the light intensity distribution of a conventional GaN based blue LED chip. The entire modeling process consists of electrical simulation with ANSYS and optical simulation with LightTools, which are based on an assumption of proportional relation between the distributed current density and light emission energy on multiple quantum well layer. Experimental results show that the proposed simulation method can give a good prediction on the light intensity distribution of a packaged GaN based blue LED chip.
{"title":"Electro-optical simulation of a GaN based blue LED chip","authors":"C. Qian, Y. Li, Jiajie Fan, Xuejun Fan, Jiajia Fu, Lixia Zhao, Guoqi Zhang","doi":"10.1109/EUROSIME.2016.7463317","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463317","url":null,"abstract":"In this study, an electro-optical simulation method is developed to simulate the light intensity distribution of a conventional GaN based blue LED chip. The entire modeling process consists of electrical simulation with ANSYS and optical simulation with LightTools, which are based on an assumption of proportional relation between the distributed current density and light emission energy on multiple quantum well layer. Experimental results show that the proposed simulation method can give a good prediction on the light intensity distribution of a packaged GaN based blue LED chip.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128523320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-18DOI: 10.1109/EUROSIME.2016.7463401
B. Vandevelde, F. Vanhee, D. Pissoort, L. Degrendele, J. De Baets, B. Allaert, R. Lauwaert, R. Labie, G. Willems
This paper deals with an alternative testing approach for quantifying the life time of board level solder joint reliability of components. This approach consists of applying a relative shear displacement between component and Printed Circuit Board (PCB) through cyclic board bending. During the cycling, the temperature is kept constant, preferably at elevated temperature in order to fasten the creep deformation of the solder joint. This is done in a four-point bending setup which allows to apply an equal loading on all components lying between the inner bars. The scope of the paper is, firstly, to evaluate if the four point bending testing generates the same fatigue fracture as in thermal cycling; secondly, that the measured life times can be also predicted through finite element simulations; and thirdly if the technique can finally fasten the cycling frequency to gain testing time.
{"title":"Four-point bending cycling as alternative for thermal cycling solder fatigue testing","authors":"B. Vandevelde, F. Vanhee, D. Pissoort, L. Degrendele, J. De Baets, B. Allaert, R. Lauwaert, R. Labie, G. Willems","doi":"10.1109/EUROSIME.2016.7463401","DOIUrl":"https://doi.org/10.1109/EUROSIME.2016.7463401","url":null,"abstract":"This paper deals with an alternative testing approach for quantifying the life time of board level solder joint reliability of components. This approach consists of applying a relative shear displacement between component and Printed Circuit Board (PCB) through cyclic board bending. During the cycling, the temperature is kept constant, preferably at elevated temperature in order to fasten the creep deformation of the solder joint. This is done in a four-point bending setup which allows to apply an equal loading on all components lying between the inner bars. The scope of the paper is, firstly, to evaluate if the four point bending testing generates the same fatigue fracture as in thermal cycling; secondly, that the measured life times can be also predicted through finite element simulations; and thirdly if the technique can finally fasten the cycling frequency to gain testing time.","PeriodicalId":438097,"journal":{"name":"2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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