We report optimization of the steering efficiency of the 1-D opto-VLSI processor using direct power measurement method for wavelengths in the near-IR and 632 nm. Highest improvement observed for the signal and interport isolation is 8 dB and 12 dB respectively. This improved performance of the processor is crucial to the realization of low crosstalk reconfigurable optical add/drop multiplexers (ROADM) using opto-VLSI processors.
{"title":"Improving the steering efficiency of 1/spl times/4096 opto-VLSI processor using direct power measurement method","authors":"C. Poh, K. Alameh","doi":"10.1109/DELTA.2006.57","DOIUrl":"https://doi.org/10.1109/DELTA.2006.57","url":null,"abstract":"We report optimization of the steering efficiency of the 1-D opto-VLSI processor using direct power measurement method for wavelengths in the near-IR and 632 nm. Highest improvement observed for the signal and interport isolation is 8 dB and 12 dB respectively. This improved performance of the processor is crucial to the realization of low crosstalk reconfigurable optical add/drop multiplexers (ROADM) using opto-VLSI processors.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122574365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital bandpass filters are widely used in the field of signal processing. A lot of implementations can be found in the literature, either by software or hardware solutions. The proposed design will use many IIR-biquads in serial and parallel form to construct a multichannel bandpass filter; each biquad contains a very small processor inside. The advantages of this modulized arrangement are simple but flexible, expandable and cost-effective. In the VLSI implementation, the hardware complexity of the filter is directly proportional to the number of orders and the bit-width of input signal and the coefficients. To reduce the hardware cost, this can be solved with iteration calculations by software; therefore, a co-design of hardware and software may produce cost-efficient IIR filters. The key design concept is to build a processor for software processing with minimum hardware resources, without sacrificing the performance of the original IIR filter. The proposed design architecture can be used for embedded systems in system-on-chip (SOC) environments easily.
{"title":"Design and implementation of multichannel bandpass filter for embedded system","authors":"Chao-Huang Wei, H. Hsiao, S. Tsai","doi":"10.1109/DELTA.2006.32","DOIUrl":"https://doi.org/10.1109/DELTA.2006.32","url":null,"abstract":"Digital bandpass filters are widely used in the field of signal processing. A lot of implementations can be found in the literature, either by software or hardware solutions. The proposed design will use many IIR-biquads in serial and parallel form to construct a multichannel bandpass filter; each biquad contains a very small processor inside. The advantages of this modulized arrangement are simple but flexible, expandable and cost-effective. In the VLSI implementation, the hardware complexity of the filter is directly proportional to the number of orders and the bit-width of input signal and the coefficients. To reduce the hardware cost, this can be solved with iteration calculations by software; therefore, a co-design of hardware and software may produce cost-efficient IIR filters. The key design concept is to build a processor for software processing with minimum hardware resources, without sacrificing the performance of the original IIR filter. The proposed design architecture can be used for embedded systems in system-on-chip (SOC) environments easily.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"163 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed.
{"title":"Energy efficient cache timing with performance bound","authors":"Leipo Yan, S. Lam, T. Srikanthan, W. Jigang","doi":"10.1109/DELTA.2006.45","DOIUrl":"https://doi.org/10.1109/DELTA.2006.45","url":null,"abstract":"Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115441868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new active circuit for realizing lossless floating inductor using current controlled conveyors (CCCIIs) and single capacitor is presented. The proposed inductance simulator can be tuned electronically by changing the biasing currents of the CCCIIs. As an application, the proposed floating inductance simulator is used to construct a fifth-order low-pass filter. The theoretical analysis is verified by SPICE simulation results
{"title":"Lossless active floating inductance simulator","authors":"S. Minaei, E. Yüce, O. Cicekoglu","doi":"10.1109/DELTA.2006.61","DOIUrl":"https://doi.org/10.1109/DELTA.2006.61","url":null,"abstract":"In this paper, a new active circuit for realizing lossless floating inductor using current controlled conveyors (CCCIIs) and single capacitor is presented. The proposed inductance simulator can be tuned electronically by changing the biasing currents of the CCCIIs. As an application, the proposed floating inductance simulator is used to construct a fifth-order low-pass filter. The theoretical analysis is verified by SPICE simulation results","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125913604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design parameters of a supervisory (SV) system intended for a distributed Raman amplifier (DBA) is investigated theoretically. The pump is low frequency modulated to transmit supervisory information which forms part of the fault management system in a Raman amplified fiber optic network. Issues regarding modulation frequency of the SV signal and its effect on the integrity of the signal are studied. Power penalty issues due to introduction of the SV signal in the optical network are also studied. These theoretical studies are based on numerical solution of coupled propagation equations for counter-pumped DRA.
{"title":"Supervisory signal transmission in distributed Raman amplifiers","authors":"Lau Bei Yer, V. Kalavally, T. Win, M. Premaratne","doi":"10.1109/DELTA.2006.82","DOIUrl":"https://doi.org/10.1109/DELTA.2006.82","url":null,"abstract":"Design parameters of a supervisory (SV) system intended for a distributed Raman amplifier (DBA) is investigated theoretically. The pump is low frequency modulated to transmit supervisory information which forms part of the fault management system in a Raman amplified fiber optic network. Issues regarding modulation frequency of the SV signal and its effect on the integrity of the signal are studied. Power penalty issues due to introduction of the SV signal in the optical network are also studied. These theoretical studies are based on numerical solution of coupled propagation equations for counter-pumped DRA.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A project based approach has been adopted to teach matlab/simulink based controller design, mixed signal embedded microcontroller (SiLab C8051F020) based implementation of the controller for DC motor speed control project, the laboratory part of the subject 143.335 Instrumentation, Electronics and Control Engineering at Massey University, New Zealand. The students developed a Matlab/Simulink based model to study the theoretical part of the controller design. The microcontroller based PID controller implementation was divided into five activities and each activity was assessed at regular intervals. The student feedback has been collected, the survey of which shows that the objectives were successfully met.
{"title":"A project based approach to teach mixed-signal embedded microcontroller for DC motor control","authors":"G. S. Gupta, S. Mukhopadhyay, M. Chew","doi":"10.1109/DELTA.2006.9","DOIUrl":"https://doi.org/10.1109/DELTA.2006.9","url":null,"abstract":"A project based approach has been adopted to teach matlab/simulink based controller design, mixed signal embedded microcontroller (SiLab C8051F020) based implementation of the controller for DC motor speed control project, the laboratory part of the subject 143.335 Instrumentation, Electronics and Control Engineering at Massey University, New Zealand. The students developed a Matlab/Simulink based model to study the theoretical part of the controller design. The microcontroller based PID controller implementation was divided into five activities and each activity was assessed at regular intervals. The student feedback has been collected, the survey of which shows that the objectives were successfully met.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose an optical wireless communication network architecture employing an all-optical central communication unit and optical transceiver units. The network can easily be installed when communication network facilities are partially damaged by a disaster. The network performance is simulated at 1Gbit/s, over 1km under different weather conditions.
{"title":"Distributed wireless optical communications for humanitarian assistance in disasters","authors":"M. Aljada, K. Alameh, K. Al-Begain","doi":"10.1109/DELTA.2006.37","DOIUrl":"https://doi.org/10.1109/DELTA.2006.37","url":null,"abstract":"We propose an optical wireless communication network architecture employing an all-optical central communication unit and optical transceiver units. The network can easily be installed when communication network facilities are partially damaged by a disaster. The network performance is simulated at 1Gbit/s, over 1km under different weather conditions.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132239882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of power. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the high-level synthesis by defining partitions. Starting from a controlled-data-flow-graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That mean, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used.
{"title":"A new design partitioning approach for low power high-level synthesis","authors":"A. Rettberg, F. Rammig","doi":"10.1109/DELTA.2006.8","DOIUrl":"https://doi.org/10.1109/DELTA.2006.8","url":null,"abstract":"The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of power. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the high-level synthesis by defining partitions. Starting from a controlled-data-flow-graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That mean, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130107409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, intra-chip design has long been the main research area for the past years, resulting in several folds of computing power increase per year. In contrast, the speed of cross-chip connection, or even cross-system connection, has not been enhanced at the same rate, and gradually became the bottleneck of current computing systems. PCI, PCI-X, and PCI-Express epitomize the evolvement of our peripheral connecting strategy. By radical change in architecture, we successfully increase throughput of connection facilities in one autonomous system. We propose a architecture for verifying advanced switch hardware. Also successfully verify the compliance of the design under test's features to the given protocol.
{"title":"A functional verification environment for advanced switching architecture","authors":"Min-An Song, Ting-Chun Huang, S. Kuo","doi":"10.1109/DELTA.2006.2","DOIUrl":"https://doi.org/10.1109/DELTA.2006.2","url":null,"abstract":"In this paper, intra-chip design has long been the main research area for the past years, resulting in several folds of computing power increase per year. In contrast, the speed of cross-chip connection, or even cross-system connection, has not been enhanced at the same rate, and gradually became the bottleneck of current computing systems. PCI, PCI-X, and PCI-Express epitomize the evolvement of our peripheral connecting strategy. By radical change in architecture, we successfully increase throughput of connection facilities in one autonomous system. We propose a architecture for verifying advanced switch hardware. Also successfully verify the compliance of the design under test's features to the given protocol.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131910402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parasitic on-chip inductance is a major concern for functionality and performance. It affects global signal busses comprised of a large number of nets and traversing long distances most prominently. Due to the difference in separation distance, an attacker affects different signals within a wide bus in varying degrees. This variance in the coupling strength gives rise to an arrival time skew within the victim bus. This paper discusses the use of swizzling to average out the inductive coupling of the attacker over its victims. The paper presents results to show that swizzling significantly reduces inductive coupling skew within a wide global signal bus with zero area and routing resource penalty.
{"title":"Reducing inductive coupling skew in wide global signal busses","authors":"B. Soudan","doi":"10.1109/DELTA.2006.74","DOIUrl":"https://doi.org/10.1109/DELTA.2006.74","url":null,"abstract":"Parasitic on-chip inductance is a major concern for functionality and performance. It affects global signal busses comprised of a large number of nets and traversing long distances most prominently. Due to the difference in separation distance, an attacker affects different signals within a wide bus in varying degrees. This variance in the coupling strength gives rise to an arrival time skew within the victim bus. This paper discusses the use of swizzling to average out the inductive coupling of the attacker over its victims. The paper presents results to show that swizzling significantly reduces inductive coupling skew within a wide global signal bus with zero area and routing resource penalty.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131401020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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