Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745196
B. Basaran, K. Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, S. Rangarajan, Naresh Sehgal
We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells.
{"title":"GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs","authors":"B. Basaran, K. Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, S. Rangarajan, Naresh Sehgal","doi":"10.1109/ICVD.1999.745196","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745196","url":null,"abstract":"We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127683052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745170
I. Sander, A. Jantsch
Formal approaches to HW and system design have not been generally adopted because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover they are frequently on a too high abstraction level to allow for efficient synthesis with today's techniques. We address this problem with a modelling method, which is strictly formal and based on formal semantics, a pure functional language, and the synchrony hypothesis. But the use of skeletons in conjunction with a proper computational model allows to associate a direct hardware interpretation. In particular we use the synchrony hypothesis and a timed signal model to provide a high abstraction for communication at the system level. This facilitates efficient modelling and design space exploration at the functional level, because the designer is not concerned with complex communication mechanisms, and functionality can easily be moved from one block to another. To bridge the gap between an elegant and abstract functional model and the details of an implementation we use skeletons to encapsulate primitive structures, such as FSMs, buffers, computation units, etc. in a purely functional way.
{"title":"Formal system design based on the synchrony hypothesis, functional models, and skeletons","authors":"I. Sander, A. Jantsch","doi":"10.1109/ICVD.1999.745170","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745170","url":null,"abstract":"Formal approaches to HW and system design have not been generally adopted because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover they are frequently on a too high abstraction level to allow for efficient synthesis with today's techniques. We address this problem with a modelling method, which is strictly formal and based on formal semantics, a pure functional language, and the synchrony hypothesis. But the use of skeletons in conjunction with a proper computational model allows to associate a direct hardware interpretation. In particular we use the synchrony hypothesis and a timed signal model to provide a high abstraction for communication at the system level. This facilitates efficient modelling and design space exploration at the functional level, because the designer is not concerned with complex communication mechanisms, and functionality can easily be moved from one block to another. To bridge the gap between an elegant and abstract functional model and the details of an implementation we use skeletons to encapsulate primitive structures, such as FSMs, buffers, computation units, etc. in a purely functional way.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"435 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745147
P. Mandal, V. Visvanathan
A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the first order behavior of an MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as convex functions. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converges to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Performance of the synthesized op-amps has been verified against detailed SPICE simulation for a 1.6 /spl mu/ CMOS process.
{"title":"A new approach for CMOS op-amp synthesis","authors":"P. Mandal, V. Visvanathan","doi":"10.1109/ICVD.1999.745147","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745147","url":null,"abstract":"A new approach for CMOS op-amp circuit synthesis has proposed here. The approach is based on the observation that the first order behavior of an MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as convex functions. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converges to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Performance of the synthesized op-amps has been verified against detailed SPICE simulation for a 1.6 /spl mu/ CMOS process.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133045898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745199
A. Kahng, S. Muddu, E. Sarto
Interconnect tuning and repeater insertion are necessary to optimize interconnect delay, signal performance and integrity, and interconnect manufacturability and reliability. Repeater insertion in interconnects is an increasingly important element in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.
{"title":"Interconnect optimization strategies for high-performance VLSI designs","authors":"A. Kahng, S. Muddu, E. Sarto","doi":"10.1109/ICVD.1999.745199","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745199","url":null,"abstract":"Interconnect tuning and repeater insertion are necessary to optimize interconnect delay, signal performance and integrity, and interconnect manufacturability and reliability. Repeater insertion in interconnects is an increasingly important element in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133843099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745135
A. Doganis, James C. Chen
In this work, we will describe and analyze simple, accurate and compact models for interconnect structures. These parameterized models are optimized for the particular fabrication process via field solver simulations and on wafer test structure measurements. Additionally, process variations will be incorporated in the compact models using the principal component analysis (PCA) and performance response surface models (RSM) to derive statistical interconnect models. A new test structure, along with the measurement scheme and the associated extraction methods are introduced here to facilitate the calibration of the interconnect models. Additionally, further tuning of those models with respect to measurements of complex on-chip test structures, such as clock nets, assures model accuracy and circuit performance predictability.
{"title":"Interconnect simple, accurate and statistical models using on-chip measurements for calibration","authors":"A. Doganis, James C. Chen","doi":"10.1109/ICVD.1999.745135","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745135","url":null,"abstract":"In this work, we will describe and analyze simple, accurate and compact models for interconnect structures. These parameterized models are optimized for the particular fabrication process via field solver simulations and on wafer test structure measurements. Additionally, process variations will be incorporated in the compact models using the principal component analysis (PCA) and performance response surface models (RSM) to derive statistical interconnect models. A new test structure, along with the measurement scheme and the associated extraction methods are introduced here to facilitate the calibration of the interconnect models. Additionally, further tuning of those models with respect to measurements of complex on-chip test structures, such as clock nets, assures model accuracy and circuit performance predictability.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132314444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745124
Kavita Nair, R. Harjani
This paper describes the design of a compact, ultra low power continuous time programmable filter. Compact programmable filters are required for a number of applications. A particular application is in feedback cancellation filters in hearing aids. Here, a feedback cancellation filter that matches the open loop transfer function is used to suppress acoustic oscillations. Because of the complexity of the transfer function the number of poles in the cancellation filter is fairly large. To realize an integrated cancellation filter an ultra-low power transconductance cell with large linear range has been designed. Both measurement and simulation results are presented to confirm our design. The power consumption for a transconductance cell is comparable to the theoretical minimum bound and is measured to be 0.8 /spl mu/W at a 3 V supply. The linear input range for this cell is 2 V/sub p-p/. In this paper we also compare our design with a programmable switched capacitor implementation and show that there is a significant savings in area as well. The complete filter has been designed, implemented and fabricated in an 2 /spl mu/ CMOS technology.
本文介绍了一种结构紧凑、超低功耗连续时间可编程滤波器的设计。紧凑的可编程滤波器是许多应用所必需的。一个特殊的应用是在助听器的反馈抵消滤波器。在这里，一个与开环传递函数相匹配的反馈抵消滤波器被用来抑制声学振荡。由于传递函数的复杂性，抵消滤波器中的极点数相当大。为了实现集成对消滤波器，设计了一种具有大线性范围的超低功耗跨导电池。测试和仿真结果验证了我们的设计。跨导电池的功耗与理论最小边界相当，在3v电源下测量为0.8 /spl mu/W。该电池的线性输入范围为2v /sub p-p/。在本文中，我们还将我们的设计与可编程开关电容器的实现进行了比较，并表明在面积上也有显着的节省。完整的滤波器以2 /spl μ m / CMOS工艺设计、实现和制造。
{"title":"Compact, ultra low power, programmable continuous-time filter banks for feedback cancellation in hearing aid","authors":"Kavita Nair, R. Harjani","doi":"10.1109/ICVD.1999.745124","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745124","url":null,"abstract":"This paper describes the design of a compact, ultra low power continuous time programmable filter. Compact programmable filters are required for a number of applications. A particular application is in feedback cancellation filters in hearing aids. Here, a feedback cancellation filter that matches the open loop transfer function is used to suppress acoustic oscillations. Because of the complexity of the transfer function the number of poles in the cancellation filter is fairly large. To realize an integrated cancellation filter an ultra-low power transconductance cell with large linear range has been designed. Both measurement and simulation results are presented to confirm our design. The power consumption for a transconductance cell is comparable to the theoretical minimum bound and is measured to be 0.8 /spl mu/W at a 3 V supply. The linear input range for this cell is 2 V/sub p-p/. In this paper we also compare our design with a programmable switched capacitor implementation and show that there is a significant savings in area as well. The complete filter has been designed, implemented and fabricated in an 2 /spl mu/ CMOS technology.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745210
J. Augustine, W. Lynch, Yuke Wang, A. Al-Khalili
A technique for lossy compression of images is presented, utilizing ideas of logic minimization. The approach specifically addresses the compression of the binary image data originated in block truncation coding (BTC). The binary vector corresponding to a block of 4/spl times/4 pixels is treated as the output of a Boolean function and prime cubes are generated. The largest prime cube is encoded. Bit rate less than 1.5 bits/pel is attained in BTC without many perceivable errors in the reconstructed grey scale image. Training, pre-stored tables or codebooks, and prior knowledge of the image source are not required by the technique which uses simple logic operations. Computational simplicity of the algorithm makes it suitable for VLSI implementation. Potential of the technique in attaining a rate less than 0.5 bit/pel by applying it on image sequences and extending to blocks of larger size is indicated.
提出了一种利用逻辑最小化思想对图像进行有损压缩的方法。该方法特别解决了源于块截断编码(BTC)的二值图像数据的压缩问题。对应于4/spl乘以/4像素块的二进制向量被视为布尔函数的输出，并生成素数立方。最大的质数立方被编码。在重构的灰度图像中，比特率小于1.5 Bit /pel，且没有明显的可感知误差。该技术使用简单的逻辑操作，不需要训练，预先存储的表或代码本以及图像源的先验知识。该算法计算简单，适合大规模集成电路的实现。指出了该技术通过将其应用于图像序列并扩展到更大尺寸的块而获得小于0.5 bit/pel的速率的潜力。
{"title":"Lossy compression of images using logic minimization","authors":"J. Augustine, W. Lynch, Yuke Wang, A. Al-Khalili","doi":"10.1109/ICVD.1999.745210","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745210","url":null,"abstract":"A technique for lossy compression of images is presented, utilizing ideas of logic minimization. The approach specifically addresses the compression of the binary image data originated in block truncation coding (BTC). The binary vector corresponding to a block of 4/spl times/4 pixels is treated as the output of a Boolean function and prime cubes are generated. The largest prime cube is encoded. Bit rate less than 1.5 bits/pel is attained in BTC without many perceivable errors in the reconstructed grey scale image. Training, pre-stored tables or codebooks, and prior knowledge of the image source are not required by the technique which uses simple logic operations. Computational simplicity of the algorithm makes it suitable for VLSI implementation. Potential of the technique in attaining a rate less than 0.5 bit/pel by applying it on image sequences and extending to blocks of larger size is indicated.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121808137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745151
L. Macchiarulo, P. Civera
The problem of disjoint functional decomposition is both an important and difficult task for theoretical reasons and synthesis purposes. The use of efficient representation techniques (decision diagrams) permits a novel approach, which surpasses the preceding ones by identifying graph-structures rather than algebraic relations. In this paper we present a demonstration of a new fact about functional decomposition, and a necessary and sufficient criterion to identify feasible decompositions of a generic function. We implemented and validated the algorithm integrating it in a decision diagram package.
{"title":"Functional decomposition through structural analysis of decision diagrams-the binary and multiple-valued cases","authors":"L. Macchiarulo, P. Civera","doi":"10.1109/ICVD.1999.745151","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745151","url":null,"abstract":"The problem of disjoint functional decomposition is both an important and difficult task for theoretical reasons and synthesis purposes. The use of efficient representation techniques (decision diagrams) permits a novel approach, which surpasses the preceding ones by identifying graph-structures rather than algebraic relations. In this paper we present a demonstration of a new fact about functional decomposition, and a necessary and sufficient criterion to identify feasible decompositions of a generic function. We implemented and validated the algorithm integrating it in a decision diagram package.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134524056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745137
V. Rajesh, R. Moona
In hardware-software codesign paradigm often a performance estimation of the system is needed for hardware-software partitioning. The tremendous growth of application specific embedded systems necessitates high level system design tools for rapid prototyping. This work involves design of a language Sim-nML which will be the base for a high level system design environment. The language is simple, elegant and powerful enough to express the behavior of the processor at instruction level. This language is used as the base for a whole set of tools such as assembler/disassembler and simulator generator. As a part of this work, we implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator. We envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML language.
{"title":"Processor modeling for hardware software codesign","authors":"V. Rajesh, R. Moona","doi":"10.1109/ICVD.1999.745137","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745137","url":null,"abstract":"In hardware-software codesign paradigm often a performance estimation of the system is needed for hardware-software partitioning. The tremendous growth of application specific embedded systems necessitates high level system design tools for rapid prototyping. This work involves design of a language Sim-nML which will be the base for a high level system design environment. The language is simple, elegant and powerful enough to express the behavior of the processor at instruction level. This language is used as the base for a whole set of tools such as assembler/disassembler and simulator generator. As a part of this work, we implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator. We envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML language.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116555544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745144
S. Batterywala, H. Narayanan
In this article we present a method for analysis of electrical networks containing positive resistors, voltage sources and current sources. We lay emphasis on computational aspects like size and positive definiteness of the resulting matrix. Currently the most popular method for analysis of such circuits is modified nodal analysis, which always yields a nonpositive definite matrix whenever voltage sources are present in the circuit. Our method constructs two minors of the underlying graph of the network and then uses these for writing KCE and KVE, thereby resulting in a symmetric positive definite system of equations of smaller size. We exploit the presence of voltage sources, and hence usually get a block diagonal structure in the matrix to be factored. Though our method is general enough and performs better than MNA for all DC circuits, it is specifically aimed towards solving DC circuits encountered during interconnect analysis.
{"title":"Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks","authors":"S. Batterywala, H. Narayanan","doi":"10.1109/ICVD.1999.745144","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745144","url":null,"abstract":"In this article we present a method for analysis of electrical networks containing positive resistors, voltage sources and current sources. We lay emphasis on computational aspects like size and positive definiteness of the resulting matrix. Currently the most popular method for analysis of such circuits is modified nodal analysis, which always yields a nonpositive definite matrix whenever voltage sources are present in the circuit. Our method constructs two minors of the underlying graph of the network and then uses these for writing KCE and KVE, thereby resulting in a symmetric positive definite system of equations of smaller size. We exploit the presence of voltage sources, and hence usually get a block diagonal structure in the matrix to be factored. Though our method is general enough and performs better than MNA for all DC circuits, it is specifically aimed towards solving DC circuits encountered during interconnect analysis.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124184712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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