Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940620
Youngrak Park, Youngmin Kim, W. Choi, J. Woo, Y. Kwon
A broadband watt-level stacked-FET power amplifier (PA) has been developed using 0.15 µm GaAs pHEMT's. A triple-stacked FET structure is used as a unit cell to combine RF voltage swings to achieve high output power and broad bandwidth at the same time. Special care has been taken to solve thermal and instability problems of stacked-FET cells for watt-level applications as well as to optimize the subsequent power combiner for bandwidth. The fabricated PA shows a peak power of 33.7 dBm with a power added efficiency (PAE) of 29.5% at frequency of 18 GHz, and higher than 32 dBm output power from 10 to 21 GHz. The fractional 3 dB output power bandwidth is 84%.
{"title":"X-to-K band broadband watt-level power amplifier using stacked-FET unit cells","authors":"Youngrak Park, Youngmin Kim, W. Choi, J. Woo, Y. Kwon","doi":"10.1109/RFIC.2011.5940620","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940620","url":null,"abstract":"A broadband watt-level stacked-FET power amplifier (PA) has been developed using 0.15 µm GaAs pHEMT's. A triple-stacked FET structure is used as a unit cell to combine RF voltage swings to achieve high output power and broad bandwidth at the same time. Special care has been taken to solve thermal and instability problems of stacked-FET cells for watt-level applications as well as to optimize the subsequent power combiner for bandwidth. The fabricated PA shows a peak power of 33.7 dBm with a power added efficiency (PAE) of 29.5% at frequency of 18 GHz, and higher than 32 dBm output power from 10 to 21 GHz. The fractional 3 dB output power bandwidth is 84%.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"17 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940640
H. Namba, T. Hashimoto, M. Furumiya
This paper presents very small on-chip vertically coiled solenoid inductors (V-solenoid) using 90nm CMOS multilevel interconnect technology. In addition, a variety of areas-saving (10um × 20um) transformers without any additional processing steps are demonstrated: a V-solenoid surrounded by another different inside-diameter V-solenoid (dual-tube transformer), a V-solenoid coiled around another one with same dimensions (a double-helix or DNA-like transformer), and face-to-face V-solenoids (face-to-face transformer). Radio-frequency characteristics were evaluated on the basis of 2-port S-parameter measurements. Measured self-resonance frequencies resulted in higher than 40GHz, and coupling coefficients were larger than 0.6.
{"title":"On-chip vertically coiled solenoid inductors and transformers for RF SoC using 90nm CMOS interconnect technology","authors":"H. Namba, T. Hashimoto, M. Furumiya","doi":"10.1109/RFIC.2011.5940640","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940640","url":null,"abstract":"This paper presents very small on-chip vertically coiled solenoid inductors (V-solenoid) using 90nm CMOS multilevel interconnect technology. In addition, a variety of areas-saving (10um × 20um) transformers without any additional processing steps are demonstrated: a V-solenoid surrounded by another different inside-diameter V-solenoid (dual-tube transformer), a V-solenoid coiled around another one with same dimensions (a double-helix or DNA-like transformer), and face-to-face V-solenoids (face-to-face transformer). Radio-frequency characteristics were evaluated on the basis of 2-port S-parameter measurements. Measured self-resonance frequencies resulted in higher than 40GHz, and coupling coefficients were larger than 0.6.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131027241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940595
Jian Chen, Liang Rong, F. Jonsson, Lirong Zheng
A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.
{"title":"All-digital transmitter based on ADPLL and phase synchronized delta sigma modulator","authors":"Jian Chen, Liang Rong, F. Jonsson, Lirong Zheng","doi":"10.1109/RFIC.2011.5940595","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940595","url":null,"abstract":"A novel architecture of all-digital polar transmitters is proposed, mainly composed of an all digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma (ΔΣ) modulator for envelop modulation and a high efficiency class-D PA. The low noise ADPLL and high oversample ΔΣ modulator relax filter design, enabling the use of a on-chip filter. The differential signaling scheme enhances the power of the fundamental tone and suppresses DC and high harmonics. The transmitter was fabricated in a 90nm digital CMOS process, occupying 1.4 mm2. The measurement results demonstrate effectiveness of the architecture. The digital transmitter consumes 58 mW power from a 1 V supply, delivering a 6.81-dBm output.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124971957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940592
R. Sadhwani, A. Ben-Bassat, R. Banin, H. Shang, B. Jann, O. Degani
We report a novel harmonic LOG based direct conversion RF transceiver for 802.11n radio. This multi-comm transceiver consists of Bluetooth SoC and WiFi, it includes 19–24GHz VCO, integrated front-end including WiFi T/R and WiFi-BT switches. Fabricated in 90nm digital CMOS technology, this IC consumes 422/560mW (Rx/Tx 802.11n 300/150Mbps), 110mW in BT mode, with an area of approx 19mm2. A peak saturated power of 24/9dBm is achieved at antenna in WiFi/BT mode.
{"title":"A fully integrated 802.11n radio with 24GHz harmonic LO generation for low-cost, low power, multi-standard systems","authors":"R. Sadhwani, A. Ben-Bassat, R. Banin, H. Shang, B. Jann, O. Degani","doi":"10.1109/RFIC.2011.5940592","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940592","url":null,"abstract":"We report a novel harmonic LOG based direct conversion RF transceiver for 802.11n radio. This multi-comm transceiver consists of Bluetooth SoC and WiFi, it includes 19–24GHz VCO, integrated front-end including WiFi T/R and WiFi-BT switches. Fabricated in 90nm digital CMOS technology, this IC consumes 422/560mW (Rx/Tx 802.11n 300/150Mbps), 110mW in BT mode, with an area of approx 19mm2. A peak saturated power of 24/9dBm is achieved at antenna in WiFi/BT mode.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940683
J. Liu, A. Tang, N. Wang, Q. Gu, R. Berenguer, H. Hsieh, Po-Yi Wu, C. Jou, Mau-Chung Frank Chang
A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.
{"title":"A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS","authors":"J. Liu, A. Tang, N. Wang, Q. Gu, R. Berenguer, H. Hsieh, Po-Yi Wu, C. Jou, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2011.5940683","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940683","url":null,"abstract":"A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940611
D. Lin, A. Trasser, H. Schumacher
In this paper a 3.1–10.6 GHz impulse-radio ultra-wideband (IR-UWB) transmitter and a receiver front-end are presented. The transmitter comprises a differential impulse generator mounted chip-on-board on a dipole fed circular slot antenna. It has a low power consumption of 6.6 mW at 200 MHz impulse repetition rate. The receiver front-end, mounted at the feed-point of another dipole antenna, is realized with a fully differential low noise amplifier, an analog multiplier-based correlator and a template impulse generator. The measurement results show a motion tracking capability in the mm range.
{"title":"Low power, fully differential SiGe IR-UWB transmitter and correlation receiver ICs","authors":"D. Lin, A. Trasser, H. Schumacher","doi":"10.1109/RFIC.2011.5940611","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940611","url":null,"abstract":"In this paper a 3.1–10.6 GHz impulse-radio ultra-wideband (IR-UWB) transmitter and a receiver front-end are presented. The transmitter comprises a differential impulse generator mounted chip-on-board on a dipole fed circular slot antenna. It has a low power consumption of 6.6 mW at 200 MHz impulse repetition rate. The receiver front-end, mounted at the feed-point of another dipole antenna, is realized with a fully differential low noise amplifier, an analog multiplier-based correlator and a template impulse generator. The measurement results show a motion tracking capability in the mm range.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128854347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940674
Jaeyoung Ryu, Seung-Yong Cho, Jeongsu Lee, Jongjin Kim, Yeonwoo Ku, K. Kwon, Hyunkoo Kang
Image rejection and harmonic rejection are important performance parameters in wideband low-IF TV system. In this paper, double quadrature harmonic rejection architecture insensitive to gain and/or phase mismatch is proposed to satisfy stringent image rejection ratio (IRR) and harmonic rejection ratio (HRR) for analog/digital TV tuner ICs. Fabricated in 0.13µm CMOS process, more than 60dB of the IRR is achieved over 42–864MHz RF frequency and more than 69dB of the 3rd HRR is achieved over 42–306MHz RF frequency without any calibration.
{"title":"Double quadrature harmonic rejection architecture insensitive to gain and phase mismatch for analog/digital TV tuner IC","authors":"Jaeyoung Ryu, Seung-Yong Cho, Jeongsu Lee, Jongjin Kim, Yeonwoo Ku, K. Kwon, Hyunkoo Kang","doi":"10.1109/RFIC.2011.5940674","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940674","url":null,"abstract":"Image rejection and harmonic rejection are important performance parameters in wideband low-IF TV system. In this paper, double quadrature harmonic rejection architecture insensitive to gain and/or phase mismatch is proposed to satisfy stringent image rejection ratio (IRR) and harmonic rejection ratio (HRR) for analog/digital TV tuner ICs. Fabricated in 0.13µm CMOS process, more than 60dB of the IRR is achieved over 42–864MHz RF frequency and more than 69dB of the 3rd HRR is achieved over 42–306MHz RF frequency without any calibration.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940707
Sachin Kalia, M. Elbadry, B. Sadhu, S. Patnaik, J. Qiu, R. Harjani
This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.
{"title":"A simple, unified phase noise model for injection-locked oscillators","authors":"Sachin Kalia, M. Elbadry, B. Sadhu, S. Patnaik, J. Qiu, R. Harjani","doi":"10.1109/RFIC.2011.5940707","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940707","url":null,"abstract":"This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940591
Kyujin Oh, S. Sankaran, Hsin-Ta Wu, Jau-Jr Lin, M. Hwang, K. O. Kenneth
A full-duplex transceiver for wireless inter-chip data communication in an engine controller board of hybrid electric vehicles that for the first time integrates an on-chip antenna and a duplexer, as well as allowing operation without a crystal frequency reference is demonstrated. The BER degradation of RX due to the TX operation is negligible when the input power is greater than −44dBm necessary to achieve BER of less than 10−12. The transceiver fabricated in 0.13µm CMOS consumes 245mW.
{"title":"Full-duplex crystalless CMOS transceiver with an on-chip antenna for wireless communication in engine controller board of hybrid electric vehicles","authors":"Kyujin Oh, S. Sankaran, Hsin-Ta Wu, Jau-Jr Lin, M. Hwang, K. O. Kenneth","doi":"10.1109/RFIC.2011.5940591","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940591","url":null,"abstract":"A full-duplex transceiver for wireless inter-chip data communication in an engine controller board of hybrid electric vehicles that for the first time integrates an on-chip antenna and a duplexer, as well as allowing operation without a crystal frequency reference is demonstrated. The BER degradation of RX due to the TX operation is negligible when the input power is greater than −44dBm necessary to achieve BER of less than 10−12. The transceiver fabricated in 0.13µm CMOS consumes 245mW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126549540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940637
D. Titz, R. Pilard, F. Ferrero, F. Gianesello, D. Gloria, C. Luxey, P. Brachat, G. Jacquemod
During past years, various research team have been implied in the development of 60GHz chipset solution, using both BiCMOS or advanced CMOS technologies. But for the 60GHz market to flourish, not only low cost RFICs are required, low cost antennas and packages also are. In order to address these issues, we review in this paper achievable antenna performance using High Resistivity (HR) silicon technologies, by discussing possible integration schemes, antenna design and 3D on wafer characterization. Antenna gain of 3.9 dBi @ 60GHz has been measured making HR Si a promising technbology to address applications packaged in millimeter-wave low cost technology.
{"title":"60GHz antenna integrated on High Resistivity silicon technologies targeting WHDMI applications","authors":"D. Titz, R. Pilard, F. Ferrero, F. Gianesello, D. Gloria, C. Luxey, P. Brachat, G. Jacquemod","doi":"10.1109/RFIC.2011.5940637","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940637","url":null,"abstract":"During past years, various research team have been implied in the development of 60GHz chipset solution, using both BiCMOS or advanced CMOS technologies. But for the 60GHz market to flourish, not only low cost RFICs are required, low cost antennas and packages also are. In order to address these issues, we review in this paper achievable antenna performance using High Resistivity (HR) silicon technologies, by discussing possible integration schemes, antenna design and 3D on wafer characterization. Antenna gain of 3.9 dBi @ 60GHz has been measured making HR Si a promising technbology to address applications packaged in millimeter-wave low cost technology.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：