Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940675
Huijung Kim, Sanghoon Kang, Jeong-Hyun Choi, Taewan Kim, Bo-Wei Lee, Jong-Dae Bae, Wooseung Choo, Hojin Park, Byeong-ha Park
A dual-band digital TV tuner for CMMB application SoC is presented. The single-chip SoC satisfies all requirements of CMMB application with margin. Moreover, the SoC meets the GSM IOP which means the co-operation GSM transmitter and mobile TV reception. To suppress GSM transmitter signal in UHF band, LC-tuned load and tunable input matching scheme are adopted in UHF LNA. The SoC consists of two RF LNAs covering the 470 to 798MHz (UHF), and 2635 to 2660MHz (S-BAND) bands, an analog baseband filter supporting low pass filtering for direct conversion, and ΔΣ fractional-N synthesizer with one VCO. The measured sensitivity at UHF for the QPSK mode is −9.8dBm with ADC clock shift scheme.
{"title":"A dual-band digital TV tuner for CMMB application SoC","authors":"Huijung Kim, Sanghoon Kang, Jeong-Hyun Choi, Taewan Kim, Bo-Wei Lee, Jong-Dae Bae, Wooseung Choo, Hojin Park, Byeong-ha Park","doi":"10.1109/RFIC.2011.5940675","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940675","url":null,"abstract":"A dual-band digital TV tuner for CMMB application SoC is presented. The single-chip SoC satisfies all requirements of CMMB application with margin. Moreover, the SoC meets the GSM IOP which means the co-operation GSM transmitter and mobile TV reception. To suppress GSM transmitter signal in UHF band, LC-tuned load and tunable input matching scheme are adopted in UHF LNA. The SoC consists of two RF LNAs covering the 470 to 798MHz (UHF), and 2635 to 2660MHz (S-BAND) bands, an analog baseband filter supporting low pass filtering for direct conversion, and ΔΣ fractional-N synthesizer with one VCO. The measured sensitivity at UHF for the QPSK mode is −9.8dBm with ADC clock shift scheme.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125873117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940597
T. Barton, SungWon Chung, P. Godoy, J. Dawson
A digital-to-RF phase modulator based on a single current-steering DAC is presented, including a carrier pre-rotation scheme that prevents phase inaccuracy due to carrier feedthrough. The phase modulator has been fabricated in a standard 65-nm CMOS process and draws 1.9 mW from a 1-V supply. The modulator achieves 12-bit resolution at a measured 200 MSamples/second, state-of-the-art performance in both resolution and sampling speed. It has sufficient speed to allow for oversampling to shape the output spectrum and therefore reduce filtering requirements, as demonstrated through a 32x oversampled 8-PSK signal at 6.25 MSymbols/second with under 6.1% EVM.
{"title":"A 12-bit resolution, 200-MSample/second phase modulator for a 2.5GHz carrier with discrete carrier pre-rotation in 65nm CMOS","authors":"T. Barton, SungWon Chung, P. Godoy, J. Dawson","doi":"10.1109/RFIC.2011.5940597","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940597","url":null,"abstract":"A digital-to-RF phase modulator based on a single current-steering DAC is presented, including a carrier pre-rotation scheme that prevents phase inaccuracy due to carrier feedthrough. The phase modulator has been fabricated in a standard 65-nm CMOS process and draws 1.9 mW from a 1-V supply. The modulator achieves 12-bit resolution at a measured 200 MSamples/second, state-of-the-art performance in both resolution and sampling speed. It has sufficient speed to allow for oversampling to shape the output spectrum and therefore reduce filtering requirements, as demonstrated through a 32x oversampled 8-PSK signal at 6.25 MSymbols/second with under 6.1% EVM.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126960334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940648
R. Debroucke, A. Pottrain, D. Titz, F. Gianesello, D. Gloria, C. Luxey, C. Gaquière
Nowadays capabilities offered by advanced silicon technologies enable both mmw design and agile circuits development, then the development of high performance tunable capacitance is now mandatory. One of the challenge to develop this component is to be able to design capacitance with a tuning range higher than 4 from RF up to millimeter wave range. Variable capacitance like MOS varactor does not meet circuit specifications due to their low tuning range and very high non linearity. Digital capacitances are a good candidate to address that need and this paper review the design, optimization and characterization of digital tunable capacitance (DTC). Specific DTC with series or traveling wave architecture are also address, allowing to synthesize high performance capacitance up to 110GHz regarding 10dBm linearity and a tuning ratio equal to 13. Those developments have been carried out using STMicroelectronics BiCMOS 0.13um millimeter wave technology. Finally, the design of a 60GHz Reflection Type Phase Shifter (RTPS) using 4 bits DTC is presented showing insertion loss less than 6dB and a phase shift of 62°.
{"title":"CMOS digital tunable capacitance with tuning ratio up to 13 and 10dBm linearity for RF and millimeterwave design","authors":"R. Debroucke, A. Pottrain, D. Titz, F. Gianesello, D. Gloria, C. Luxey, C. Gaquière","doi":"10.1109/RFIC.2011.5940648","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940648","url":null,"abstract":"Nowadays capabilities offered by advanced silicon technologies enable both mmw design and agile circuits development, then the development of high performance tunable capacitance is now mandatory. One of the challenge to develop this component is to be able to design capacitance with a tuning range higher than 4 from RF up to millimeter wave range. Variable capacitance like MOS varactor does not meet circuit specifications due to their low tuning range and very high non linearity. Digital capacitances are a good candidate to address that need and this paper review the design, optimization and characterization of digital tunable capacitance (DTC). Specific DTC with series or traveling wave architecture are also address, allowing to synthesize high performance capacitance up to 110GHz regarding 10dBm linearity and a tuning ratio equal to 13. Those developments have been carried out using STMicroelectronics BiCMOS 0.13um millimeter wave technology. Finally, the design of a 60GHz Reflection Type Phase Shifter (RTPS) using 4 bits DTC is presented showing insertion loss less than 6dB and a phase shift of 62°.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130696550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940717
Helen Kim, M. Green, B. Miller, Andrew K. Bolstad, D. Santiago
An active filter with a 50 Ω buffer suitable as an anti-alias filter to drive a highly linear ADC is implemented in 0.13 µm SiGe BiCMOS. This 6th-order Chebyshev filter has a 3 dB cutoff frequency of 28.3 MHz and achieves 36.5 dBm OIP3. Nonlinear digital equalization further improves OIP3 to 43.6 dBm. Measurements show 92 dB of rejection at the stopband and a gain of 49 dB. The measured in-band OIP3 of 43.6 dBm is 19 dB higher than previously published designs.
{"title":"An active filter achieving 43.6dBm OIP3","authors":"Helen Kim, M. Green, B. Miller, Andrew K. Bolstad, D. Santiago","doi":"10.1109/RFIC.2011.5940717","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940717","url":null,"abstract":"An active filter with a 50 Ω buffer suitable as an anti-alias filter to drive a highly linear ADC is implemented in 0.13 µm SiGe BiCMOS. This 6<sup>th</sup>-order Chebyshev filter has a 3 dB cutoff frequency of 28.3 MHz and achieves 36.5 dBm OIP<inf>3</inf>. Nonlinear digital equalization further improves OIP<inf>3</inf> to 43.6 dBm. Measurements show 92 dB of rejection at the stopband and a gain of 49 dB. The measured in-band OIP<inf>3</inf> of 43.6 dBm is 19 dB higher than previously published designs.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940599
U. Mayer, M. Wickert, R. Eickhoff, F. Ellinger
This paper presents an active BiCMOS vector modulator based RF weighting circuit suitable for WLAN diversity transceivers. It features a LNA, a SPI and 8-bit DACs for vector control and internal references. When mounted on a PCB, it delivers a maximum gain of 12 dB at 5.6 GHz. It draws a current of 17 mA from a 3.3 V supply. The whole design is free of bulky inductors thus requiring an area of only 1.3 mm2.
{"title":"Multiband mixed-signal vector modulator IC","authors":"U. Mayer, M. Wickert, R. Eickhoff, F. Ellinger","doi":"10.1109/RFIC.2011.5940599","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940599","url":null,"abstract":"This paper presents an active BiCMOS vector modulator based RF weighting circuit suitable for WLAN diversity transceivers. It features a LNA, a SPI and 8-bit DACs for vector control and internal references. When mounted on a PCB, it delivers a maximum gain of 12 dB at 5.6 GHz. It draws a current of 17 mA from a 3.3 V supply. The whole design is free of bulky inductors thus requiring an area of only 1.3 mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131850335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940602
Saihua Lin, K. Ng, H. Wong, Kwai-Man Luk, S. Wong, A. Poon
An RF-path 60-GHz band 4-element array using proposed phase-oversampling vector modulation is implemented in 65-nm CMOS. Digitally controlled semi-lookup table method is proposed to compensate for non-idealities in circuits, antenna array, and interfaces. Accurate and high resolution control on the gain and phase is demonstrated. The receiver features an NF of 5.6 dB and 3.5° phase resolution at a backoff of 3 dB. It dissipates 178mW from 1-V supply and obtains 18.5 dB gain for each channel.
{"title":"A 60GHz digitally controlled RF beamforming array in 65nm CMOS with off-chip antennas","authors":"Saihua Lin, K. Ng, H. Wong, Kwai-Man Luk, S. Wong, A. Poon","doi":"10.1109/RFIC.2011.5940602","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940602","url":null,"abstract":"An RF-path 60-GHz band 4-element array using proposed phase-oversampling vector modulation is implemented in 65-nm CMOS. Digitally controlled semi-lookup table method is proposed to compensate for non-idealities in circuits, antenna array, and interfaces. Accurate and high resolution control on the gain and phase is demonstrated. The receiver features an NF of 5.6 dB and 3.5° phase resolution at a backoff of 3 dB. It dissipates 178mW from 1-V supply and obtains 18.5 dB gain for each channel.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127988449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940704
F. Bohn, K. Dasgupta, A. Hajimiri
On-chip spurious tone detection and correction in an 8–12 GHz CMOS synthesizer is used to automatically reduce spurious output tones at different offset frequencies by up to 20dB. Using synchronous detection, sensitivity is limited by detection time only. The presented methods are generally applicable to frequency synthesizers and phased-locked loops in various applications.
{"title":"Closed-loop spurious tone reduction for self-healing frequency synthesizers","authors":"F. Bohn, K. Dasgupta, A. Hajimiri","doi":"10.1109/RFIC.2011.5940704","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940704","url":null,"abstract":"On-chip spurious tone detection and correction in an 8–12 GHz CMOS synthesizer is used to automatically reduce spurious output tones at different offset frequencies by up to 20dB. Using synchronous detection, sensitivity is limited by detection time only. The presented methods are generally applicable to frequency synthesizers and phased-locked loops in various applications.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134088066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940657
Steven Callender, A. Niknejad
This paper presents the design of a 1 GHz Delay-Locked Loop (DLL) with embedded phase interpolation. The DLL was designed in a 0.13µm SiGe BiCMOS process and provides a measured single-tap phase range of 50ps (18°) with an average and worst-case phase resolution of 1.36ps (0.49°) and 5ps (1.8°), respectively. This translates to beamsteering resolutions of < 3.5mm in free space when integrated into mm-wave imagers that utilize time-domain beamforming. The DLL has an average output rms-jitter (across all interpolation steps) of 860fs. The DLL consumes 33 mW of power and occupies an area of 0.185mm2.
本文设计了一种内置相位插值的1ghz延时锁相环(DLL)。DLL采用0.13 μ m SiGe BiCMOS工艺设计，可提供50ps(18°)的单相测量范围，平均和最差相位分辨率分别为1.36ps(0.49°)和5ps(1.8°)。这意味着波束转向分辨率为<当集成到利用时域波束形成的毫米波成像仪中时，自由空间为3.5mm。DLL的平均输出均方根抖动(跨所有插值步骤)为860fs。DLL的功耗为33 mW，占地面积为0.185mm2。
{"title":"A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation","authors":"Steven Callender, A. Niknejad","doi":"10.1109/RFIC.2011.5940657","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940657","url":null,"abstract":"This paper presents the design of a 1 GHz Delay-Locked Loop (DLL) with embedded phase interpolation. The DLL was designed in a 0.13µm SiGe BiCMOS process and provides a measured single-tap phase range of 50ps (18°) with an average and worst-case phase resolution of 1.36ps (0.49°) and 5ps (1.8°), respectively. This translates to beamsteering resolutions of < 3.5mm in free space when integrated into mm-wave imagers that utilize time-domain beamforming. The DLL has an average output rms-jitter (across all interpolation steps) of 860fs. The DLL consumes 33 mW of power and occupies an area of 0.185mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134553991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5946283
X. Wang, B. Busze, J. Romme, R. Vinella, C. Zhou, K. Philips, H. de Groot
A frequency-locked-loop optimized for output frequency accuracy and locking time is implemented in a 90nm CMOS technology. The output frequency ranges from 7–9.8GHz with a reference frequency at 130MHz. The accuracy of the output frequency is 130ppm, achieved by minimizing and dithering the fine tuning bits of the oscillator. The estimated locking-time is below 50 reference clock cycles, thanks to the frequency locking nature. A binary frequency detector is adopted, lending the FLL naturally to a digital implementation, therefore avoiding the control voltage leakage issue. The measured phase noise @1MHz is −67dBc/Hz. The implementation offers itself a suitable solution for duty-cycled system.
{"title":"A multi-GHz 130ppm accuracy FLL for duty-cycled systems","authors":"X. Wang, B. Busze, J. Romme, R. Vinella, C. Zhou, K. Philips, H. de Groot","doi":"10.1109/RFIC.2011.5946283","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5946283","url":null,"abstract":"A frequency-locked-loop optimized for output frequency accuracy and locking time is implemented in a 90nm CMOS technology. The output frequency ranges from 7–9.8GHz with a reference frequency at 130MHz. The accuracy of the output frequency is 130ppm, achieved by minimizing and dithering the fine tuning bits of the oscillator. The estimated locking-time is below 50 reference clock cycles, thanks to the frequency locking nature. A binary frequency detector is adopted, lending the FLL naturally to a digital implementation, therefore avoiding the control voltage leakage issue. The measured phase noise @1MHz is −67dBc/Hz. The implementation offers itself a suitable solution for duty-cycled system.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131870803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940702
Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, H. Qian
A synchronous 50% duty cycle divide-by-3 divider up to 6GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the input clock signal. These cells are not stand alone, but coupled with each other. Thanks to the coupling and input current with 120° phase splitting, the outputs of the three cells are locked at the 1/3 input frequencies with 60°phase splitting, which means that the outputs are of an accurate 50% duty cycle. Injection behavior model is proposed for analysis, and some design guidelines are acquired here. This divider is fabricated in 0.18µm CMOS process and works with a nominal supply voltage of 1.8V. The measured results indicate that the locking range of this divider is 4GHz (from 2.5GHz to 6.5GHz) at an input power of 0dBm with about 4mW power dissipation. As high as 28dB second harmonic suppression of a single-ended output proves that this proposed divider realizes a true 50% duty cycle signal.
{"title":"A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz","authors":"Chunyuan Zhou, Lei Zhang, Li Zhang, Yan Wang, Zhiping Yu, H. Qian","doi":"10.1109/RFIC.2011.5940702","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940702","url":null,"abstract":"A synchronous 50% duty cycle divide-by-3 divider up to 6GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the input clock signal. These cells are not stand alone, but coupled with each other. Thanks to the coupling and input current with 120° phase splitting, the outputs of the three cells are locked at the 1/3 input frequencies with 60°phase splitting, which means that the outputs are of an accurate 50% duty cycle. Injection behavior model is proposed for analysis, and some design guidelines are acquired here. This divider is fabricated in 0.18µm CMOS process and works with a nominal supply voltage of 1.8V. The measured results indicate that the locking range of this divider is 4GHz (from 2.5GHz to 6.5GHz) at an input power of 0dBm with about 4mW power dissipation. As high as 28dB second harmonic suppression of a single-ended output proves that this proposed divider realizes a true 50% duty cycle signal.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131953861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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