Pub Date : 2024-03-22DOI: 10.1109/TSM.2024.3379949
Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett
This study focuses on energy saving for a Taiwan high-tech DRAM factory as the primary research subject. Collecting operational parameters related to various facility systems and process equipment is initially performed by using the developed energy conversion factors (ECF) calculator. Moreover, innovative fab energy simulation (FES) software has been designed by Taipei Tech. This software is designed for high-tech fab energy consumption analysis. The annual energy consumption data for fabs can be calculated. This data is then converted into carbon dioxide emissions using the power carbon emission coefficient provided by the Bureau of Energy, Ministry of Economic Affairs Taiwan. In this study, five different energy-saving strategies were proposed. The energy consumption and carbon emissions distribution were evaluated to assess the benefits of those different techniques. The findings show that among the existing operational facilities, the use of an exhaust air conditioning unit with reduced enthalpy value setting, with lowered supply air temperature, demonstrates the highest energy-saving. This technique has the potential to annually reduce carbon emissions by approximately 623,158 kg CO2 and operational costs by NT${$}$ 6,005,764 (189,602 U.S.${$}$ ). This can reduce the overall manufacturing cost and is also beneficial for the environment.
本研究以台湾一家高科技 DRAM 工厂的节能为主要研究对象。首先使用已开发的能源转换系数（ECF）计算器收集与各种设施系统和工艺设备相关的运行参数。此外，台北科技大学还设计了创新的工厂能源模拟（FES）软件。该软件专为高科技工厂能耗分析而设计。它可以计算出工厂的年度能耗数据。然后，利用台湾经济部能源局提供的电力碳排放系数，将这些数据转换为二氧化碳排放量。本研究提出了五种不同的节能策略。对能源消耗和碳排放分布进行了评估，以评估这些不同技术的效益。研究结果表明，在现有的运行设施中，使用降低焓值设置的排风空调机，同时降低送风温度，节能效果最好。这项技术每年可减少约 623,158 千克二氧化碳排放，减少运营成本 6,005,764 新台币（189,602 美元）。这可以降低总体制造成本，同时也有利于环境。
{"title":"Energy Consumption and Carbon Emission Reduction in HVAC System of a Dynamic Random Access Memory (DRAM) Semiconductor Fabrication Plant (fab)","authors":"Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett","doi":"10.1109/TSM.2024.3379949","DOIUrl":"10.1109/TSM.2024.3379949","url":null,"abstract":"This study focuses on energy saving for a Taiwan high-tech DRAM factory as the primary research subject. Collecting operational parameters related to various facility systems and process equipment is initially performed by using the developed energy conversion factors (ECF) calculator. Moreover, innovative fab energy simulation (FES) software has been designed by Taipei Tech. This software is designed for high-tech fab energy consumption analysis. The annual energy consumption data for fabs can be calculated. This data is then converted into carbon dioxide emissions using the power carbon emission coefficient provided by the Bureau of Energy, Ministry of Economic Affairs Taiwan. In this study, five different energy-saving strategies were proposed. The energy consumption and carbon emissions distribution were evaluated to assess the benefits of those different techniques. The findings show that among the existing operational facilities, the use of an exhaust air conditioning unit with reduced enthalpy value setting, with lowered supply air temperature, demonstrates the highest energy-saving. This technique has the potential to annually reduce carbon emissions by approximately 623,158 kg CO2 and operational costs by NT\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000 6,005,764 (189,602 U.S.\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000). This can reduce the overall manufacturing cost and is also beneficial for the environment.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"174-184"},"PeriodicalIF":2.7,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-21DOI: 10.1109/TSM.2024.3403230
Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo
In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures.
{"title":"Optimization of Void Defects at TiN/Si:HfO2 Interface for 3-D Ferroelectric Memory","authors":"Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo","doi":"10.1109/TSM.2024.3403230","DOIUrl":"10.1109/TSM.2024.3403230","url":null,"abstract":"In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"542-545"},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/TSM.2024.3402214
Se Yun Jo;Minsuk Choi;Sang Jeen Hong
Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms.
{"title":"Plasma Pretreatment System for the Reduction of By-Product Particles in Semiconductor Manufacturing","authors":"Se Yun Jo;Minsuk Choi;Sang Jeen Hong","doi":"10.1109/TSM.2024.3402214","DOIUrl":"10.1109/TSM.2024.3402214","url":null,"abstract":"Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"381-393"},"PeriodicalIF":2.3,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3394310
{"title":"Call for Nominations: 2024 EDS Early Career Award","authors":"","doi":"10.1109/TSM.2024.3394310","DOIUrl":"https://doi.org/10.1109/TSM.2024.3394310","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"222-222"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3378554
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2024.3378554","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378554","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.
随着 5G、人工智能和物联网等高度发达时代的到来，最新一代集成电路的设计需要更小尺寸的 FET、更低的时间延迟和更低的功耗。为了应对这些进步带来的挑战，人们正在开发 k 值低于二氧化硅（低 k 值，<4.0）的材料，以减少电阻电容 (RC) 时间延迟和功耗。虽然低 k 值材料仍在不断涌现，但各材料公司仍在不断推出创新的低 k 值产品，如不同公司推出的 SiLK、Fox、Coral 和 Aurora。同时，考虑到专有商业利益，与这些产品相关的工艺和材料还没有得到清晰的介绍。在本报告中，我们采用了一套新型设备来验证合成低 K 值二氧化硅层的创新配方。厚度测量结果表明，二氧化硅层的沉积率更高，在 8" 晶圆上观察到了极佳的均匀性。此外，介电常数（k）降至 2.35，表明生产出了极佳的低 k 材料。此外，在反应物配方中，我们避免了硅烷和有机硅烷的使用，从而提高了设备的安全性，并有效控制了反应物成本。这些结果凸显了制造集成电路互连层的有利选择。
{"title":"Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits","authors":"Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu","doi":"10.1109/TSM.2024.3374067","DOIUrl":"10.1109/TSM.2024.3374067","url":null,"abstract":"With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"185-189"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140073978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.
在这项工作中，通过在应力记忆技术（SMT）中引入等离子体增强原子层沉积（PEALD）制造的氮化硅薄层，证明了负偏压热不稳定性（NBTI）寿命的显著改善。SiN 薄膜是在具有高拉伸应力的 SiN 层的等离子体增强化学气相沉积 (PECVD) 之前沉积的。结果表明，PEALD SiN 薄膜可以有效抑制可能伴随着界面去钝化的 H2 逸出，从而进一步减少硅/栅介质界面的界面态。因此，PMOSFET 的 NBTI 寿命提高了约 500%，而 NMOSFET 和 PMOSFET 的性能都没有明显下降。
{"title":"Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique","authors":"Cheng-Hao Liang;Zhao-Yang Li;Hao Liu;Yu-Long Jiang","doi":"10.1109/TSM.2024.3397814","DOIUrl":"10.1109/TSM.2024.3397814","url":null,"abstract":"In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"405-409"},"PeriodicalIF":2.3,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140936903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/TSM.2024.3373690
Yiwen Liao;Raphaël Latty;Bin Yang
Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.
{"title":"Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation","authors":"Yiwen Liao;Raphaël Latty;Bin Yang","doi":"10.1109/TSM.2024.3373690","DOIUrl":"10.1109/TSM.2024.3373690","url":null,"abstract":"Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"199-206"},"PeriodicalIF":2.7,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140057229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/TSM.2024.3396994
Min Ho Kim;Hye Eun Sim;Sang Jeen Hong
Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing.
{"title":"Part-Level Fault Classification of Mass Flow Controller Drift in Plasma Deposition Equipment","authors":"Min Ho Kim;Hye Eun Sim;Sang Jeen Hong","doi":"10.1109/TSM.2024.3396994","DOIUrl":"10.1109/TSM.2024.3396994","url":null,"abstract":"Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"373-380"},"PeriodicalIF":2.3,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140882583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：