Pub Date : 2024-10-02DOI: 10.1016/j.microrel.2024.115516
Shan Wan, Tingting Wen, Bokai Liao, Xingpeng Guo
Silver nanowire (AgNW) transparent conductive thin films possess high flexibility, high conductivity, high light transmittance and etc., demonstrating significant advantages in flexible electronics applications. However, in the service occasions, the coupled effect of corrosion and mechanical force easily makes the electrical conductivity of AgNW films deteriorate or even fail, which seriously affects the service reliability of AgNW films. In this work, scanning vibrating electrode technique was firstly used to confirm the existence of electrochemical corrosion on AgNW films. Furthermore, electrochemical measurements (including OCP, PDP and EIS) were carried out for researching the electrochemical corrosion process on AgNW films under different environmental factors and mechanical forces. Their surface morphologies and electrical conductivity were characterized and evaluated by the Scanning Electron Microscopy and square resistance tester respectively. Experimental results indicate that the corrosion-mechanics interaction effect aggravates the damage process of electrical conductivity of AgNW films.
{"title":"Corrosion and conductivity damage of AgNW transparent conductive thin films under a simulated sulfur-containing atmosphere and mechanical force","authors":"Shan Wan, Tingting Wen, Bokai Liao, Xingpeng Guo","doi":"10.1016/j.microrel.2024.115516","DOIUrl":"10.1016/j.microrel.2024.115516","url":null,"abstract":"<div><div>Silver nanowire (AgNW) transparent conductive thin films possess high flexibility, high conductivity, high light transmittance and etc., demonstrating significant advantages in flexible electronics applications. However, in the service occasions, the coupled effect of corrosion and mechanical force easily makes the electrical conductivity of AgNW films deteriorate or even fail, which seriously affects the service reliability of AgNW films. In this work, scanning vibrating electrode technique was firstly used to confirm the existence of electrochemical corrosion on AgNW films. Furthermore, electrochemical measurements (including OCP, PDP and EIS) were carried out for researching the electrochemical corrosion process on AgNW films under different environmental factors and mechanical forces. Their surface morphologies and electrical conductivity were characterized and evaluated by the Scanning Electron Microscopy and square resistance tester respectively. Experimental results indicate that the corrosion-mechanics interaction effect aggravates the damage process of electrical conductivity of AgNW films.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115516"},"PeriodicalIF":1.6,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142422025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-02DOI: 10.1016/j.microrel.2024.115515
Bin An , Hongliang Zhou , Jun Cao , Pingmei Ming , Jie Xia , Jingguang Yao , John Persic
Palladium coated copper (PCC) wire is an emerging bonding wire. There are relatively few studies on the effect of palladium plating thickness and temperature on its bonding performance. In order to investigate the effects of three parameters, namely palladium plating thickness, chip preheating temperature and the free air ball (FAB) initial temperature, on the bonding performance of PCC wires, this paper establishes a transient nonlinear finite element analysis model of thermal coupling between bare copper wires and PCC wires, and simplifies the whole bonding process into two stages of impact and ultrasonic vibration to carry out the experimental simulation. Firstly, the Taguchi orthogonal test method was adopted to obtain the ranking of the degree of influence of the three factors on the bonding results, and the optimum palladium plating thickness and FAB initial temperature of 100 nm and 100 °C were derived, respectively. Then the PCC wires with 100 nm palladium plating thickness were selected, and the bare copper wires were used as the reference, and multiple one-factor simulation experiments were carried out under the condition of changing the chip preheating temperature only. The simulation results show that the FAB and pad stress levels in the bonding results of the PCC wires are significantly higher than those of the bare copper wires, but the GaN layer stress is less than that of the bare copper wires. Moreover, there is an approximate parabolic relationship between the maximum stresses of pad and GaN layer and the preheating temperature of the chip. In the bonding results of bare copper wire, there is also an approximate parabolic relationship between the maximum stress of FAB and the chip preheating temperature. This parabolic relationship allows a prediction of the optimum chip preheating temperature. Selecting the appropriate palladium plating thickness and controlling the appropriate FAB temperature and chip preheating temperature can improve the bonding quality, and this numerical simulation work can provide a reference for the selection of palladium plating thickness and temperature parameter regulation of PCC wires.
镀钯铜线（PCC）是一种新兴的键合线。关于镀钯厚度和温度对其键合性能影响的研究相对较少。为了研究镀钯厚度、芯片预热温度和自由空气球（FAB）初始温度这三个参数对 PCC 线键合性能的影响，本文建立了裸铜线与 PCC 线热耦合的瞬态非线性有限元分析模型，并将整个键合过程简化为冲击和超声振动两个阶段，进行了实验模拟。首先，采用田口正交试验法得出三个因素对键合结果影响程度的排序，分别得出最佳镀钯厚度和 FAB 初始温度为 100 nm 和 100 ℃。然后选择镀钯厚度为 100 nm 的 PCC 线，以裸铜线为参考，在仅改变芯片预热温度的条件下进行了多次单因素模拟实验。仿真结果表明，PCC 线键合结果中的 FAB 和焊盘应力水平明显高于裸铜线，但 GaN 层应力小于裸铜线。此外，焊盘和 GaN 层的最大应力与芯片的预热温度之间存在近似抛物线的关系。在裸铜线的键合结果中，FAB 的最大应力与芯片预热温度之间也存在近似抛物线关系。通过这种抛物线关系可以预测芯片预热的最佳温度。选择合适的镀钯厚度、控制合适的 FAB 温度和芯片预热温度可以提高键合质量，而这一数值模拟工作可以为 PCC 线镀钯厚度的选择和温度参数的调节提供参考。
{"title":"Simulation study on the effect of palladium layer thickness and temperature on the bonding properties of palladium coated copper wire","authors":"Bin An , Hongliang Zhou , Jun Cao , Pingmei Ming , Jie Xia , Jingguang Yao , John Persic","doi":"10.1016/j.microrel.2024.115515","DOIUrl":"10.1016/j.microrel.2024.115515","url":null,"abstract":"<div><div>Palladium coated copper (PCC) wire is an emerging bonding wire. There are relatively few studies on the effect of palladium plating thickness and temperature on its bonding performance. In order to investigate the effects of three parameters, namely palladium plating thickness, chip preheating temperature and the free air ball (FAB) initial temperature, on the bonding performance of PCC wires, this paper establishes a transient nonlinear finite element analysis model of thermal coupling between bare copper wires and PCC wires, and simplifies the whole bonding process into two stages of impact and ultrasonic vibration to carry out the experimental simulation. Firstly, the Taguchi orthogonal test method was adopted to obtain the ranking of the degree of influence of the three factors on the bonding results, and the optimum palladium plating thickness and FAB initial temperature of 100 nm and 100 °C were derived, respectively. Then the PCC wires with 100 nm palladium plating thickness were selected, and the bare copper wires were used as the reference, and multiple one-factor simulation experiments were carried out under the condition of changing the chip preheating temperature only. The simulation results show that the FAB and pad stress levels in the bonding results of the PCC wires are significantly higher than those of the bare copper wires, but the GaN layer stress is less than that of the bare copper wires. Moreover, there is an approximate parabolic relationship between the maximum stresses of pad and GaN layer and the preheating temperature of the chip. In the bonding results of bare copper wire, there is also an approximate parabolic relationship between the maximum stress of FAB and the chip preheating temperature. This parabolic relationship allows a prediction of the optimum chip preheating temperature. Selecting the appropriate palladium plating thickness and controlling the appropriate FAB temperature and chip preheating temperature can improve the bonding quality, and this numerical simulation work can provide a reference for the selection of palladium plating thickness and temperature parameter regulation of PCC wires.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115515"},"PeriodicalIF":1.6,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142422026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1016/j.microrel.2024.115506
Sachintha De Vas Gunawardena, Nadarajah Narendran
This paper proposes a life test method and a model to predict the time to failure of LED drivers with electrolytic capacitors at the output stage that experience cycled power/thermal conditions. Based on failure rate estimation methods and field studies, degradation of aluminum electrolytic capacitors can be considered a potential point of failure in LED drivers and other power electronic applications. It is essential to identify failure modes, causes, and precursors of failure of electrolytic capacitors to design reliable power electronic circuits and estimate the useful lifetime of the designed drivers for a given application. LED drivers are exposed to elevated temperatures, on-off switching, and cycled thermal conditions like other power electronic converters. Past studies have investigated the parametric degradation of electrolytic capacitors under constant thermal stresses but not under cycled thermal conditions commonly found in lighting applications. Therefore, temperature and thermal cycling were selected as acceleration factors to study the effects of power/thermal cycling on the life of electrolytic capacitors in LED drivers. The accelerated life test showed that the LED driver's useful life had an inverse exponential relationship to the operating temperature of the output capacitor. The thermally cycled conditions did not indicate additional failure mechanisms introduced due to thermal cycling within the tested temperature range. Based on the experimental results, we developed a mathematical modeling technique to estimate the time to failure of LED drivers due to the electrolytic capacitor's parametric degradation with different operating profiles.
本文提出了一种寿命测试方法和模型，用于预测在输出级使用电解电容的 LED 驱动器在经历循环电源/热条件后的失效时间。根据故障率估算方法和现场研究，铝电解电容器的降解可被视为 LED 驱动器和其他电力电子应用中的潜在故障点。确定电解电容器的失效模式、原因和失效前兆对于设计可靠的电力电子电路和估算特定应用中设计驱动器的使用寿命至关重要。与其他电力电子转换器一样，LED 驱动器也暴露在高温、开关和循环热条件下。以往的研究调查了电解电容在恒定热应力下的参数退化情况，但没有调查照明应用中常见的循环热条件下的参数退化情况。因此，我们选择温度和热循环作为加速因素，研究功率/热循环对 LED 驱动器中电解电容器寿命的影响。加速寿命测试表明，LED 驱动器的使用寿命与输出电容器的工作温度呈反指数关系。在热循环条件下，没有发现在测试温度范围内因热循环而引入的其他失效机制。根据实验结果，我们开发了一种数学建模技术，用于估算 LED 驱动器在不同工作曲线下因电解电容参数退化而发生故障的时间。
{"title":"Modeling LED driver lifespan through capacitor degradation due to thermal cycling","authors":"Sachintha De Vas Gunawardena, Nadarajah Narendran","doi":"10.1016/j.microrel.2024.115506","DOIUrl":"10.1016/j.microrel.2024.115506","url":null,"abstract":"<div><div>This paper proposes a life test method and a model to predict the time to failure of LED drivers with electrolytic capacitors at the output stage that experience cycled power/thermal conditions. Based on failure rate estimation methods and field studies, degradation of aluminum electrolytic capacitors can be considered a potential point of failure in LED drivers and other power electronic applications. It is essential to identify failure modes, causes, and precursors of failure of electrolytic capacitors to design reliable power electronic circuits and estimate the useful lifetime of the designed drivers for a given application. LED drivers are exposed to elevated temperatures, on-off switching, and cycled thermal conditions like other power electronic converters. Past studies have investigated the parametric degradation of electrolytic capacitors under constant thermal stresses but not under cycled thermal conditions commonly found in lighting applications. Therefore, temperature and thermal cycling were selected as acceleration factors to study the effects of power/thermal cycling on the life of electrolytic capacitors in LED drivers. The accelerated life test showed that the LED driver's useful life had an inverse exponential relationship to the operating temperature of the output capacitor. The thermally cycled conditions did not indicate additional failure mechanisms introduced due to thermal cycling within the tested temperature range. Based on the experimental results, we developed a mathematical modeling technique to estimate the time to failure of LED drivers due to the electrolytic capacitor's parametric degradation with different operating profiles.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115506"},"PeriodicalIF":1.6,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142327863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1016/j.microrel.2024.115511
M. Rebosolan , M. van Soestbergen , J.J.M. Zaal , T. Hauck , A. Dasgupta , B. Chen
The objective of this work is to develop a microstructure-based simulation approach to assess the fatigue life of solder joints that are used by the microelectronics industry. The developed approach can generate solder joints with random grain morphologies by means of 3D Voronoi tessellation. The anisotropic material behavior of each grain is described by the Garofalo creep equation combined with Hill's definition of the equivalent stress for anisotropic materials. Grain boundaries are implemented as interface elements, with an isotropic creep constitutive model. The stochastic variability in the creep response of solder joints was qualitatively estimated by generating 100 unique solder joints containing 5 to 9 grains, each having a random material orientation. These joints were independently loaded with a realistic stress level for microelectronic products during thermal cycling. The volume-averaged creep strain energy density in the solder joints was used to predict the fatigue life of the solder joints. The results showed a factor of ~4 difference in expected lifetime of the individual solder joints. Next, nine randomly picked solder joints from the above-mentioned pool of 100 were sandwiched between a silicon die and a printed circuit board to form a simulation model of a Wafer-Level Chip-Scale package (WLCSP). The creep strain energy density in the joints was computed for 34 unique cases of the WLCSP. A factor of ~2.5 between the highest and lowest estimate for the solder joint life was found. The slope of the corresponding Weibull distribution equals ~6, which falls within the slopes typical reported for solder joint reliability of WLCSPs.
{"title":"Effect of microstructural variability on fatigue simulations of solder joints","authors":"M. Rebosolan , M. van Soestbergen , J.J.M. Zaal , T. Hauck , A. Dasgupta , B. Chen","doi":"10.1016/j.microrel.2024.115511","DOIUrl":"10.1016/j.microrel.2024.115511","url":null,"abstract":"<div><div>The objective of this work is to develop a microstructure-based simulation approach to assess the fatigue life of solder joints that are used by the microelectronics industry. The developed approach can generate solder joints with random grain morphologies by means of 3D Voronoi tessellation. The anisotropic material behavior of each grain is described by the Garofalo creep equation combined with Hill's definition of the equivalent stress for anisotropic materials. Grain boundaries are implemented as interface elements, with an isotropic creep constitutive model. The stochastic variability in the creep response of solder joints was qualitatively estimated by generating 100 unique solder joints containing 5 to 9 grains, each having a random material orientation. These joints were independently loaded with a realistic stress level for microelectronic products during thermal cycling. The volume-averaged creep strain energy density in the solder joints was used to predict the fatigue life of the solder joints. The results showed a factor of ~4 difference in expected lifetime of the individual solder joints. Next, nine randomly picked solder joints from the above-mentioned pool of 100 were sandwiched between a silicon die and a printed circuit board to form a simulation model of a Wafer-Level Chip-Scale package (WLCSP). The creep strain energy density in the joints was computed for 34 unique cases of the WLCSP. A factor of ~2.5 between the highest and lowest estimate for the solder joint life was found. The slope of the corresponding Weibull distribution equals ~6, which falls within the slopes typical reported for solder joint reliability of WLCSPs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115511"},"PeriodicalIF":1.6,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142324015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1016/j.microrel.2024.115509
Jindian Chen, Jigui Miao, Quan Yin
The degradation process of aluminum electrolytic capacitors(AECs) usually exhibits characteristics such as non-linearity and multi-stage. These degradation features lead to the difficulty to accurately predict the remaining useful life(RUL) of the whole degradation process of AECs. To address this, by dividing the capacitor degradation process into two stages, a two-stage RUL prediction method for AECs considering multiple degradation models is proposed in this paper.In the offline parameter estimation phase, the initial degradation model parameters of two stages are estimated using two-step maximum likelihood estimation combined with particle swarm optimization(PSO) algorithm. In the dynamic parameter updating phase, a sequential Bayesian method is used to update the model parameters. To select the optimal degradation model, an evaluation method based on historical RUL similarity is proposed to calculate the fitness of each model. Finally, the effectiveness of the method is verified on NASA’s accelerated degradation data set and several widely used methods are used for comparison. The experimental results show that the proposed method has higher accuracy, which proves the superiority of the method.
铝电解电容器（AEC）的降解过程通常具有非线性和多阶段等特点。这些降解特征导致难以准确预测铝电解电容器整个降解过程的剩余使用寿命（RUL）。在离线参数估计阶段，采用两步最大似然估计结合粒子群优化（PSO）算法估计两个阶段的初始退化模型参数。在动态参数更新阶段，采用连续贝叶斯方法更新模型参数。为了选择最佳降解模型，提出了一种基于历史 RUL 相似性的评估方法，以计算每个模型的适配度。最后，在 NASA 的加速退化数据集上验证了该方法的有效性，并使用了几种广泛使用的方法进行比较。实验结果表明，提出的方法具有更高的准确性，证明了该方法的优越性。
{"title":"A remaining useful life prediction method of aluminum electrolytic capacitor with adaptive degradation model selection","authors":"Jindian Chen, Jigui Miao, Quan Yin","doi":"10.1016/j.microrel.2024.115509","DOIUrl":"10.1016/j.microrel.2024.115509","url":null,"abstract":"<div><div>The degradation process of aluminum electrolytic capacitors(AECs) usually exhibits characteristics such as non-linearity and multi-stage. These degradation features lead to the difficulty to accurately predict the remaining useful life(RUL) of the whole degradation process of AECs. To address this, by dividing the capacitor degradation process into two stages, a two-stage RUL prediction method for AECs considering multiple degradation models is proposed in this paper.In the offline parameter estimation phase, the initial degradation model parameters of two stages are estimated using two-step maximum likelihood estimation combined with particle swarm optimization(PSO) algorithm. In the dynamic parameter updating phase, a sequential Bayesian method is used to update the model parameters. To select the optimal degradation model, an evaluation method based on historical RUL similarity is proposed to calculate the fitness of each model. Finally, the effectiveness of the method is verified on NASA’s accelerated degradation data set and several widely used methods are used for comparison. The experimental results show that the proposed method has higher accuracy, which proves the superiority of the method.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115509"},"PeriodicalIF":1.6,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142324014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-25DOI: 10.1016/j.microrel.2024.115512
Bo-Ding Wu, Fei-Yi Hung, Kang-Pei Chan
In this study, we introduced trace amounts of silver and nickel into 500 μm diameter copper wires to form micro-alloyed copper wires used in insulated gate bipolar transistors (IGBT). The addition of silver and nickel enhanced the mechanical properties of the conductors and suppressed the work hardening effect, significantly improving the power cyclic lifetime. Additionally, this study conducted chlorination and high-temperature oxidation test to compare the application characteristics of the heavy micro-alloyed copper wires with pure copper wires, through tensile and bending test, as well as electrical property comparisons. Finally, Cu50Ni (50 ppm Ni) wires were selected and nickel ceramic substrates for wire bonding to evaluate module electrical properties and bonding reliability.
In the chloride test, there was no significant pitting corrosion observed in copper wire, and the micro-alloyed copper wire outperformed the pure copper wires in terms of bending lifetime and power cycling performance. In the high-temperature oxidation test, an oxide layer of cuprous oxide formed on the surface of all wires. The pure copper wire exhibited a significant increase in resistance. Notably, the micro-alloyed copper wires had better resistance to oxidation. Regarding wire bonding, the use of Cu50Ni wires and nickel ceramic substrates reduced the diffusion rate of nickel atoms from the substrate to the copper wire, forming a thinner alloy diffusion layer. This prevented electrical degradation and achieved high bonding reliability, especially under higher bonding forces. These findings confirm that micro-alloyed copper wires are suitable for high-power applications.
{"title":"500 μm heavy micro-alloyed Cu wire for IGBT application: The study on microstructure characteristics, electrical fatigue fracture mechanism and bonding reliability","authors":"Bo-Ding Wu, Fei-Yi Hung, Kang-Pei Chan","doi":"10.1016/j.microrel.2024.115512","DOIUrl":"10.1016/j.microrel.2024.115512","url":null,"abstract":"<div><div>In this study, we introduced trace amounts of silver and nickel into 500 μm diameter copper wires to form micro-alloyed copper wires used in insulated gate bipolar transistors (IGBT). The addition of silver and nickel enhanced the mechanical properties of the conductors and suppressed the work hardening effect, significantly improving the power cyclic lifetime. Additionally, this study conducted chlorination and high-temperature oxidation test to compare the application characteristics of the heavy micro-alloyed copper wires with pure copper wires, through tensile and bending test, as well as electrical property comparisons. Finally, Cu<img>50Ni (50 ppm Ni) wires were selected and nickel ceramic substrates for wire bonding to evaluate module electrical properties and bonding reliability.</div><div>In the chloride test, there was no significant pitting corrosion observed in copper wire, and the micro-alloyed copper wire outperformed the pure copper wires in terms of bending lifetime and power cycling performance. In the high-temperature oxidation test, an oxide layer of cuprous oxide formed on the surface of all wires. The pure copper wire exhibited a significant increase in resistance. Notably, the micro-alloyed copper wires had better resistance to oxidation. Regarding wire bonding, the use of Cu<img>50Ni wires and nickel ceramic substrates reduced the diffusion rate of nickel atoms from the substrate to the copper wire, forming a thinner alloy diffusion layer. This prevented electrical degradation and achieved high bonding reliability, especially under higher bonding forces. These findings confirm that micro-alloyed copper wires are suitable for high-power applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115512"},"PeriodicalIF":1.6,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142318651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fretting is one of the common phenomena during the use of electrical connectors, which is usually affected by the working environment and has a significant impact on the electrical contact life. In this work, the influence of different fretting wear conditions on electrical contact failure is studied by combining theoretical analysis, finite element simulation and experimental verification. The mechanical and electrical properties are related through experiments in different environments. It can be concluded that the main causes of electrical contact failure are contact structure deterioration and surface coating loss. Increased fretting cycles aggravate the surface fretting wear of high-speed electrical connectors. The failure of electrical connectors can be delayed by a decrease in frequency and amplitude in addition to an increase in coating thickness. The insertion and withdrawal force gradually decreases due to continuous wear. The failure mechanism of electrical contact during wear is also explained. It provides theoretical guidance for predicting the life of electrical connectors.
{"title":"Electrical contact reliability investigation of high-speed electrical connectors under fretting wear behavior","authors":"Xin Lei, Chenzefang Feng, Weishan Lv, Yuqi Zhou, Chuanguo Xiong, Yuhan Gao, Fulong Zhu","doi":"10.1016/j.microrel.2024.115510","DOIUrl":"10.1016/j.microrel.2024.115510","url":null,"abstract":"<div><div>Fretting is one of the common phenomena during the use of electrical connectors, which is usually affected by the working environment and has a significant impact on the electrical contact life. In this work, the influence of different fretting wear conditions on electrical contact failure is studied by combining theoretical analysis, finite element simulation and experimental verification. The mechanical and electrical properties are related through experiments in different environments. It can be concluded that the main causes of electrical contact failure are contact structure deterioration and surface coating loss. Increased fretting cycles aggravate the surface fretting wear of high-speed electrical connectors. The failure of electrical connectors can be delayed by a decrease in frequency and amplitude in addition to an increase in coating thickness. The insertion and withdrawal force gradually decreases due to continuous wear. The failure mechanism of electrical contact during wear is also explained. It provides theoretical guidance for predicting the life of electrical connectors.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115510"},"PeriodicalIF":1.6,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142314599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1016/j.microrel.2024.115508
Wei Chen , Shuo Feng , Xu Liu , Dong Hu , Xu Liu , Xi Zhu , Qi Yao , Xuejun Fan , Guoqi Zhang , Jiajie Fan
Sintered nanocopper (nanoCu) paste, exhibiting excellent electrical, thermal, and mechanical performances, offers promise for interconnections in wide bandgap (WBG) semiconductors operating at higher temperatures. However, sintered nanoCu is prone to severe corrosion in environments containing H2S, with on-site characterization methods for the composition of corrosion products currently lacking. In this study, a novel method was proposed for the rapid characterization of corrosion products during the corrosion process based on hyperspectral imaging (HSI) technology. Sintered nanoCu samples were subjected to 336 h H2S gas corrosion tests with bulk Cu as the reference, followed by correlating the corrosion element content with hyperspectral characteristic parameters. Then, the morphology and composition of corrosion products were researched using focused ion beam scanning electron microscope (FIB-SEM) and transmission electron microscope (TEM) analysis. The results showed that (1) during the corrosion process, a linear relationship was established between the Cu, O elemental atomic contents on the sample surfaces and their hyperspectral characteristic parameters. (2) The elemental atomic content of S exhibited an exponential relationship with the characteristic parameter. (3) The change rate in the spectral characteristic parameters during the corrosion process reflected the severity of corrosion, which was confirmed by comparing the thickness of the corrosion products of the sintered nanoCu and bulk Cu. This study offers a foundation for the further investigation of rapid on-site characterization of sintered nanoCu corrosion involving H2S.
{"title":"Rapid on-site nondestructive surface corrosion characterization of sintered nanocopper paste in power electronics packaging using hyperspectral imaging","authors":"Wei Chen , Shuo Feng , Xu Liu , Dong Hu , Xu Liu , Xi Zhu , Qi Yao , Xuejun Fan , Guoqi Zhang , Jiajie Fan","doi":"10.1016/j.microrel.2024.115508","DOIUrl":"10.1016/j.microrel.2024.115508","url":null,"abstract":"<div><div>Sintered nanocopper (nanoCu) paste, exhibiting excellent electrical, thermal, and mechanical performances, offers promise for interconnections in wide bandgap (WBG) semiconductors operating at higher temperatures. However, sintered nanoCu is prone to severe corrosion in environments containing H<sub>2</sub>S, with on-site characterization methods for the composition of corrosion products currently lacking. In this study, a novel method was proposed for the rapid characterization of corrosion products during the corrosion process based on hyperspectral imaging (HSI) technology. Sintered nanoCu samples were subjected to 336 h H<sub>2</sub>S gas corrosion tests with bulk Cu as the reference, followed by correlating the corrosion element content with hyperspectral characteristic parameters. Then, the morphology and composition of corrosion products were researched using focused ion beam scanning electron microscope (FIB-SEM) and transmission electron microscope (TEM) analysis. The results showed that (1) during the corrosion process, a linear relationship was established between the Cu, O elemental atomic contents on the sample surfaces and their hyperspectral characteristic parameters. (2) The elemental atomic content of S exhibited an exponential relationship with the characteristic parameter. (3) The change rate in the spectral characteristic parameters during the corrosion process reflected the severity of corrosion, which was confirmed by comparing the thickness of the corrosion products of the sintered nanoCu and bulk Cu. This study offers a foundation for the further investigation of rapid on-site characterization of sintered nanoCu corrosion involving H<sub>2</sub>S.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115508"},"PeriodicalIF":1.6,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142314598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-20DOI: 10.1016/j.microrel.2024.115507
Rongxing Cao , Bang Qian , Yuxiong Xue , Jiaen Fang , Yang Liu
High-frequency organic dielectric substrate materials have been widely applied in the fabrication of FCBGA (Flip Chip Ball Grid Array) substrates due to their excellent characteristics of high-speed signal transmission. However, their higher coefficient of thermal expansion (CTE) causes the CTE mismatch between the chip and substrate to increase. High-temperature heating during the reflow soldering process intensifies the thermal mismatch within packaging structure, causing severe warping of the substrate, thereby reducing the yield and subsequent reliability. This study adopted a flatness analyzer and scanning electron microscope (SEM) to characterize the package deformation and micromorphology, and found that the substrate warped after reflow soldering, which caused defects such as chip cracks and micro-bump delamination. A fine finite element simulation model was constructed based on the structure of the experimental sample, and the structure deformation during the soldering process was simulated. An accurate finite element simulation model was constructed based on the structure of the experimental sample to simulate the deformation process of substrate during reflow. Research results show that the constraint of the chip on the substrate during the soldering process is the main factor affecting the thermal deformation mechanism, and the deformation can be suppressed by adding stiffener. This research benefits to the design of FCBGA high-density packaging.
{"title":"Deformation mechanism and optimization of high-density organic substrates during reflow soldering","authors":"Rongxing Cao , Bang Qian , Yuxiong Xue , Jiaen Fang , Yang Liu","doi":"10.1016/j.microrel.2024.115507","DOIUrl":"10.1016/j.microrel.2024.115507","url":null,"abstract":"<div><p>High-frequency organic dielectric substrate materials have been widely applied in the fabrication of FCBGA (Flip Chip Ball Grid Array) substrates due to their excellent characteristics of high-speed signal transmission. However, their higher coefficient of thermal expansion (CTE) causes the CTE mismatch between the chip and substrate to increase. High-temperature heating during the reflow soldering process intensifies the thermal mismatch within packaging structure, causing severe warping of the substrate, thereby reducing the yield and subsequent reliability. This study adopted a flatness analyzer and scanning electron microscope (SEM) to characterize the package deformation and micromorphology, and found that the substrate warped after reflow soldering, which caused defects such as chip cracks and micro-bump delamination. A fine finite element simulation model was constructed based on the structure of the experimental sample, and the structure deformation during the soldering process was simulated. An accurate finite element simulation model was constructed based on the structure of the experimental sample to simulate the deformation process of substrate during reflow. Research results show that the constraint of the chip on the substrate during the soldering process is the main factor affecting the thermal deformation mechanism, and the deformation can be suppressed by adding stiffener. This research benefits to the design of FCBGA high-density packaging.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115507"},"PeriodicalIF":1.6,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142272159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1016/j.microrel.2024.115505
Hui Jin , Xiaoyang Xu , Zhaohao Wang , Siyu Chen , Jing Guo , Bi Wang
With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 , and the power consumption is only 0.82 mw.
{"title":"Novel Latin square matrix code of large burst error correction for MRAM applications","authors":"Hui Jin , Xiaoyang Xu , Zhaohao Wang , Siyu Chen , Jing Guo , Bi Wang","doi":"10.1016/j.microrel.2024.115505","DOIUrl":"10.1016/j.microrel.2024.115505","url":null,"abstract":"<div><p>With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>, and the power consumption is only 0.82 mw.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115505"},"PeriodicalIF":1.6,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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