Microelectronics Reliability最新文献_第8页

Source-connected and gate-connected field-plate influence on thermal resistance of AlGaN/GaN HEMT with varying passivation thickness and field-plate length 不同钝化厚度和场板长度下，源接和栅接场板对AlGaN/GaN HEMT热阻的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-11-04 DOI: 10.1016/j.microrel.2025.115947

Vaidehi Vijay Painter , Raphael Sommet , Jean-Christophe Nallatamby , P. Vigneshwara Raja

A comprehensive investigation into the electrothermal behaviour of AlGaN/GaN high-electron mobility transistor (HEMT) is presented in this work, by means of validated physics-based TCAD simulations. The focus is on the impact of different field-plate (FP) architectures, including source-connected field-plate (SC-FP), gate-connected field-plate (GC-FP), and without FP structures, on the thermal resistance (R_TH) of the HEMT. A key finding is the identification of multiple R_TH regions in the field-plated HEMT, a direct consequence of the primary hotspot dynamically evolving from the gate-edge, to a dual-hotspot configuration, and finally migrating to the FP edge with increasing power levels; in contrast to the single R_TH of the HEMT without FP. This multi-R_TH characteristic is consistent in both SC-FP and GC-FP structures. Moreover, the channel temperature profile is nearly identical in both FPs. The influence of passivation thickness (t_SiN) and field-plate length (L_FP), on R_TH is systematically investigated. The results reveal a critical design trade-off; thicker passivation improves electrical insulation but thermally decouples the FP effect, while thinner t_SiN increases the electric field at the FP edge. The increased L_FP leads to a corresponding reduction in the R_TH. Hence, integrated electrothermal co-design is a fundamental prerequisite for optimizing the performance and reliability of the HEMTs.

本文通过基于物理验证的TCAD模拟，对AlGaN/GaN高电子迁移率晶体管（HEMT）的电热行为进行了全面的研究。重点是不同场板（FP）架构的影响，包括源连接场板（SC-FP），栅极连接场板（GC-FP），以及没有FP结构，对HEMT的热阻（RTH）。一个关键的发现是在场镀HEMT中发现了多个RTH区域，这是主热点从栅极边缘动态演变到双热点配置的直接结果，最后随着功率水平的增加迁移到FP边缘；与不含FP的HEMT的单一RTH相比。这种多rth特征在SC-FP和GC-FP结构中是一致的。此外，两种FPs的通道温度分布几乎相同。系统地研究了钝化厚度（tSiN）和场板长度（LFP）对RTH的影响。结果揭示了一个关键的设计权衡；较厚的钝化改善了电绝缘性，但热去耦了FP效应，而较薄的tSiN增加了FP边缘的电场。LFP的增加导致RTH相应的降低。因此，集成电热协同设计是优化hemt性能和可靠性的基本前提。

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引用次数: 0

Thermal and electrical characterization of flexible microheaters: Influence of material choice and geometry 柔性微加热器的热和电特性：材料选择和几何形状的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-11-04 DOI: 10.1016/j.microrel.2025.115944

Shweta , Sunil Jadav

Microheaters are necessary for a variety of applications, including biomedical implants, wearable sensor systems, and portable electronics that require low-power, quick thermal actuation. This research compares three widely used microheater materials namely silver, copper, and platinum placed on a polyimide (PI) substrate using a thorough electro-thermo-mechanical simulation performed using COMSOL Multiphysics. Thermo-mechanical analysis confirmed that the microheater's structural integrity is maintained since the generated stresses are less than the yield strength of the component materials. The paper also examines the effect of various parameters such as heater width, thickness, voltage, and number of turns on temperature distribution, power dissipation, and resistance. The results of various statistical indicators such as normalized uniformity index and coefficient of variation as well as graph of voltage vs ΔT revealed that platinum provides excellent thermal uniformity as compared to other two materials. The simulation results are validated against analytical calculations, showing good agreement with an average deviation of approximately 7 % across all materials, thereby confirming the accuracy of the modelling approach. With its useful design insights and material-specific trade-offs, this research offers designers creating next-generation flexible heating elements for gas sensors, wearable sensors, and biomedical systems.

微加热器是各种应用所必需的，包括生物医学植入物、可穿戴传感器系统和需要低功耗、快速热致动的便携式电子设备。本研究比较了三种广泛使用的微加热器材料，即放置在聚酰亚胺（PI）衬底上的银、铜和铂，使用COMSOL Multiphysics进行了彻底的电热机械模拟。热力学分析证实，由于产生的应力小于部件材料的屈服强度，因此保持了微加热器的结构完整性。本文还考察了加热器宽度、厚度、电压和匝数等参数对温度分布、功耗和电阻的影响。标准化均匀性指数、变异系数以及电压vs ΔT等统计指标的结果表明，与其他两种材料相比，铂具有优异的热均匀性。通过分析计算验证了模拟结果，所有材料的平均偏差约为7%，从而证实了建模方法的准确性。凭借其有用的设计见解和特定材料的权衡，该研究为设计人员提供了用于气体传感器、可穿戴传感器和生物医学系统的下一代柔性加热元件。

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引用次数: 0

Reliability assessment of graphene channel vertical TFET: Role of trap-assisted tunneling 石墨烯通道垂直TFET的可靠性评估：陷阱辅助隧道的作用

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-31 DOI: 10.1016/j.microrel.2025.115943

Vanshika Ghai , Sidhartha Dash , Guru Prasad Mishra

This paper proposes a graphene channel-based Vertical Tunnel Field Effect Transistor (V-TFET) and analyzes its reliability using Trap-Assisted Tunneling (TAT). The Graphene Channel V-TFET (GC V-TFET) improves device performance because of graphene's two-dimensional honeycomb structure enhancing electron tunneling. Compared to ordinary V-TFETs, this GC V-TFET offers over one decade of improvement in drain current, a two-decade increase in the I_ON/I_OFF ratio, a higher electric field, a lower energy bandgap width, and a one-fold improvement in transconductance. The Silvaco ATLAS TCAD tool compares the simulations of V-TFET and GC V-TFET. To assess reliability, the impact of TAT on the GC V-TFET has been investigated. The results showed an increase of about one decade in the I_OFF value, increase in electric field of approximately 3.0 × 10⁴ V/cm, decrease in potential of about 0.04 V, an upward shift in energy bands of about 0.02 eV, increased transconductance of 1.5 × 10⁻⁶ S, electron concentration at source side is reduced by 4 × 10¹⁶ cm⁻³, hole concentration at channel region decreases by approximately 20 %, electron current density is increased by three and two orders at channel and drain region respectively, hole current density is increased by approximately four orders at source region and decrease in the recombination rate of 4.2 × 10⁴ cm⁻¹ s⁻¹.

本文提出了一种基于石墨烯沟道的垂直隧道场效应晶体管（V-TFET），并利用陷阱辅助隧道（TAT）分析了其可靠性。石墨烯通道V-TFET （GC V-TFET）由于石墨烯的二维蜂窝结构增强了电子隧穿，从而提高了器件性能。与普通的V-TFET相比，这种GC V-TFET提供了超过十年的漏极电流改善，离子/IOFF比增加了二十年，更高的电场，更低的能量带隙宽度，跨导性提高了一倍。Silvaco ATLAS TCAD工具比较了V-TFET和GC V-TFET的模拟结果。为了评估可靠性，研究了TAT对GC V-TFET的影响。结果表明：IOFF值增加约10年，电场增加约3.0 × 104 V/cm，电势下降约0.04 V，能带向上移动约0.02 eV，跨导增加1.5 × 10−6 S，源侧电子浓度降低4 × 1016 cm−3，沟道区空穴浓度降低约20%。通道区和漏极区电子电流密度分别提高了3个和2个数量级，源区空穴电流密度提高了约4个数量级，复合速率为4.2 × 104 cm−1 s−1。

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引用次数: 0

A temperature-invariant and ML-resilient, RO PUF design with improved security and performance metrics 具有温度不变和ml弹性的RO PUF设计，具有更高的安全性和性能指标

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-31 DOI: 10.1016/j.microrel.2025.115941

Nitish Kumar , Aditya Antil , Himanshu Kesarwani , Dhirendra Kumar , Kavindra Kandpal , Manish Goswami

Physically Unclonable Functions (PUFs) represent a modern hardware approach for achieving authentication and secure key generation. The PUF uses the intrinsic, numerous, unpredictable, and unavoidable variances in the semiconductor manufacturing process to enhance hardware and software security. The inherent process variations in semiconductor technology are exploited in PUF circuits to generate unique and unclonable device identifiers. In the proposed design, integrating a Current-Starved (CS) inverter, metastable circuit, and LFSR enhances reliability from 91.06% to 98.96%. The design achieves 49.24% uniqueness, 50.27% uniformity, and 49.87% bit aliasing across a wide temperature range (−40 °C to 120 °C). Power consumption is reduced by about 2.14

\times

compared to a conventional RO PUF. Prelayout and postlayout simulations report delays of 1.11 ns and 2.3 ns, respectively, while NIST tests confirm randomness. FPGA implementation on a Basys-3 Artix-7 using Vivado requires minimal hardware and achieves an 80 Mb/s bit generation rate. Furthermore, the design resists ML-based modeling attacks, limiting prediction accuracy to 45%–65%.

物理不可克隆函数（puf）代表了实现身份验证和安全密钥生成的现代硬件方法。PUF利用半导体制造过程中固有的、大量的、不可预测的和不可避免的差异来增强硬件和软件的安全性。在PUF电路中利用半导体技术中固有的工艺变化来产生唯一的和不可克隆的设备标识符。在提出的设计中，集成电流耗尽（CS）逆变器、亚稳电路和LFSR将可靠性从91.06%提高到98.96%。该设计在宽温度范围（- 40°C至120°C）内实现了49.24%的唯一性、50.27%的均匀性和49.87%的位混叠。与传统的RO PUF相比，功耗降低了约2.14倍。布局前和布局后的模拟分别报告了1.11 ns和2.3 ns的延迟，而NIST测试证实了随机性。使用Vivado的Basys-3 Artix-7上的FPGA实现需要最少的硬件，并实现80 Mb/s的比特生成速率。此外，该设计抵抗基于ml的建模攻击，将预测精度限制在45%-65%。

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引用次数: 0

Thermomechanical stress optimization in flip-chip packages: Impacts of copper pillar geometry on ultra-low-k layer reliability 倒装封装中的热机械应力优化：铜柱几何形状对超低k层可靠性的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-30 DOI: 10.1016/j.microrel.2025.115940

Danting Li , Kai Zhao , Ruiwang Yu , Hao Wei , Yudi Zhao , Shuying Ma

Thermo-mechanical stress at ultra-low-k (ULK) dielectric interfaces has emerged as a critical challenge for flip-chip package reliability, stemming from the inherent brittleness of ULK materials, significant coefficient of thermal expansion (CTE) mismatch in chip-package systems, and the high modulus of copper interconnects. This study develops a multiscale finite element analysis framework that integrates global-submodel coupling methodology with temperature-dependent material properties to systematically investigate stress evolution during 25-260-25 °C reflow processes. Simulation results demonstrate that geometric optimization of copper pillar bumps can effectively reduce interfacial stresses across the solder/Ni/ULK multilayer interfaces while establishing design guidelines, including adopting passivation-covered PI openings, decreasing the PI opening-to-pillar diameter ratio for ULK interfacial stress redistribution, and reducing bump height while increasing PI thickness to ensure effective stress buffering. This research breaks through the limitations of traditional single-parameter optimization approaches, providing critical design insights for minimizing chip-package interfacial fracture failures.

由于ULK材料固有的脆性、芯片封装系统中显著的热膨胀系数（CTE）失配以及铜互连的高模量，超低k （ULK）介电界面上的热机械应力已成为倒装封装可靠性的关键挑战。本研究开发了一个多尺度有限元分析框架，将全局子模型耦合方法与温度相关的材料特性集成在一起，系统地研究了25-260-25°C回流过程中的应力演化。仿真结果表明，铜柱凸点的几何优化可以有效降低焊料/Ni/ULK多层界面上的界面应力，同时建立设计准则，包括采用钝化覆盖的PI开口，减小PI开口与ULK界面应力重分布的柱径比，降低凸点高度同时增加PI厚度以确保有效的应力缓冲。该研究突破了传统单参数优化方法的局限性，为最大限度地减少芯片封装界面断裂故障提供了关键的设计见解。

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引用次数: 0

Yet another reliability assessment method for RRAM-based dot-product engine 另一种基于随机存储器的点积引擎可靠性评估方法

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-24 DOI: 10.1016/j.microrel.2025.115938

Ahmed Mahmoudi , Alessandro Veronesi , Philipp Grothe , Jianan Wen , Rolf Meyer , Markus Ulbricht , Rainer Buchty , Mladen Berekovic , Saleh Mulhem

Resistive random-access memory (RRAM) has been deployed to realize different hardware components, notably dot-product engines that accelerate neural network execution. Several designs of RRAM dot-product engines (RDPEs) have been proposed in the last decade. While generally a promising technology, RRAM devices suffer from various performance-affecting reliability issues. The stuck-at faults (SAFs) in RRAM devices significantly degrade the accuracy of the neural networks running on the RDPE. Therefore, the effect of these faults on applications needs to be assessed. Consequently, this paper introduces a new concept for evaluating the impact of unreliable RRAM behavior due to the most notable SAF phenomenon on executable software. For this, we propose a novel reliability concept called Execution-Guided Reliability (EGR). This EGR model is formulated mathematically based on the reliability block diagram method and later applied to evaluate RDPE reliability. Subsequently, we integrate EGR into a framework with multiple RDPEs to perform several experiments and show numerical results. We then explore and analyze the correlation between the EGR model and the computation error magnitudes of RDPEs to explain the behavior of SAFs in the RRAM devices. The results show that the correlation ranging from

− 0.988

to

− 0.999

indicates, with high confidence, a decreasing monotonic trend between EGR values and error magnitudes.

电阻式随机存取存储器（RRAM）已被用于实现不同的硬件组件，特别是加速神经网络执行的点积引擎。在过去的十年中，已经提出了几种RRAM点积引擎的设计。虽然RRAM设备通常是一种很有前途的技术，但它存在各种影响性能的可靠性问题。RRAM设备中的卡在故障严重降低了神经网络在RDPE上运行的精度。因此，需要评估这些故障对应用程序的影响。因此，本文引入了一个新的概念来评估由于最显著的SAF现象而导致的不可靠RRAM行为对可执行软件的影响。为此，我们提出了一种新的可靠性概念——执行导向可靠性（EGR）。基于可靠性方框图法建立了EGR模型，并将其应用于RDPE可靠性评估。随后，我们将EGR集成到一个具有多个rdpe的框架中，进行了多次实验并给出了数值结果。然后，我们探索和分析了EGR模型与rpe计算误差大小之间的相关性，以解释RRAM器件中SAFs的行为。结果表明，相关系数在- 0.988 ~ - 0.999范围内表明，EGR值与误差值呈单调递减趋势，置信度较高。

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引用次数: 0

Gas breakdown characteristic and ablation defect formation mechanism of micro-scale gap in MEMS MEMS微尺度间隙气体击穿特性及烧蚀缺陷形成机理

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-23 DOI: 10.1016/j.microrel.2025.115936

Jiaqi Zheng , Renzhi Hu , Jie Yang , Guofen Xie , Xuhui Gong , Chunlin Liu , Baolin Zhao

Gas breakdown at the microscale dimension has become one of the critical challenges one of urgent challenges along with the miniaturization and high-performance development of MEMS (Micro-Electro-Mechanical Systems) devices. However, comprehensive theoretical frameworks for micro-scale gas discharge characteristic and damage mechanisms in MEMS devices remains to be developed. In the article, the gas discharge behaviors of silicon-based MEMS devices with 1.5 μm gap were investigated, whose I-V characteristics during the initial breakdown process under DC voltage and the subsequent breakdown behavior upon reapplication of voltage were characterized in detail. A theoretical investigation incorporating field emission theory was performed to examine the twice breakdown phenomena, elucidating the critical factors and underlying mechanisms of micro-gap gas discharge. Incorporating ablation defect morphology, compositional analysis, and finite element simulation, the formation process of ablation defects on silicon electrodes was investigated, revealing the breakdown characteristics of MEMS devices with micro-gaps.

随着微机电系统（MEMS）器件的小型化和高性能发展，微尺度气体击穿已成为关键挑战之一。然而，关于MEMS器件微尺度气体放电特性和损伤机理的全面理论框架仍有待发展。本文研究了具有1.5 μm隙隙的硅基MEMS器件的气体放电行为，详细表征了其在直流电压下初始击穿过程中的I-V特性以及随后在重新施加电压时的击穿行为。结合场发射理论对微间隙气体放电的二次击穿现象进行了理论分析，阐明了微间隙气体放电的关键因素和机理。结合烧蚀缺陷形貌、成分分析和有限元模拟，研究了硅电极上烧蚀缺陷的形成过程，揭示了微间隙MEMS器件的击穿特性。

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引用次数: 0

Low-cycle fatigue of printed sintered silver in extreme environments: Mechanical shock at multiple temperatures 印刷烧结银在极端环境下的低周疲劳：多重温度下的机械冲击

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-23 DOI: 10.1016/j.microrel.2025.115932

Hayden Richards , Abhijit Dasgupta , Andres Bujanda , Harvey Tsang , Matthew Bowman

This study considers the response of printed hybrid electronic (PHE) assemblies to extreme mechanical shock (50,000 g base excitation) at multiple elevated temperatures (25–125 °C). Passive components were recessed into milled cavities in injection-molded polysulfone beams using a unique ‘mill-and-fill’ method. The components were interconnected to printed silver traces using printed solder, with circuits then formed from the silver traces. The populated beam specimens were subjected to drop testing in a clamped-clamped configuration without secondary impact using an accelerated-fall drop tower with dual mass shock amplifier (DMSA), resulting in strain magnitudes in the polysulfone substrate of ∼30,000 μm/m at rates up to ∼200 /s. A finite element model of the fully populated assembly was used to estimate plastic strain history at the failure site in the sintered silver.

Circuit failure occurred due to component separation from the substrate caused by cracking within the sintered silver beneath the soldered interconnect – a failure mode common across all temperatures. Maximum plastic strain magnitudes in the sintered silver were ∼ 0.11 m/m at rates of ∼1000 /s. Total number of drops to failure was recorded in four different component locations at all temperatures. These results, together with transient nonlinear finite element simulation data, were then integrated by means of a cumulative damage model, to generate a low-cycle fatigue curve for sintered silver from 25 to 125 °C.

本研究考虑了印刷混合电子（PHE）组件在多个高温（25-125°C）下对极端机械冲击（50,000 g基激励）的响应。采用独特的“铣削-填充”方法，将被动元件嵌入注塑成型聚砜梁的铣削腔中。这些元件使用印刷焊料连接到印刷银线，然后由银线形成电路。填充梁试件在没有二次冲击的夹紧配置下进行跌落测试，使用带有双质量冲击放大器（DMSA）的加速跌落塔，在聚砜衬底中产生约30,000 μm/m的应变，速率高达约200 /s。利用满填充体的有限元模型估计了烧结银在破坏部位的塑性应变历史。电路故障发生的原因是由于元件与衬底分离，这是由于焊接互连下面烧结银的开裂造成的，这种故障模式在所有温度下都很常见。烧结银的最大塑性应变为~ 0.11 m/m，速率为~ 1000 /s。在所有温度下，在四个不同的组件位置记录到故障的总滴数。这些结果与瞬态非线性有限元模拟数据一起，通过累积损伤模型进行整合，生成烧结银在25 - 125°C范围内的低周疲劳曲线。

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引用次数: 0

A novel triple-node upset tolerance and lower-power hardened latch circuit for aerospace applications 一种用于航空航天应用的新型三节点扰动公差和低功耗硬化锁存电路

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-22 DOI: 10.1016/j.microrel.2025.115939

Xiuying Wang , Qingyi Liu , Duowen Sun , Mingkun Xu , Qiang Zhao

At present, the anti-radiation hardening of latches in integrated circuits often requires large hardware overhead in order to achieve multi-node upset recovery, which also affects the working performance of the circuits. To overcome this design limitation, this paper proposes a low-power polarity-hardened design latch (LPDL) that tolerates triple-node upset (TNU) with a low power-delay-area product (PDAP). Based on NMOS polarity-hardened technology and transistor-stacked technology, the LPDL not only reduces the number of sensitive nodes, but also significantly lowers power consumption. Compared with other latches, for example, CLCT, FERST, TP-DICE, RH, RHPDL, FPADRL, DURMC, LCTNUT and LCTNUCR, the average optimization degrees of the LPDL for power consumption, and PDAP are 58.04%, and 63.39%, respectively. Additionally, the critical charge (

Q_{c r i t}

) exceeds 150 fC. The standard deviations under different process, voltage, and temperature and Monte Carlo simulations indicate that the LPDL is not only less sensitive to variations in the environment but also tolerates upsets, even under extreme process conditions.

目前，集成电路中锁存器的抗辐射硬化往往需要较大的硬件开销才能实现多节点扰动恢复，这也影响了电路的工作性能。为了克服这一设计限制，本文提出了一种低功耗极性硬化设计锁存器（LPDL），该锁存器具有低功耗延迟面积积（PDAP），可以承受三节点干扰（TNU）。基于NMOS极性硬化技术和晶体管堆叠技术，LPDL不仅减少了敏感节点的数量，而且显著降低了功耗。与CLCT、FERST、TP-DICE、RH、RHPDL、FPADRL、DURMC、LCTNUT、LCTNUCR等锁存器相比，LPDL对功耗的平均优化度为58.04%，PDAP的平均优化度为63.39%。此外，临界电荷（Qcrit）超过150 fC。在不同工艺、电压、温度和蒙特卡罗模拟下的标准差表明，LPDL不仅对环境变化不太敏感，而且即使在极端工艺条件下也能承受扰动。

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引用次数: 0

The effect of halogen ion on the process of electrochemical migration of resistor 卤素离子对电阻器电化学迁移过程的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-21 DOI: 10.1016/j.microrel.2025.115937

Yao Tan , Zixue Jiang , Hao Zhang , Xianqin Zhuo , Junsheng Wu , Luntao Wang , Kui Xiao

A water droplet experiment was used to determine the threshold for electrochemical migration of the resistor in halogen contaminants. The risk of electrochemical migration increases with increasing pollutant concentrations, with NaCl being the most significant. At a Cl- concentration of 10 ppm, no dendrites formation; When Cl- concentrations are between 100 and 700 ppm, dendritic growth. When the electrolyte concentration is low, the formation of intact dendrites leads to a prolonged surge of current; With the increase of concentration, the number of nucleation sites and dendrites increases, However, the strong hydrogen evolution reaction makes it difficult to produce intact dendrites.

用水滴实验确定了电阻器在卤素污染物中电化学迁移的阈值。电化学迁移风险随着污染物浓度的增加而增加，以NaCl浓度的增加最为显著。在Cl-浓度为10ppm时，不形成枝晶；当Cl浓度在100 - 700ppm之间时，枝晶生长。当电解质浓度较低时，完整树突的形成导致电流的浪涌延长；随着浓度的增加，成核位点和枝晶的数量增加，但析氢反应强烈，难以生成完整的枝晶。

引用次数: 0