Pub Date : 2022-09-15DOI: 10.1109/JXCDC.2022.3206778
Zongxian Yang;Kangqiang Pan;Norman Y. Zhou;Lan Wei
In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.
{"title":"Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays","authors":"Zongxian Yang;Kangqiang Pan;Norman Y. Zhou;Lan Wei","doi":"10.1109/JXCDC.2022.3206778","DOIUrl":"10.1109/JXCDC.2022.3206778","url":null,"abstract":"In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"84-92"},"PeriodicalIF":2.4,"publicationDate":"2022-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09893161.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46809461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-15DOI: 10.1109/JXCDC.2022.3206879
Rui Xiao;Wenyu Jiang;Piew Yoong Chee
The growing data volume and complexity of deep neural networks (DNNs) require new architectures to surpass the limitation of the von-Neumann bottleneck, with computing-in-memory (CIM) as a promising direction for implementing energy-efficient neural networks. However, CIM’s peripheral sensing circuits are usually power- and area-hungry components. We propose a time-multiplexing CIM architecture (TM-CIM) based on memristive analog computing to share the peripheral circuits and process one column at a time. The memristor array is arranged in a column-wise manner that avoids wasting power/energy on unselected columns. In addition, digital-to-analog converter (DAC) power and energy efficiency, which turns out to be an even greater overhead than analog-to-digital converter (ADC), can be fine-tuned in TM-CIM for significant improvement. For a 256*256 crossbar array with a typical setting, TM-CIM saves $18.4times $ in energy with 0.136 pJ/MAC efficiency, and $19.9times $ area for 1T1R case and $15.9times $ for 2T2R case. Performance estimation on VGG-16 indicates that TM-CIM can save over $16times $ area. A tradeoff between the chip area, peak power, and latency is also presented, with a proposed scheme to further reduce the latency on VGG-16, without significantly increasing chip area and peak power.
{"title":"An Energy Efficient Time-Multiplexing Computing-in-Memory Architecture for Edge Intelligence","authors":"Rui Xiao;Wenyu Jiang;Piew Yoong Chee","doi":"10.1109/JXCDC.2022.3206879","DOIUrl":"10.1109/JXCDC.2022.3206879","url":null,"abstract":"The growing data volume and complexity of deep neural networks (DNNs) require new architectures to surpass the limitation of the von-Neumann bottleneck, with computing-in-memory (CIM) as a promising direction for implementing energy-efficient neural networks. However, CIM’s peripheral sensing circuits are usually power- and area-hungry components. We propose a time-multiplexing CIM architecture (TM-CIM) based on memristive analog computing to share the peripheral circuits and process one column at a time. The memristor array is arranged in a column-wise manner that avoids wasting power/energy on unselected columns. In addition, digital-to-analog converter (DAC) power and energy efficiency, which turns out to be an even greater overhead than analog-to-digital converter (ADC), can be fine-tuned in TM-CIM for significant improvement. For a 256*256 crossbar array with a typical setting, TM-CIM saves \u0000<inline-formula> <tex-math>$18.4times $ </tex-math></inline-formula>\u0000 in energy with 0.136 pJ/MAC efficiency, and \u0000<inline-formula> <tex-math>$19.9times $ </tex-math></inline-formula>\u0000 area for 1T1R case and \u0000<inline-formula> <tex-math>$15.9times $ </tex-math></inline-formula>\u0000 for 2T2R case. Performance estimation on VGG-16 indicates that TM-CIM can save over \u0000<inline-formula> <tex-math>$16times $ </tex-math></inline-formula>\u0000 area. A tradeoff between the chip area, peak power, and latency is also presented, with a proposed scheme to further reduce the latency on VGG-16, without significantly increasing chip area and peak power.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"111-118"},"PeriodicalIF":2.4,"publicationDate":"2022-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09893208.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44009321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-30DOI: 10.1109/JXCDC.2022.3202517
Yongmo Park;Ziyu Wang;Sangmin Yoo;Wei D. Lu
As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.
{"title":"RM-NTT: An RRAM-Based Compute-in-Memory Number Theoretic Transform Accelerator","authors":"Yongmo Park;Ziyu Wang;Sangmin Yoo;Wei D. Lu","doi":"10.1109/JXCDC.2022.3202517","DOIUrl":"10.1109/JXCDC.2022.3202517","url":null,"abstract":"As more cloud computing resources are used for machine learning training and inference processes, privacy-preserving techniques that protect data from revealing at the cloud platforms attract increasing interest. Homomorphic encryption (HE) is one of the most promising techniques that enable privacy-preserving machine learning because HE allows data to be evaluated under encrypted forms. However, deep neural network (DNN) implementations using HE are orders of magnitude slower than plaintext implementations. The use of very long polynomials and associated number theoretic transform (NTT) operations for polynomial multiplications is the main bottlenecks of HE implementation for practical uses. This article introduces RRAM number theoretic transform (RM-NTT): a resistive random access memory (RRAM)-based compute-in-memory (CIM) system to accelerate NTT and inverse NTT (INTT) operations. Instead of running fast Fourier transform (FFT)-like algorithms, RM-NTT uses a vector-matrix multiplication (VMM) approach to achieve maximal parallelism during NTT and INTT operations. To improve the efficiency, RM-NTT stores modified forms of the twiddle factors in the RRAM arrays to process NTT/INTT in the same RRAM array and employs a Montgomery reduction algorithm to convert the VMM results. The proposed optimization methods allow RM-NTT to significantly reduce NTT operation latency compared with other NTT accelerators, including both CIM and non-CIM-based designs. The effects of different RM-NTT design parameters and device nonidealities are also discussed.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"93-101"},"PeriodicalIF":2.4,"publicationDate":"2022-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09870678.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44468639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-09DOI: 10.1109/JXCDC.2022.3181925
Siri Narla;Piyush Kumar;Ann Franchesca Laguna;Dayane Reis;X. Sharon Hu;Michael Niemier;Azad Naeemi
This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with $1.35times $ and $14.4times $ improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below $10^{-4}$ while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a $2times $ energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.
{"title":"Modeling and Design for Magnetoelectric Ternary Content Addressable Memory (TCAM)","authors":"Siri Narla;Piyush Kumar;Ann Franchesca Laguna;Dayane Reis;X. Sharon Hu;Michael Niemier;Azad Naeemi","doi":"10.1109/JXCDC.2022.3181925","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3181925","url":null,"abstract":"This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with \u0000<inline-formula> <tex-math>$1.35times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$14.4times $ </tex-math></inline-formula>\u0000 improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below \u0000<inline-formula> <tex-math>$10^{-4}$ </tex-math></inline-formula>\u0000 while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"44-52"},"PeriodicalIF":2.4,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09792464.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49963534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3202180
Michael Balinskiy;Alexander Khitun
Yttrium iron garnet Y3Fe2(FeO4)3 (YIG) has a uniquely low magnetic damping for spin waves, which makes it a perfect material for magnonic devices. Spin waves typically exist in the microwave frequency range, and their wavelength can be decreased to the nanoscale. Their dispersion in YIG waveguides depends on the strength and orientation of the bias magnetic field. It may be possible to exploit YIG waveguides as field-controlled filters and delay lines. In this work, we describe combinatorial logic and memory devices to benefit YIG properties. An act of computation in the combinatorial device is associated with finding a route connecting the input and output ports. We present experimental data demonstrating the pathfinding in the active ring circuit with YIG waveguide. The ability to search in parallel through multiple paths is the most appealing property of combinatorial devices. Potentially, they may compete with quantum computers in functional throughput.
{"title":"Yttrium Iron Garnet-Based Combinatorial Logic and Memory Devices","authors":"Michael Balinskiy;Alexander Khitun","doi":"10.1109/JXCDC.2022.3202180","DOIUrl":"10.1109/JXCDC.2022.3202180","url":null,"abstract":"Yttrium iron garnet Y3Fe2(FeO4)3 (YIG) has a uniquely low magnetic damping for spin waves, which makes it a perfect material for magnonic devices. Spin waves typically exist in the microwave frequency range, and their wavelength can be decreased to the nanoscale. Their dispersion in YIG waveguides depends on the strength and orientation of the bias magnetic field. It may be possible to exploit YIG waveguides as field-controlled filters and delay lines. In this work, we describe combinatorial logic and memory devices to benefit YIG properties. An act of computation in the combinatorial device is associated with finding a route connecting the input and output ports. We present experimental data demonstrating the pathfinding in the active ring circuit with YIG waveguide. The ability to search in parallel through multiple paths is the most appealing property of combinatorial devices. Potentially, they may compete with quantum computers in functional throughput.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"53-58"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09868767.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42869408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3204198
Azad Naeemi
Welcome to the seventh volume, second semiannual issue of the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), a multidisciplinary, open access IEEE journal that is focused on publishing seminal research in the exploration for energy-efficient computing based on physics and materials to enable new devices, circuits, and architecture that will be of great interest to integrated circuit researchers and those working in the information technology (IT) industry. The articles in the journal are selectively chosen to provide insight into the architectural, circuit, and device implications of emerging quantum nanoelectronic and nanomagnetic device technologies. Discovery of new materials, devices, and circuits for energy-efficient computational circuits will be needed to enable Moore’s law to continue for computing beyond the end of the roadmap for CMOS technologies, with significant improvement in energy efficiency and cost per function.
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits—Vol. 8, No. 1","authors":"Azad Naeemi","doi":"10.1109/JXCDC.2022.3204198","DOIUrl":"10.1109/JXCDC.2022.3204198","url":null,"abstract":"Welcome to the seventh volume, second semiannual issue of the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), a multidisciplinary, open access IEEE journal that is focused on publishing seminal research in the exploration for energy-efficient computing based on physics and materials to enable new devices, circuits, and architecture that will be of great interest to integrated circuit researchers and those working in the information technology (IT) industry. The articles in the journal are selectively chosen to provide insight into the architectural, circuit, and device implications of emerging quantum nanoelectronic and nanomagnetic device technologies. Discovery of new materials, devices, and circuits for energy-efficient computational circuits will be needed to enable Moore’s law to continue for computing beyond the end of the roadmap for CMOS technologies, with significant improvement in energy efficiency and cost per function.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"ii-iii"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09903016.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44882687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3207087
Dmitri E. Nikonov
As is well known, the traditional electronics as well as exploratory logic and memory devices have relied on mono- or bi-elemental semiconductors for many decades. Oxides served an indispensable, but still secondary role of capacitor dielectrics, insulation, tunneling barriers, and so on. The functionality of oxides putting them at the center stage of computing (such as conduction, ferroelectricity, magnetic/spin, piezoelectric, ion drift, metal–insulator transitions, etc.) was researched from the material science side throughout this time. However, the work on realistic computing devices based on these properties really took off in the past decade. Oxides allow for a wider variety of phenomena which can be utilized (multiferroic materials, spin waves, to name a few). They require more sophisticated theoretical treatment (such as indirect exchange, Dzyaloshinskii–Moriya interaction, and topological materials) than traditional semi-conductors. In some cases, the single crystal state and close to atomically flat interfaces require novel fabrication methods. All these provide exciting opportunities to advance computing.
{"title":"Guest Editorial Special Topic on Oxide Electronics for Beyond CMOS Logic and Memory","authors":"Dmitri E. Nikonov","doi":"10.1109/JXCDC.2022.3207087","DOIUrl":"10.1109/JXCDC.2022.3207087","url":null,"abstract":"As is well known, the traditional electronics as well as exploratory logic and memory devices have relied on mono- or bi-elemental semiconductors for many decades. Oxides served an indispensable, but still secondary role of capacitor dielectrics, insulation, tunneling barriers, and so on. The functionality of oxides putting them at the center stage of computing (such as conduction, ferroelectricity, magnetic/spin, piezoelectric, ion drift, metal–insulator transitions, etc.) was researched from the material science side throughout this time. However, the work on realistic computing devices based on these properties really took off in the past decade. Oxides allow for a wider variety of phenomena which can be utilized (multiferroic materials, spin waves, to name a few). They require more sophisticated theoretical treatment (such as indirect exchange, Dzyaloshinskii–Moriya interaction, and topological materials) than traditional semi-conductors. In some cases, the single crystal state and close to atomically flat interfaces require novel fabrication methods. All these provide exciting opportunities to advance computing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"ii-iii"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09906568.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43591151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143391
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本刊的编辑委员会、理事会、现任工作人员、委员会成员和/或社团编辑。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2022.3143391","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3143391","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09916563.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49962921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143399
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本刊的编辑委员会、理事会、现任工作人员、委员会成员和/或社团编辑。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2022.3143399","DOIUrl":"10.1109/JXCDC.2022.3143399","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09916566.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43858938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3181925
Siri Narla, Piyush Kumar, Ann Franchesca Laguna, D. Reis, X. S. Hu, M. Niemier, A. Naeemi
This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with $1.35times $ and $14.4times $ improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below $10^{-4}$ while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a $2times $ energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.
{"title":"Modeling and Design for Magnetoelectric Ternary Content Addressable Memory (TCAM)","authors":"Siri Narla, Piyush Kumar, Ann Franchesca Laguna, D. Reis, X. S. Hu, M. Niemier, A. Naeemi","doi":"10.1109/JXCDC.2022.3181925","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3181925","url":null,"abstract":"This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with <inline-formula> <tex-math notation=\"LaTeX\">$1.35times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$14.4times $ </tex-math></inline-formula> improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below <inline-formula> <tex-math notation=\"LaTeX\">$10^{-4}$ </tex-math></inline-formula> while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a <inline-formula> <tex-math notation=\"LaTeX\">$2times $ </tex-math></inline-formula> energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"44-52"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62234230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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