Integration-The Vlsi Journal最新文献

The single-objective and single-parameter optimization method is commonly used in the structure optimization of TSV to improve the transmission characteristics, for which a structure design scheme that simultaneously satisfies multiple target requirements is difficult to obtain. Moreover, the method cannot simultaneously optimize different design parameters. Aiming at the above problems, a global optimization method based on the grey wolf optimization (GWO) algorithm and artificial neural network (ANN) model is proposed. With the presented mixed dielectric coaxial-annular TSV model, firstly six key design parameters A-F are selected as optimization variables by the control variable method. The L₂₅(5⁶) orthogonal experiment is designed for Taguchi analysis and analysis of variance (ANOVA). Then, three prediction models, ANN, support vector machine (SVM), and extreme learning machine (ELM), are developed with the extended orthogonal data as the training sets. It is found that the ANN model performed best. To search for the global optimal solution, the genetic algorithm (GA) and GWO algorithm, combined with the ANN model are applied, respectively. The results show that the GWO algorithm is more successful in solving the problem of falling into the local optimum than GA, and the convergence speed is faster and more stable. After GWO-ANN optimization, the performance of each S-parameter index is greatly improved, S₁₁ reduces by 14.05 dB, S₂₁ increases by 0.33 dB, and S₃₁ reduces by 12.50 dB at 30 GHz.

A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.

Computer-based machine learning algorithms that produce impressive performance results are computationally demanding and thus subject to high energy consumption during training and testing. Therefore, compact neuro-inspired devices are required to achieve efficiency in hardware resource consumption for the smooth implementation of neural network applications that require low energy and area. In this paper, learning characteristics and performances of the nanoscale titanium dioxide (${\mathrm{TiO}}_2$) based synaptic device have been analyzed by implementing it in the hardware-based neural network for digit classification. Our model is experimentally validated by using 32-nm CMOS technology and the results demonstrate that the model provides high computational ability with better accuracy and efficiency in resource consumption with low energy and less area. The proposed model exhibits 20% energy gain and 16.82% accuracy improvement and 18% less total latency compared to the state-of-the-art $\mathrm{Ag}$:$\mathrm{Si}$ synaptic device-based neural network. Furthermore, when compared to the software-based (i.e., computer-based) implementation of neural networks, our ${\mathrm{TiO}}_2$-based model not only achieved an impressive accuracy rate of 90.01% on the MNIST dataset but also did so with reduced energy consumption. Consequently, our model, characterized by a low hardware implementation cost, emerges as a promising neuro-inspired hardware solution for various neural network applications. The proposed model has further demonstrated outstanding performance in experiments involving both the MNIST and Fisher’s Iris datasets. On the latter dataset, the model exhibited notable precision (94.5%), recall (91.5%), and an impressive F1-score (92.9%), accompanied by a commendable accuracy rate of 93.04%.

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130^◦C and T = 25^◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.

Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130^◦C) compared to lower operating temperatures (T = 25^◦C).

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level $V_C$, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using $0.18\mu m$ SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.

To address the limitations of existing chaotic maps, we proposed a non-degenerate n-dimensional (n ≥ 2) integer domain chaotic map (nD-IDCM) model that can construct any non-degenerate n-dimensional integer domain chaotic maps. Moreover, we analyzed its chaotic behavior through Lyapunov exponent, and found that the nD-IDCM generates chaotic sequences in the integer domain, which effectively resolves the issue of finite precision effect when implementing existing chaotic maps on computers or digital devices. To verify the effectiveness of nD-IDCM, we presented two instances to demonstrate how the positive Lyapunov exponents can be regulated by manipulating the parameter matrix. Subsequently, we have scrutinized their dynamical behavior using Kolmogorov entropy, sample entropy, correlation dimension and randomness testing via TestU01. Finally, to assess the feasibility of nD-IDCM, we devised a keyed pseudo random number generator (PRNG) based on a 3D-IDCM that can ensure superior randomness and unpredictability. Experimental results indicated that integer domain chaotic maps constructed using nD-IDCM have desirable Lyapunov exponents and exhibit ergodicity within a sufficient larger chaotic range.

CMOS devices are increasingly affected by triple-node-upset as transistor characteristics reduce, particularly in radiation environments. For the shortcomings of the existing radiation hardened designs, including high overhead and high delay, this paper proposes a novel low cost triple-node-upset self-recoverable latch. Simulation results show that compared with the existing triple-node-upset hardened designs, the proposed latch has reduced power consumption, delay, and power-delay product by 34.57 %, 6.42 %, and 34.98 %, respectively.

An ensemble data-learning approach based on proper orthogonal decomposition (POD) and Galerkin projection (EnPOD-GP) is proposed for thermal simulations of multi-core CPUs to improve training efficiency and the model accuracy for a previously developed global POD-GP method (GPOD-GP). GPOD-GP generates one set of basis functions (or POD modes) to account for thermal behavior in response to variations in dynamic power maps (PMs) in the entire chip, which is computationally intensive to cover possible variations of all power sources. EnPOD-GP however acquires multiple sets of POD modes to significantly improve training efficiency and effectiveness, and its simulation accuracy is independent of any dynamic PM. Compared to finite element simulation, both GPOD-GP and EnPOD-GP offer a computational speedup over 3 orders of magnitude. For a processor with a small number of cores, GPOD-GP provides a more efficient approach. When high accuracy is desired and/or a processor with more cores is involved, EnPOD-GP is more preferable in terms of training effort and simulation accuracy and efficiency. Additionally, the error resulting from EnPOD-GP can be precisely predicted for any random spatiotemporal power excitation.

In this paper a new encryption system has been designed and implemented for real-time speech transmission to reduce bandwidth requirements, increase security and minimize residual intelligibility. To guarantee robustness and lightweight computation, the developed cryptosystem has been carried out in the wavelet transform domain based on a hyperchaotic model to generate mask and permutation keys. The cryptographic system has been designed using a hardware-software (HW/SW) co-design approach by developing several IP-cores in a relatively short development time. The performances and security evaluation of the system have been validated through simulation results followed by an experimental validation through the implementation of an encrypted speech signal transmission between two low cost Nexys-4 DDR FPGA platforms, operating in real-time for both wired and wireless communications. Compared to similar works, high performances have been obtained in terms of bandwidth efficiency due to the use of DWT, limited area of FPGA resources, low power consumption and high security level with a large keyspace that is sufficient to resist against brute force attacks. The designed system can be a very useful solution for many real-time secure integrated voice communication systems, multiple communication purposes, military, professional or personal high level of conversations security.

With the increasing application of IoT devices, the memory subsystem, as the performance and energy bottleneck of IoT systems, has received a lot of attention. One of the keys is on-chip memory which can bridge the performance gap between the CPU and main memory. While many off-the-shelf embedded processors utilize the hybrid on-chip memory architecture containing scratchpad memories (SPMs) and caches, most existing literature ignores the collaboration between caches and SPMs. This paper proposes static SPM allocation strategies for the architecture mentioned above in IoT systems, which try to minimize the overall instruction memory subsystem latency and/or energy consumption. We capture the intra- and inter-task cache conflict misses via a fine-grained temporal cache behavior model. Based on this cache conflict information, we propose an integer linear programming (ILP) algorithm to generate an optimal static function level SPM allocation for system performance. Furthermore, to improve the scalability of the proposed allocation scheme for an enormous task set, we offer the interference factor to calculate the interference impact quantitatively. Then, based on the interference factor, we present two approximate knapsack based heuristic algorithms to provide near optimal static allocation schemes at both function- and basic block-level granularities, which favors fast design space exploration. The experiment results demonstrate that the proposed solution achieves a 30.85% improvement in memory performance, and up to 31.39% reduction in energy consumption, compared to the existing SPM allocation scheme at the function level. In addition, the proposed basic block level allocation algorithm shows better performance than our function level allocation algorithm and other basic block level allocation algorithm.