Integration-The Vlsi Journal最新文献_第9页

Low-cost compression architecture based on extended DCT algorithm 基于扩展DCT算法的低成本压缩体系结构

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-04 DOI: 10.1016/j.vlsi.2025.102568

Nedra Jarray , Majdi Elhajji , Abdelkrim Zitouni

This paper introduces a low-power, hardware-efficient 2D-DCT architecture aimed at image and video encoding. The architecture implements an optimized Cordic-Loeffler algorithm, which reduces area cost, power consumption, and accelerates the encoding process. The improvement in the Cordic algorithm is achieved by reducing the large number of iteration sequences. Furthermore, the proposed design integrates the Modified Carry Look-Ahead Adder (MCLA) and the Carry Save Adder (CSA) to minimize arithmetic operations and memory requirements. Experimental results demonstrate that the proposed architecture achieves an efficient average peak signal-to-noise ratio (PSNR), especially for endoscopy image compression, along with a reduction in addition/shift operations compared to other competitive Cordic-DCT algorithms.

The proposed architecture was implemented using Xilinx ISE 13.1 for the Virtex5-FPGA, with an operating frequency of 254.6 MHz and a power consumption of 39 mW at 100 MHz. These results surpass the performance of most previous architectures for Virtex-4/Virtex-5 FPGA implementations. According to performance estimations for ASIC implementation using TSMC 130 nm technology, the proposed design dissipates approximately 4.68 mW at 100 MHz, which is notably lower than that of previous works. Thus, the proposed 2D-DCT architecture is particularly suitable for low-power, high-quality codecs, making it ideal for battery-powered embedded systems.

本文介绍了一种针对图像和视频编码的低功耗、硬件高效的2D-DCT架构。该架构实现了一种优化的Cordic-Loeffler算法，降低了面积成本和功耗，加快了编码过程。Cordic算法的改进是通过减少大量的迭代序列来实现的。此外，该设计还集成了改进进位预判加法器（MCLA）和进位保存加法器（CSA），以最大限度地减少算术运算和内存需求。实验结果表明，与其他竞争的Cordic-DCT算法相比，该架构实现了高效的平均峰值信噪比（PSNR），特别是内窥镜图像压缩，同时减少了加法/移位操作。所提出的架构使用Xilinx ISE 13.1实现Virtex5-FPGA，工作频率为254.6 MHz， 100 MHz时功耗为39 mW。这些结果超过了大多数以前的Virtex-4/Virtex-5 FPGA实现架构的性能。根据使用台积电130纳米技术实现ASIC的性能估计，提出的设计在100 MHz时功耗约为4.68 mW，明显低于之前的工作。因此，所提出的2D-DCT架构特别适用于低功耗、高质量的编解码器，使其成为电池供电的嵌入式系统的理想选择。

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引用次数: 0

Cross-regulation characteristics of non-ideal single-inductor dual-output buck converter with voltage controlled 电压控制下非理想单电感双输出降压变换器的交叉调节特性

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-03 DOI: 10.1016/j.vlsi.2025.102575

Bingli Liu , Jiarong Wu , Liping Luo , Chunming Wen , Weilin Wu , Hailong Ma

Single-inductor multiple-output (SIMO) dc-dc converters are widely adopted in smart homes due to their high efficiency and small circuit volume. However, cross-regulation (CR) seriously influences the dynamic performance and the stability of SIMO dc-dc converters. In this paper, the CR characteristics of a non-ideal single-inductor dual-output (NI-SIDO) Buck converter with voltage control are analyzed, which includes parasitic resistors of the inductor and output capacitors. A nonlinear mathematical model and small-signal circuit are built, deducing the CR transfer functions and CR impedances. Therefore, the important factors affecting the CR are explored. Moreover, the CR characteristics are studied by the Bode plot under the common-mode voltage and differential-mode voltage control. The simulation results demonstrate that increasing the parasitic resistor of the inductor reduces the CR between the output branches. Furthermore, when the parasitic resistor of a branch output capacitor increases, the CR of the other output branch decreases accordingly. Finally, an experimental prototype is constructed to provide the correctness of the theoretical analysis.

单电感多输出（SIMO） dc-dc变换器以其效率高、电路体积小等优点被广泛应用于智能家居中。然而，交叉调节严重影响SIMO dc-dc变换器的动态性能和稳定性。本文分析了具有电压控制的非理想单电感双输出（NI-SIDO） Buck变换器的CR特性，包括电感的寄生电阻和输出电容。建立了非线性数学模型和小信号电路，推导了CR传递函数和CR阻抗。因此，对影响CR的重要因素进行了探讨。此外，利用波德图研究了共模电压和差模电压控制下的CR特性。仿真结果表明，增大电感的寄生电阻可以降低输出支路间的电阻阻抗。另外，当一个支路输出电容的寄生电阻增大时，另一个输出支路的CR相应减小。最后搭建了实验样机，验证了理论分析的正确性。

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引用次数: 0

A PSRR enhanced capacitorless LDO with gate capacitance cancellation technique 采用门电容对消技术的PSRR增强无电容LDO

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-01 DOI: 10.1016/j.vlsi.2025.102573

Hang Shu , Pengfei Liao , Yong Tao , Wensuo Chen

—Switching power supplies, characterized by significant power noise, can degrade the performance of display driver ICs, especially with switching frequencies ranging from hundreds of kilohertz to several megahertz. To minimize this power noise, low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) are essential. This paper introduces a capacitorless LDO regulator that integrates a gate capacitance cancellation (GCC) technique for enhanced PSRR and a class-AB operational amplifier for improved transient response. Post-layout simulation results in 180-nm CMOS technology confirm the effectiveness of the proposed design. With an input voltage of 1.5 V, the LDO exhibits a settling time of only 0.15 μs under an undershoot voltage of 122.8 mV and 0.24 μs under an overshoot voltage of 92.8 mV. The proposed CL-LDO achieves a PSRR of −75.3 dB at 398 kHz, with a total on-chip capacitance as low as 8.8 pF. This design offers superior noise suppression and transient response, making it well-suited for applications requiring stable and clean power supply in noise-sensitive environments.

-开关电源的特点是显著的功率噪声，可以降低显示驱动ic的性能，特别是开关频率范围从数百千赫兹到几兆赫兹。为了尽量减少这种功率噪声，具有高电源抑制比（PSRR）的低差（LDO）稳压器是必不可少的。本文介绍了一种无电容LDO稳压器，该稳压器集成了用于增强PSRR的门电容抵消（GCC）技术和用于改善瞬态响应的ab类运算放大器。在180nm CMOS技术下的布局后仿真结果证实了所提设计的有效性。当输入电压为1.5 V时，LDO在122.8 mV欠调电压下的沉降时间仅为0.15 μs，在92.8 mV过调电压下的沉降时间仅为0.24 μs。所提出的CL-LDO在398 kHz时的PSRR为- 75.3 dB，片上总电容低至8.8 pF。该设计具有出色的噪声抑制和瞬态响应，非常适合在噪声敏感环境中需要稳定清洁电源的应用。

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引用次数: 0

Low power current-mode hybrid computing architecture signal processing circuit 低功耗电流模式混合计算架构信号处理电路

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-01 DOI: 10.1016/j.vlsi.2025.102571

Yuhang Lu, Huimin Liu

To address the increasingly prominent physical limitations and energy efficiency challenges in digital circuits, this paper proposes an innovative current-mode computing paradigm and presents a low-power current-mode hybrid computing architecture specifically designed for signal processing circuits. The core current-mode circuits of the architecture employ the MOSFET Translinear loop (MTL) principle. The key contributions include the structural simplification of the MTL nonlinear computing unit, flipped voltage follower biasing, which enables reliable low-voltage operation, and a significant reduction in silicon area and power consumption. The proposed design demonstrates versatile capabilities for implementing nonlinear functions, including square, absolute value, square root, and multiplication operations. By incorporating multiplier circuits, the design achieves a configurable-coefficient hybrid current-mode low-voltage discrete third-order Finite Impulse Response (FIR) filter, effectively mitigating the high-power consumption and area overhead caused by high-bit-width operations and fractional coefficients in conventional digital filter implementations. Additionally, a 6-bit flash current-mode ADC is introduced to serve as an interface between current-domain analog circuits and digital systems. Simulation results based on 28 nm CMOS technology with a 0.9V supply voltage confirm the functional robustness of the proposed circuit across temperature variations and process corners. Compared with conventional MTL implementations, the proposed solution not only achieves enhanced stability under low-voltage operation but also preserves computational accuracy comparable to 32-bit floating-point digital filters. Most notably, the hybrid architecture demonstrates significant improvements in both power efficiency (63 % reduction) and silicon area utilization (25 % reduction), setting a new state-of-the-art standard for energy-efficient signal processing systems.

为了解决数字电路中日益突出的物理限制和能效挑战，本文提出了一种创新的电流模式计算范式，并提出了一种专为信号处理电路设计的低功耗电流模式混合计算架构。该架构的核心电流模式电路采用了MOSFET跨线性环路（MTL）原理。主要贡献包括MTL非线性计算单元的结构简化，翻转电压从动器偏置，实现可靠的低压运行，以及硅面积和功耗的显着减少。提出的设计展示了实现非线性函数的多种功能，包括平方，绝对值，平方根和乘法运算。通过结合乘法器电路，该设计实现了可配置系数混合电流模式低压离散三阶有限脉冲响应（FIR）滤波器，有效减轻了传统数字滤波器实现中由高位宽操作和分数系数引起的高功耗和面积开销。此外，还引入了一个6位闪存电流模式ADC，作为电流域模拟电路和数字系统之间的接口。基于28 nm CMOS技术、0.9V电源电压的仿真结果证实了该电路在温度变化和工艺拐角上的功能稳健性。与传统的MTL实现相比，该方案不仅提高了低压工作下的稳定性，而且保持了与32位浮点数字滤波器相当的计算精度。最值得注意的是，混合架构在功率效率（减少63%）和硅面积利用率（减少25%）方面都有显着改善，为节能信号处理系统设定了新的最先进标准。

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引用次数: 0

Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology 基于FinFET 18nm技术的软误差弹性13T SRAM架构设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-01 DOI: 10.1016/j.vlsi.2025.102574

Anish Paul , Siya Sharma , Kulbhushan Sharma

As SRAM cells are scaled down to advanced technology nodes, their sensitivity to radiation-induced soft errors increases significantly, making them less reliable for use in critical environments like aerospace and defense. To address this issue, a new 13-transistor radiation-hardened SRAM cell, called SEFCR-13T, is proposed using 18 nm FinFET technology. The cell uses a feedback-cutting technique and redundant node structure to improve soft-error tolerance while maintaining a balance among power, speed, and area. The SEFCR-13T cell is designed and simulated using Cadence Virtuoso and compared with five existing SRAM cells: Conventional 6T, Hybrid 12T, TRD 9T, RHIRS 12T, and RRS 14T. Key performance parameters such as critical charge, static noise margins (SNM), power consumption, delay, and area were evaluated across a voltage range of 0.6 V–1.0 V. At 0.7 V, the proposed SEFCR 13T shows the highest critical charge of 3.67 fC, which is 2.65 × higher than the 6T SRAM and 1.2 × higher than RHIRS 12T. It also achieves a write SNM improvement of up to 2.95 × and read SNM improvement of 2.67 × compared to the 6T cell. Read and write delays are reduced by 2.5 × and 1.8 × , respectively, while read power is reduced by 2.4 × . The proposed design also achieves the highest overall figure of merit (FOM), 17 × better than 6T SRAM. These results show that the proposed cell provides excellent improvement in soft-error resistance and overall stability, making it a strong candidate for reliable memory design in radiation-prone and low-power applications.

随着SRAM单元缩小到先进的技术节点，它们对辐射引起的软误差的敏感性显着增加，使它们在航空航天和国防等关键环境中使用的可靠性降低。为了解决这个问题，提出了一种新的13晶体管抗辐射SRAM单元，称为SEFCR-13T，采用18nm FinFET技术。该单元采用反馈切割技术和冗余节点结构来提高软误差容忍度，同时保持功率、速度和面积之间的平衡。使用Cadence Virtuoso对SEFCR-13T单元进行了设计和仿真，并与现有的五种SRAM单元进行了比较：常规6T、混合12T、TRD 9T、RHIRS 12T和RRS 14T。关键性能参数如临界电荷、静态噪声裕度（SNM）、功耗、延迟和面积在0.6 V - 1.0 V电压范围内进行了评估。在0.7 V下，SEFCR 13T显示出最高的临界电荷为3.67 fC，比6T SRAM高2.65倍，比rirs 12T高1.2倍。与6T单元相比，它还实现了高达2.95倍的写SNM改进和2.67倍的读SNM改进。读时延降低2.5倍，写时延降低1.8倍，读功耗降低2.4倍。提出的设计还实现了最高的总体性能（FOM），比6T SRAM好17倍。这些结果表明，所提出的电池在抗软误差和整体稳定性方面提供了出色的改进，使其成为辐射易发和低功耗应用中可靠存储器设计的有力候选者。

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引用次数: 0

Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design 功率门控sram和基于超低功耗查找表的新型头脚多路复用器设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-09-27 DOI: 10.1016/j.vlsi.2025.102566

Meeniga Srikanth Reddy , Debanjali Nath , Debajit Deb

In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01

μ

W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42

μ

W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.

在本文中，我们提出了一种两级功率门控技术，该技术可以显著降低通管（PTL）和基于传输门（T-Gate）的查找表（LUT）的泄漏功率，该技术使用cadence的45 nm通用库设计。SRAM阵列的一级功率门控降低了器件的亚阈值和栅极泄漏。在LUT的电源门MUX逻辑中实现了一种新颖的Header/Footer逻辑。与传统的仅切断电源或接地以减少泄漏的表头/脚方案不同，我们的二极管连接表头和反馈控制的脚能够在抑制泄漏的同时实现并联输出电平恢复。反馈控制脚（NFD）确保来自多路复用器的弱逻辑电平不会传播到输出缓冲区，从而减少亚阈值和门漏。功率门控SRAM的平均功耗从6.09 pW降低到1.884 pW （write-1操作）。SRAM阵列中的功率门控使得基于通通晶体管的LUT水平的平均功率从17.01μ W降低到153.05 nW，降低了3个数量级。基于T-Gate的MUX-LUT的功率门控sram的平均功耗从16.42μ W降至688.3 nW，平均功耗降低了3个数量级。当在MUX级别应用新颖的页眉/页脚逻辑时，PTL和基于t门的设计的值进一步降低了三个数量级以上。布局后的仿真进一步验证了与传统和门控SRAM的布局前结果相比，寄生效应降低了整体功耗。此外，CLB实现在低性能模式下展示了389.8 pW的超低功耗（HP=0），突出了所提出的架构相对于传统基于lut的设计的实际优势。所提出设计的实现在SRAM的输入到CLB的最终输出之间没有可观察到的数据传输延迟。

{"title":"Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design","authors":"Meeniga Srikanth Reddy , Debanjali Nath , Debajit Deb","doi":"10.1016/j.vlsi.2025.102566","DOIUrl":"10.1016/j.vlsi.2025.102566","url":null,"abstract":"<div><div>In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01<span><math><mi>μ</mi></math></span> W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42<span><math><mi>μ</mi></math></span> W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102566"},"PeriodicalIF":2.5,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145221216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nadam optimized deep self-guided clustering dual-domain attention network security framework for reliable detection of malicious modules in VLSI circuits Nadam优化了深度自引导聚类双域关注网络安全框架，实现了VLSI电路中恶意模块的可靠检测

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-09-26 DOI: 10.1016/j.vlsi.2025.102570

M.Maria Rubiston , B.R. Tapas Bapu , R. Radhika , R. Anitha

The exponential growth of Very-Large-Scale Integration (VLSI) circuit complexity has emerged as a source of hardware security concern, particularly the covert implantation of Hardware Trojans (HTs) that compromise the reliability and confidentiality of integrated systems. Traditional detection techniques are grossly disadvantaged by their inability to scale up, generalize, and identify covert Trojan modules. To address these shortcomings, this work proposes a Nadam Optimized Deep Self-Guided Clustering Dual-Domain Attention Network (DSGCN-D2AM-NOA)-based security platform that can detect malicious modules with high accuracy and minimal supervision. The goal is to develop an explainable and scalable HT detection pipeline, starting with rare node detection and feature extraction using Adjusted Decimal Scaling with Statistical Column Normalization (ADS-SCN), followed by pre-processing with a Deep Fuzzy min-max Network (DFmmN). The detection and classification pipeline is centered on a Deep Self-Guided Clustering Dual-Domain Attention Network (DSGCN-D2AM) that integrates Dual-Domain Attention Mechanism (D2AM) and Deep Self-Guided Clustering Network (DS-GCN). The model is advanced further by the Nadam Optimization Algorithm (NOA) to achieve stability in convergence and optimal learning of parameters. Experimental assessment was carried out on benchmark ISCAS'85 and ISCAS'89 circuits. The proposed DSGCN-D2AM-NOA framework resulted in an outstanding 99.89 % detection accuracy with 0.11 % false positive instances and 99.92 % precision, beating all state-of-the-art methods. These results demonstrate the model's ability to detect both subtle and clever HTs without relying on golden references. In short, the DSGCN-D2AM-NOA framework provides a strong and reliable solution for real-time and scalable HT detection. Its modularity and high interpretability make it possible for it to be used in critical security-sensitive applications in the VLSI design and verification process.

超大规模集成电路（VLSI）复杂性的指数级增长已经成为硬件安全问题的一个来源，特别是硬件木马（ht）的隐蔽植入危及集成系统的可靠性和机密性。传统的检测技术由于无法扩展、泛化和识别隐蔽的木马模块而处于严重的劣势。为了解决这些缺点，本研究提出了一种基于那达慕优化深度自引导聚类双域注意网络（DSGCN-D2AM-NOA）的安全平台，该平台能够以高精度和最少的监督检测恶意模块。目标是开发一个可解释和可扩展的HT检测管道，从使用统计列归一化（ADS-SCN）的调整十进制缩放的稀有节点检测和特征提取开始，然后使用深度模糊最小-最大网络（DFmmN）进行预处理。检测和分类管道以深度自导向聚类双域注意网络（DSGCN-D2AM）为中心，该网络集成了双域注意机制（D2AM）和深度自导向聚类网络（DS-GCN）。通过那达慕优化算法（NOA）对模型进行进一步改进，使其收敛稳定性和参数的最优学习。在基准电路ISCAS’85和ISCAS’89上进行了实验评估。提出的DSGCN-D2AM-NOA框架的检测准确率为99.89%，假阳性实例为0.11%，精度为99.92%，击败了所有最先进的方法。这些结果表明，该模型能够在不依赖黄金参考的情况下检测出微妙的和聪明的高温高温。总之，DSGCN-D2AM-NOA框架为实时和可扩展的高温高温检测提供了强大可靠的解决方案。它的模块化和高可解释性使得它可以用于VLSI设计和验证过程中对安全敏感的关键应用。

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引用次数: 0

Leveraging asynchronous quantum secretary bird Generative propagation adversarial attention networks for FIR filter design in ECG applications 利用异步量子秘书鸟生成传播对抗注意网络进行心电应用中的FIR滤波器设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-09-26 DOI: 10.1016/j.vlsi.2025.102569

Theivanathan G, Murukesh C

The escalating demand for better ECG signal analysis has created a demand for designs of better filters. This paper provides an alternate methodology towards proposing filter designs, through the use of Asynchronous Quantum Secretary Bird Generative Propagation Adversarial Attention Networks (Asyn-Qan-SBG-P2AN). In this proposal, the optimal filter coefficients are derived through the employment of Quantum Generative Adversarial Networks (QGAN), filter response characteristics are derived using Asynchronous Propagation Attention Networks (APAN) for adaptive signal feature extraction, and finally, using the Secretary Bird Optimization Algorithm (SBOA) based upon a filter's role, couples with Asyn-Qan-SBG-P2AN in differentiating ECG signals from other physiological measurements. Technology and method have combined to offer a generation of smart, adaptive and learning-based filter design in ECG applications. Our band-pass FIR filter has marked improvements in signal clarity, noise suppression, and resources being used to offer newly stunned opportunities for signal processing using lower specifications. Contributor offers a power consumption of 12 mW, Area 10 mm², Operating speed 300 MHz, and Frequency 4.8 GHz. The parameters also provide evidence that machine learning solutions can be used in real-time processing of ECG signals while capturing diagnostic AUCs, and provide a coronation for lower power possible in wearables.

对更好的心电信号分析的不断增长的需求产生了对设计更好的滤波器的需求。本文通过使用异步量子秘书鸟生成传播对抗性注意网络（异步- qan - sbg - p2an），提供了一种提出滤波器设计的替代方法。在该方案中，通过使用量子生成对抗网络（QGAN）推导出最优滤波器系数，使用异步传播注意网络（APAN）推导出滤波器响应特性，用于自适应信号特征提取，最后，使用基于滤波器作用的秘书鸟优化算法（sba），结合asynqan - sbg - p2an将心电信号与其他生理测量信号区分开来。技术和方法相结合，在ECG应用中提供了一代智能，自适应和基于学习的滤波器设计。我们的带通FIR滤波器在信号清晰度，噪声抑制和资源使用方面有显著改善，为使用较低规格的信号处理提供了新的震惊机会。Contributor的功耗为12 mW，面积为10 mm2，工作速度为300 MHz，频率为4.8 GHz。这些参数还提供了证据，证明机器学习解决方案可以在捕获诊断auc的同时用于实时处理ECG信号，并为可穿戴设备的低功耗提供了可能。

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引用次数: 0

An analytical approach and fine-tuning strategy for PCB placement optimization PCB布局优化的分析方法与微调策略

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-09-26 DOI: 10.1016/j.vlsi.2025.102567

Hongyu Zhao, Yunhao Hu, Zhuomin Chai, Peng Wei, Shupei He, Wei Liu

As the foundation for connecting and supporting various electronic components, Printed Circuit Boards (PCBs) play an important role in modern electronic systems. The quality of PCBs physical design directly impacts the performance, reliability, and cost of the entire circuit. However, the automation of PCB physical design remains an issue that has not been fully resolved. In order to obtain high quality PCBs, component placement is the most important stage in an PCB design, and its result significantly influences both the wirelength and the overall routability of the design. Hence, we propose an analytical automated placement algorithm tailored for PCBs in this paper, including three stages: global placement, legalization, and fine-tuning. We perform an extensive study with 10 PCB designs and an open-source router. We show that the quality of our placement results is closer to that of manual. Compared to traditional algorithms, our analytical approach achieves higher routing completion rates and significantly reduces placement runtime.

印刷电路板作为连接和支撑各种电子元件的基础，在现代电子系统中起着重要的作用。pcb物理设计的质量直接影响到整个电路的性能、可靠性和成本。然而，PCB物理设计的自动化仍然是一个尚未完全解决的问题。为了获得高质量的PCB，元件放置是PCB设计中最重要的阶段，其结果对设计的无线长度和整体可达性都有重大影响。因此，我们在本文中提出了一种针对pcb定制的分析自动放置算法，包括三个阶段：全局放置，合法化和微调。我们对10个PCB设计和一个开源路由器进行了广泛的研究。我们表明，我们的放置结果的质量更接近于人工。与传统算法相比，我们的分析方法实现了更高的路由完成率，并显著缩短了放置运行时间。

引用次数: 0

True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation 基于分数阶Sprott H混沌系统的真随机数发生器设计及统计验证

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-09-24 DOI: 10.1016/j.vlsi.2025.102555

Mehmet Ziya Hoşbaş , Berkay Emi̇n , Akif Akgül , Fırat Kaçar

The increasing demand for secure communication systems has emphasized the necessity of high-quality entropy sources in cryptographic applications. True Random Number Generators (TRNGs), which derive randomness from physical and chaotic processes, are essential for ensuring data confidentiality in domains such as the Internet of Things (IoT), healthcare, and wireless communication. This study presents a novel TRNG architecture based on the Fractional-Order Sprott H Chaotic System (FOSHCS), a model not previously employed in TRNG design. The chaotic properties of FOSHCS were rigorously evaluated through bifurcation diagrams, the maximum Lyapunov exponent (MLE), and attractor projections, confirming its viability as a reliable entropy source. The system was physically implemented on an NVIDIA Jetson AGX Orin platform using a custom-designed DAC circuit to observe the chaotic trajectories in the analog domain. Furthermore, real-time GPU temperature data was incorporated with the chaotic output to enhance entropy diversity. The resulting bitstreams underwent standard statistical randomness tests, including the NIST SP 800-22, FIPS 140-1, and ENT test suites, all of which were successfully passed. The integration of fractional-order chaotic modeling with physical entropy harvesting enabled the development of a compact and high-entropy TRNG suitable for embedded and security-critical applications. To the best of our knowledge, this work represents the first hardware realization of a TRNG based on the FOSHCS, offering a promising new direction in secure and robust random number generation.

对安全通信系统日益增长的需求强调了高质量熵源在密码学应用中的必要性。真随机数生成器（trng）从物理和混沌过程中获得随机性，对于确保物联网（IoT）、医疗保健和无线通信等领域的数据机密性至关重要。本研究提出了一种基于分数阶Sprott H混沌系统（FOSHCS）的新型TRNG架构，这是一种以前未在TRNG设计中使用的模型。通过分岔图、最大Lyapunov指数（MLE）和吸引子投影对FOSHCS的混沌特性进行了严格评价，证实了其作为可靠熵源的可行性。该系统在NVIDIA Jetson AGX Orin平台上物理实现，使用定制设计的DAC电路来观察模拟域中的混沌轨迹。此外，将实时GPU温度数据与混沌输出相结合，增强了熵的多样性。生成的比特流经过标准的统计随机性测试，包括NIST SP 800-22、FIPS 140-1和ENT测试套件，均成功通过。分数阶混沌建模与物理熵收集的集成使开发适合嵌入式和安全关键应用的紧凑高熵TRNG成为可能。据我们所知，这项工作代表了基于FOSHCS的TRNG的第一个硬件实现，为安全和鲁棒随机数生成提供了一个有希望的新方向。

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引用次数: 0