Integration-The Vlsi Journal最新文献_第8页

A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units 综合分析亚10nm CNFET技术对64位并行前缀加法器和32位矩阵乘法单元的影响

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-14 DOI: 10.1016/j.vlsi.2025.102583

Chenlin Shi , Tongxin Yang , Ryota Shioya , Hayato Yamaki , Hiroki Honda , Shinobu Miwa

In this paper, we provide the first thorough analysis of LSI circuits implemented using sub 10-nm carbon nanotube field effect transistors (CNFETs). Unlike many previous studies in which researchers performed the analysis of CNFET circuits at the SPICE level, we focus on netlists placed and routed using the state-of-the-art CNFET cell libraries. This approach enables us to analyze a more complex and wider range of CNFET circuits (i.e., various architectures that have the same functionality) than researchers in previous studies, while considering various effects of the circuits’ physical layout. Our experimental results demonstrate that, under comparable technology nodes, circuits implemented with CNFET technology can achieve superior performance compared to state-of-the-art 3-nm FinFET technology, exhibiting an energy-delay product (EDP) improvement of up to over 23

\times

for 64-bit Parallel Prefix Adders (PPAs) and up to over 18

\times

for 32-bit Matrix Multiply Units (MMUs). In addition, our analysis shows that the impact of both local and global wires on delay and energy consumption is more substantial in CNFET circuits than in FinFET circuits, and wire savings, which could lead to an EDP improvement of up to 49% in large-scale CNFET circuits, are therefore crucial for the optimization of the EDP of CNFET circuits, even with considering process variations. This study opens up a new opportunity to develop a wire-aware design for CNFET circuits.

在本文中，我们首次对使用亚10nm碳纳米管场效应晶体管（cnfet）实现的LSI电路进行了全面分析。与许多先前研究人员在SPICE级别对CNFET电路进行分析的研究不同，我们专注于使用最先进的CNFET细胞库放置和路由的网络列表。这种方法使我们能够分析比以前研究人员更复杂和更广泛的CNFET电路（即具有相同功能的各种架构），同时考虑电路物理布局的各种影响。我们的实验结果表明，在可比较的技术节点下，与最先进的3纳米FinFET技术相比，采用CNFET技术实现的电路可以实现卓越的性能，对于64位并行前缀加法器（PPAs），能量延迟积（EDP）提高了23倍以上，对于32位矩阵乘单元（mmu），能量延迟积（EDP）提高了18倍以上。此外，我们的分析表明，在CNFET电路中，局部和全局导线对延迟和能耗的影响比在FinFET电路中更大，并且在大规模CNFET电路中，节省导线可能导致EDP提高高达49%，因此对于优化CNFET电路的EDP至关重要，即使考虑到工艺变化。这项研究为CNFET电路的线感设计开辟了一个新的机会。

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引用次数: 0

Enhancing logic optimization of Alliance tool based on directed acyclic graphs 基于有向无环图的联盟工具逻辑优化

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-14 DOI: 10.1016/j.vlsi.2025.102580

Qiyao He, Zhang Hu, Yinshui Xia, Lunyao Wang, Zhufei Chu

High efficiency and robust optimization are critical for modern electronic design automation (EDA) tools, particularly as circuit complexity and design constraints continue to grow. Alliance is an open-source EDA tool designed for digital circuit design that supports logic synthesis, placement, and routing. This paper addresses the limitations of the Alliance tool in handling large-scale complex circuits by proposing a directed acyclic graph (DAG)-based logic optimization method. We integrate this method directly into the Alliance framework, streamlining the digital synthesis process. By eliminating the need for external tools or intermediate steps, our approach reduces data redundancy and enhances execution efficiency. Using EPFL benchmarks, we demonstrate that our method improves delay and area by 49% and 65%, respectively, compared to the Alliance toolchain. Furthermore, it outperforms Coriolis, which is tailored for full-flow ASIC physical design, in placement and routing (P&R) and achieves a 27% improvement in wirelength expansion ratio, resulting in a 1.88x speedup.

高效率和稳健的优化对于现代电子设计自动化（EDA）工具至关重要，特别是在电路复杂性和设计约束不断增长的情况下。Alliance是为数字电路设计而设计的开源EDA工具，支持逻辑合成、放置和路由。本文提出了一种基于有向无环图（DAG）的逻辑优化方法，解决了联盟工具在处理大规模复杂电路方面的局限性。我们将这种方法直接集成到联盟框架中，简化了数字合成过程。通过消除对外部工具或中间步骤的需求，我们的方法减少了数据冗余并提高了执行效率。使用EPFL基准测试，我们证明与联盟工具链相比，我们的方法分别将延迟和面积提高了49%和65%。此外，它在放置和布线方面优于专为全流ASIC物理设计而定制的Coriolis (P&；R)，并且在带宽扩展比方面提高了27%，从而实现了1.88倍的加速。

引用次数: 0

Double-node-upset-hardened full-subtractor applying MTJ for the high energy physics experiments 应用MTJ进行高能物理实验的双节点抗扰全减法器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-13 DOI: 10.1016/j.vlsi.2025.102582

Yuehong Gong , Min Luo , Chenxu Wang , Shanqiang Yang

In radiation environment, the single event effect (SEE) poses great threat to the peripheral circuit of the particle detectors. In order to improve the anti-radiation performance of the CMOS pixel sensor, a double-node-upset-hardened full-subtractor applying magnetic tunnel junction (MTJ) is proposed in this paper. To improve the radiation resistance of the peripheral circuit, a redundancy transistor based peripheral circuitry structure is designed. The working state of the circuit is controlled by the designed reading-writing control circuit. Different from the conventional writing circuit, it controls the writing sequence by an OR gate. This circuit could control the reading and writing to switch flexibly and reduce the writing supply voltage. Simulation results show that the proposed circuit functions as a full-subtractor and the maximum double-node-upset tolerant charge is over 1000fC. This work presents a feasible candidate for the application of MTJ in the digital circuit of CMOS pixel sensors and has great prospect for the high energy physics experiments.

在辐射环境下，单事件效应对粒子探测器的外围电路构成了很大的威胁。为了提高CMOS像素传感器的抗辐射性能，提出了一种基于磁隧道结（MTJ）的双节点加强型全减法器。为了提高外围电路的抗辐射能力，设计了一种基于冗余晶体管的外围电路结构。电路的工作状态由所设计的读写控制电路控制。与传统的写入电路不同，它通过一个OR门来控制写入顺序。该电路可以灵活控制读写开关，降低写入电源电压。仿真结果表明，该电路具有全减法器的功能，最大双节点干扰容忍电荷超过1000fC。本工作为MTJ在CMOS像素传感器数字电路中的应用提供了一个可行的候选方案，在高能物理实验中具有广阔的应用前景。

引用次数: 0

Dynamical analysis and secure communication application of parameter-controlled multiscroll attractors in memristive chaotic system 忆阻混沌系统中参数控制多涡旋吸引子的动力学分析及安全通信应用

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-10 DOI: 10.1016/j.vlsi.2025.102577

Yijin Liu, Qiang Lai, Huangtao Wang, Yongxian Zhang

The nonlinear constitutive relations and multistable memory characteristics of memristors that render them ideal for chaotic systems, this paper introduces the modular arithmetic operations to the memristor and constructs a parameter controlled multiscroll memristive chaotic system (PCMMCS). The unique nonlinearity of modular arithmetic operations endows the system with distinctive dynamical behaviors. Specifically, PCMMCS exhibits a multiplicity of equilibrium points, the types and locations can be regulated via parametric modulation. This mechanism enables precise control over the number of multiscroll attractors, thereby establishing a direct parametric dependency for attractor configuration. The heterogeneous, homogeneous coexisting attractors and infinite coexisting attractors in the system are formatted via initial value manipulation. A hardware realization of the system has been developed, with multiscroll attractor dynamics successfully observed and characterized on an oscilloscope. The PCMMCS was further developed into a dynamic carrier-differential frequency chaos keying (DC-DFCK) secure communication scheme, and experimental results confirming its operational validity, thereby demonstrating the practical applicability of PCMMCS.

由于忆阻器的非线性本构关系和多稳记忆特性使其成为混沌系统的理想器件，本文将模运算引入到忆阻器中，构造了一个参数控制的多涡旋忆阻混沌系统。模运算特有的非线性特性赋予了系统独特的动力学行为。具体来说，PCMMCS具有多重平衡点，其类型和位置可以通过参数调制来调节。这种机制可以精确控制多卷轴吸引子的数量，从而为吸引子配置建立直接的参数依赖关系。通过初始值处理对系统中的异质、同质和无限共存吸引子进行了格式化。开发了系统的硬件实现，并在示波器上成功地观察和表征了多涡旋吸引子的动态。将PCMMCS进一步发展为动态载波-差频混沌键控（DC-DFCK）保密通信方案，实验结果验证了其运行有效性，从而证明了PCMMCS的实际适用性。

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引用次数: 0

HDHL: A hybrid GSP lightweight block cipher with two-round high diffusion HDHL：一种混合GSP轻量级分组密码，具有两轮高扩散

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-10 DOI: 10.1016/j.vlsi.2025.102581

Xingqi Yue, Lang Li, Qingling Song

Lightweight cryptography is crucial for securing data in resource-constrained IoT devices. However, most existing lightweight block ciphers suffer from slow diffusion, high hardware cost, or insufficient side-channel resistance, limiting their practical deployment. To address these challenges, this work proposes HDHL, a 64-bit block cipher that integrates a hybrid Generalized Feistel and Substitution-Permutation Network (GSP) structure. The design features a 64-bit sponge-based

F

-function for strong nonlinearity, lightweight AND-Rotation-XOR (AND-RX) operations for enhanced confusion, and an involutive linear layer that enables efficient encryption and decryption with a unified datapath. A compact LFSR-driven key schedule delivers four 16-bit sub-keys per round with near-ideal entropy. Experimental results show that HDHL achieves full diffusion in just two rounds, area occupies only 1756.71 gate equivalents (GE), and energy 7.82

μ

J/bit at a 100 kHz test clock, outperforming CRAFT and SKINNY-64 in both area and energy. Security evaluation demonstrates strong resistance against differential, linear, integral, and algebraic attacks, with a seven-round differential probability below

2^{- 70}

. Fixed-random

t

-tests on a prototype ASIC confirm first-order side-channel resistance when lightweight masking or a two-share threshold implementation is applied. These results indicate that HDHL offers a balanced combination of security, efficiency, and implementation cost, making it a promising candidate for future low-power embedded applications.

轻量级加密对于保护资源受限的物联网设备中的数据至关重要。然而，现有的大多数轻量级分组密码存在扩散慢、硬件成本高或侧信道阻力不足等问题，限制了它们的实际部署。为了应对这些挑战，本研究提出了HDHL，一种集成了混合广义费斯特尔和替换置换网络（GSP）结构的64位分组密码。该设计具有一个基于64位海绵的f函数，用于强非线性，轻量级and - rotation - xor （and - rx）操作，用于增强混淆，以及一个对合线性层，通过统一的数据路径实现高效的加密和解密。紧凑的lfsr驱动密钥调度每轮提供4个16位子密钥，熵接近理想。实验结果表明，在100 kHz测试时钟下，HDHL仅用两轮就实现了完全扩散，面积仅为1756.71个栅极当量（GE），能量为7.82 μJ/bit，在面积和能量上均优于CRAFT和SKINNY-64。安全评估显示对微分、线性、积分和代数攻击具有很强的抵抗力，七轮差分概率低于2 - 70。在原型ASIC上的固定随机t检验确认了当轻量级屏蔽或双共享阈值实现应用时的一阶侧通道电阻。这些结果表明，HDHL提供了安全性、效率和实现成本的平衡组合，使其成为未来低功耗嵌入式应用的有希望的候选者。

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引用次数: 0

A new circuit configuration for emulating charge/flux controlled memelements 一种模拟电荷/磁通控制元件的新电路结构

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-09 DOI: 10.1016/j.vlsi.2025.102576

Shashi Prakash, Mayank Srivastava, Mrutyunjay Rout

The mem-elements are the extension of the memristor idea to memory capacitors and inductors. In this article, an electronic circuit is designed to realize the behavior of all three mem-elements: the memristor, meminductor, and memcapacitor. A key aspect of this study is that the proposed emulator can implement a charge-controlled memristor (CCMR), a flux-controlled memcapacitor (FCMC), and a flux-controlled meminductor (FCMI) using a CCII and Transconductance amplifier (TA), with only a few passive elements and switches. The performance of the proposed emulator is analyzed through simulation results obtained using P-Spice software. The frequency range of the proposed emulator is found to be satisfactory, with an operating frequency of up to 1.2 MHz. Furthermore, these results are validated by available commercial ICs like AD844 and LM13700. The analysis of various parameters, including Monte Carlo simulations, electronic tunability, and non-volatile behavior, demonstrates the strength and robustness of the proposed emulator. Additionally, this emulator has potential applications in neuromorphic computing, as it can mimic associative learning behavior and amoeba-like behavior in memristor and meminductor networks, respectively. The proposed design has also been validated on the breadboard implementation using physical ICs and results are demonstrated.

记忆元件是记忆电阻器思想在记忆电容器和电感中的延伸。在本文中，设计了一个电子电路来实现所有三个mems元件的行为：忆阻器，忆电感器和忆电容。本研究的一个关键方面是，所提出的仿真器可以实现一个电荷控制的忆阻器（CCMR），一个磁通控制的memcapacitor (FCMC)，以及一个磁通控制的meminductor (FCMI)，使用一个CCII和跨导放大器（TA），只有少数的无源元件和开关。通过P-Spice软件的仿真结果，分析了该仿真器的性能。仿真器的频率范围令人满意，工作频率高达1.2 MHz。此外，这些结果还通过AD844和LM13700等现有商用ic进行了验证。各种参数的分析，包括蒙特卡罗模拟，电子可调性和非易失性行为，证明了所提出的模拟器的强度和鲁棒性。此外，该模拟器在神经形态计算中有潜在的应用，因为它可以分别模拟记忆电阻器和记忆电感网络中的联想学习行为和阿米巴样行为。所提出的设计也已在使用物理ic的面包板实现上进行了验证，并展示了结果。

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引用次数: 0

Dynamics analysis of 3D hyperchaotic map based on discrete Hopfield neural network coupled discrete cosine memristor 基于离散Hopfield神经网络耦合离散余弦忆阻器的三维超混沌映射动力学分析

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-09 DOI: 10.1016/j.vlsi.2025.102579

Chenkai Zhang, Huibin Wang, Yiyan Zhang, Chunyan Ma

Discrete chaotic maps have garnered considerable attention due to their rapid iteration speeds and their facility in generating hyperchaotic phenomena. Similarly, discrete Hopfield neural networks and discrete memristors are increasingly being explored for their unique nonlinear characteristics. This paper introduces a novel three-dimensional (3D) hyperchaotic map, constructed by coupling a discrete memristor with a discrete Hopfield neural network, thereby exhibiting enhanced dynamic complexity. The fixed points and their stability are theoretically analyzed. Furthermore, numerical simulations reveal rich dynamic behaviors, including the coexistence of heterogeneous attractors, attractor extension, and attractor offset. Additionally, a pseudo-random number generation (PRNG) algorithm based on this model is designed, and its randomness is rigorously evaluated. The results demonstrate that the sequences generated by the PRNG algorithm exhibit favorable randomness properties. Finally, the proposed discrete model is implemented on a Digital Signal Processor (DSP) hardware platform to validate its physical feasibility.

离散混沌映射由于其快速的迭代速度和生成超混沌现象的能力而引起了人们的广泛关注。同样，离散Hopfield神经网络和离散记忆电阻器也因其独特的非线性特性而受到越来越多的研究。本文介绍了一种新的三维（3D）超混沌映射，该映射通过将离散记忆电阻器与离散Hopfield神经网络耦合来构建，从而增强了动态复杂性。从理论上分析了不动点及其稳定性。此外，数值模拟还揭示了丰富的动力学行为，包括异质吸引子共存、吸引子扩展和吸引子偏移。在此基础上设计了伪随机数生成算法，并对其随机性进行了严格评估。结果表明，PRNG算法生成的序列具有良好的随机性。最后，在数字信号处理器（DSP）硬件平台上实现了所提出的离散模型，以验证其物理可行性。

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引用次数: 0

Dynamical analysis and FPGA implementation of a memristive non-Hamiltonian conservative hyperchaotic system with extreme multistability 极端多稳定记忆非哈密顿保守超混沌系统的动力学分析与FPGA实现

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-08 DOI: 10.1016/j.vlsi.2025.102565

Runze Lan, Yumeng Wang, Tianxing Xia, Liandong Lin

Recent studies indicate that coupling a memristor with a nonlinear circuit can generate more complex dynamical behaviors. However, research on high-dimensional memristor-based conservative systems remains scarce, and existing low-dimensional memristive systems have yet to exhibit rich dynamic characteristics. In this work, we integrate a magnetically controlled memristor into a conservative chaotic circuit, proposing a novel four-dimensional memristive non-Hamiltonian conservative hyperchaotic system (MHHS) with hidden chaotic dynamics. Through dissipation analysis, Lyapunov exponents, and energy evolution, we verify the system’s non-Hamiltonian conservative properties and hyperchaotic nature. The MHHS system demonstrates high sensitivity to initial conditions and parameters, exhibiting extreme multistability phenomena governed by Hamiltonian energy variations. Phase-space analysis reveals diverse multistable attractors under different initial conditions. Time-series analysis further identifies three distinct transition behaviors: (1) amplitude expansion, (2) quasiperiodic-to-hyperchaotic transitions, and (3) the coexistence of multiple topological states. The system’s chaotic sequences pass the NIST randomness tests, confirming strong pseudorandomness, while Shannon entropy (SE) complexity analysis highlights their high unpredictability. Finally, we implement the MHHS system on FPGA hardware using the fourth-order Runge–Kutta method, experimentally validating its physical realizability. This study not only advances the theoretical understanding of conservative hyperchaotic systems but also provides practical foundations for high-security chaos-based encryption applications.

近年来的研究表明，将忆阻器与非线性电路耦合可以产生更复杂的动态行为。然而，对基于高维忆阻器的保守系统的研究仍然很少，现有的低维忆阻系统还没有表现出丰富的动态特性。在这项工作中，我们将磁控忆阻器集成到保守混沌电路中，提出了一种新的具有隐藏混沌动力学的四维忆阻非哈密顿保守超混沌系统（MHHS）。通过耗散分析、李雅普诺夫指数和能量演化，验证了系统的非哈密顿保守性和超混沌性质。MHHS系统对初始条件和参数具有很高的敏感性，表现出由哈密顿能量变化控制的极端多稳定性现象。相空间分析揭示了不同初始条件下不同的多稳定吸引子。时间序列分析进一步确定了三种不同的转变行为：(1)振幅扩张，(2)准周期到超混沌的转变，以及(3)多个拓扑状态共存。该系统的混沌序列通过了NIST的随机性测试，证实了其强伪随机性，而香农熵（Shannon entropy， SE）复杂度分析则突出了其高不可预测性。最后，我们利用四阶龙格-库塔方法在FPGA硬件上实现了MHHS系统，实验验证了其物理可实现性。该研究不仅提高了对保守超混沌系统的理论认识，而且为基于混沌的高安全性加密应用提供了实践基础。

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引用次数: 0

Hybrid GACO approach for optimized floorplanning in partially reconfigurable FPGAs 部分可重构fpga布局优化的混合遗传算法

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-08 DOI: 10.1016/j.vlsi.2025.102578

Ramzi ayadi , Med Lassaad kaddachi , Yassine Bouteraa

This paper presents Hybrid GACO, a novel floorplanning framework for Partially Reconfigurable Field-Programmable Gate Arrays (PR-FPGAs) that integrates Genetic Algorithms (GA) and Ant Colony Optimization (ACO). The proposed approach addresses the multi-objective challenges of PR-FPGA floorplanning—including wirelength minimization, timing closure, resource utilization, and reconfiguration overhead—under architectural and runtime constraints. A formal FPGA grid model is introduced to account for heterogeneous resource types and forbidden regions. GA is employed for global exploration of the design space, while ACO provides fine-grained local refinement using pheromone-guided search. A weight calibration and adaptive feedback mechanism ensures cost function responsiveness to implementation metrics. The framework is evaluated on MCNC benchmarks and a real-time object detection system using the YOLOv3-Tiny model on a Xilinx Zynq UltraScale + MPSoC ZU9EG. Experimental results demonstrate that Hybrid GACO outperforms traditional MILP-based (FLORA), GA-based, and simulated annealing (SA)-based methods across all key metrics, including Half-Perimeter Wire Length (HPWL), resource efficiency, reconfiguration time, latency, and power consumption. These results confirm the framework's suitability for dynamic, resource-constrained, and latency-sensitive reconfigurable systems.

本文提出了一种基于遗传算法（GA）和蚁群优化（ACO）的部分可重构现场可编程门阵列（pr - fpga）平面规划框架。提出的方法解决了PR-FPGA平面规划的多目标挑战，包括在架构和运行时约束下的最小带宽、时间关闭、资源利用和重新配置开销。引入了一种正式的FPGA网格模型来考虑异构资源类型和禁止区域。遗传算法用于设计空间的全局探索，蚁群算法使用信息素引导搜索提供细粒度的局部优化。权重校准和自适应反馈机制确保成本函数对实现度量的响应。该框架在MCNC基准测试和实时目标检测系统上进行了评估，该系统使用Xilinx Zynq UltraScale + MPSoC ZU9EG上的YOLOv3-Tiny模型。实验结果表明，混合GACO在所有关键指标上都优于传统的基于milp （FLORA）、基于ga和基于模拟退火（SA）的方法，包括半周线长（HPWL）、资源效率、重构时间、延迟和功耗。这些结果证实了该框架适用于动态、资源受限和延迟敏感的可重构系统。

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引用次数: 0

Novel designs of fault-tolerant nano-scale circuits for digital signal processing using quantum dot technology 基于量子点技术的数字信号处理容错纳米电路的新设计

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal

Pub Date : 2025-10-04 DOI: 10.1016/j.vlsi.2025.102572

Muhammad Zohaib , Nima Jafari Navimipour , Mehmet Timur Aydemir , Seyed-Sajad Ahmadpour

Digital signal processing (DSP) is a crucial engineering field dedicated to the processing and analysis of digital signals. DSP is particularly significant in critical sectors such as telecommunications, medical imaging, and secure communications, where it demands high accuracy, reliability, and real-time performance. In addition, the fault-tolerant (F-T) Arithmetic and Logic Unit (ALU) provides a fundamental building block of DSP architectures, enabling the accurate implementation of arithmetic and logical functions that are essential for advanced computational tasks. However, traditional ALUs were designed using complementary metal-oxide semiconductors (CMOS) and very large-scale integration (VLSI), which led to several challenges, such as high energy consumption, high occupied area, and slow operating speed. These limitations can be effectively addressed through nanotechnology, specifically quantum-dot cellular automata (QCA), which offers high speed, reduces occupying area, and has low power consumption. Accordingly, this paper proposes a QCA-based ALU circuit for DSP applications. The proposed designs integrate an F-T full adder (FA), a QCA-based multiplexer (MUX), and an ALU circuit to enhance performance and efficiency for DSP applications. The validation and verification of all suggested designs are performed using the simulation tool QCADesigner.

数字信号处理（DSP）是一个致力于数字信号处理和分析的关键工程领域。DSP在电信、医疗成像和安全通信等关键领域尤其重要，这些领域要求高精度、可靠性和实时性。此外，容错（F-T）算术和逻辑单元（ALU）提供了DSP架构的基本构建块，能够精确实现对高级计算任务至关重要的算术和逻辑功能。然而，传统的alu是采用互补金属氧化物半导体（CMOS）和超大规模集成电路（VLSI）设计的，这带来了高能耗、高占地面积和运行速度慢等挑战。这些限制可以通过纳米技术有效地解决，特别是量子点元胞自动机（QCA），它提供了高速度，减少占地面积，并具有低功耗。因此，本文提出了一种基于qca的DSP应用ALU电路。提出的设计集成了一个F-T全加法器（FA）、一个基于qca的多路复用器（MUX）和一个ALU电路，以提高DSP应用的性能和效率。使用仿真工具qcaddesigner对所有建议的设计进行验证和验证。

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引用次数: 0