Integration-The Vlsi Journal最新文献

In the indoor environment, the output voltage of a small photovoltaic cell is usually too low to charge the battery or utilize it directly. As a result, this paper proposed a low-voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting. The boost converter utilized switched-capacitor charge pump architecture. Compared with conventional charge pumps, the proposed boost converter uses driver enhancement technology, which improves the output current ability of the circuit and power conversion efficiency. Besides, an adaptive dead-time circuit is designed to further optimize conversion efficiency at low input voltage. The integrated circuit (IC) of the boost converter has been manufactured in a 180 nm BCD process and occupies an active chip area of 1.6mm × 0.6 mm. Experimental measurement results confirm that the voltage boost converter increased the input voltage by four times. And the lowest start-up voltage is 0.12 V. The voltage conversion efficiency is 98 % and the highest power conversion efficiency is 76.7 % at Vin of 0.5 V. The design is suitable for indoor solar energy harvesting.

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 $\mu m^2$, delay is 3.01 ns, power consumption is 0.021 mW and power delay product is 119 fJ.

Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match-lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search-speed. A novel selective-charging and adaptive-discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full-swing CAM cell forms the basis of storage and comparison-evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 × 32-bit and 256 × 144-bit SCAD-CAM arrays dissipate only 0.45–0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low-power ML schemes, viz., low-swing precharge, division and control, and master–slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%–89.35% energy-delay. The average-power reduction of 1.8$\times$–2.4$\times$ establishes the SCAD-CAM as a promising memory architecture for emerging search-intensive applications involving large-scale data workloads.

As the feature size of transistors decreases, multiple bit upsets and single event transient effects become severe in circuits working in radiation environment. In static random-access memories (SRAM), both single event upsets and single event transients need caring about. Fault-tolerant ECCs are optional for SRAM protection, which own the ability to deal with SEU and SET at the same time. We designed a series of low complexity burst error correcting codes with fault detection feature. This can deal with burst errors in memories and transient errors in the decoder. Low complexity ECC simplifies the decoding circuits and reduces hardware overhead. Compared with schemes to deal with SET in decoders, the proposed scheme has obvious advantage on area’s overhead and can be an effective choice for SRAM protection in radiation environment.

A new three-dimensional Jerk chaotic system with line equilibrium points is proposed. The system is researched in detail by the Lyapunov exponent graph, bifurcation diagram, phase diagram, and time domain waveform diagram, which show that the system has rich dynamical behaviors, such as eight types of coexisting attractors, extreme multistability of four different attractor states, and offset boosting in two directions. In addition, the system also has six types of transient chaos, which greatly increase the complexity of the system. We study the variation of the spectral entropy (SE) and C0 complexity when the system takes different initial values. Also, in this paper, the initial conditions under which the system is in a synchronized state are determined by initial values with higher complexity. The correctness of the theoretical analysis and numerical simulation is verified by circuit simulation and hardware experiments. Finally, the new system achieves synchronization control utilizing a designed adaptive backstepping controller, laying the foundation for its subsequent use in secure communications.

Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning-based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization.

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the $\Delta V_{GS}$ of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

In today’s increasingly complex traffic environment, pedestrian detection has become increasingly important. The Histogram of Oriented Gradients (HOG) algorithm has been proven to be highly efficient in pedestrian detection. This paper proposes a low-resource consumption, high-speed hardware implementation for HOG algorithm. In the case of a slight sacrifice in accuracy, it increases computational speed and reduces resource consumption. Experimental results demonstrate that the implementation achieves a speed of 0.933 pixels per clock cycle and consumes 4117 look-up tables and 4.5 Kbits of block RAMs while its accuracy decreases by 1.2% on the INRIA dataset and by 0.11% on the MIT dataset.

Previous work has presented a synthesizable design approach to ease the design of an on-chip period-jitter sensor (PJS) with a high resolution. Although the designer of a very large scale integration (VLSI) chip hopes to use this design as an intellectual property (IP), our analysis reveals that this PJS faces key challenges: high power consumption and vulnerability to static PVT and dynamic IR-drop variations. This work develops several design techniques to conquer these challenges at the same time. Taking the PJS IP for monitoring the clock signal in LPDDR4-4266 as a design example, we implement a synthesized 22 nm 2.133 GHz PJS with a resolution of 1.0 ps to verify the design techniques. Post-layout simulation results show that the new design reduces over half of the power while meeting the resolution specification. It passes functional and electrical verification over a broader process variation than the previous design, and the higher variation resiliency assists the synthesizable Verilog code as a soft IP.

A programmable logic device based on a memristor-diode crossbar and CMOS logic has been developed. The crossbar implements NAND logic gates using memristor ratioed logic and CMOS inverters. The digitally controlled peripheral circuit provides digital signals transmission and allows modification and evaluation memristor states in the crossbar. The proposed logic device circuit requires fewer transistors than known analogues and less area on the chip.

The maximum size of the crossbar in a logic device is estimated by numerical simulation at the level of electrical circuits. The limited size is caused by the degradation of the logic levels voltages in the memristor-diode crossbar. The operability of peripheral circuits as part of a complete electrical circuit of a logic device is demonstrated during the simulation of the execution of logical operations, the processes of modification and evaluation states of individual memristors.