In this paper, we propose a simulator and methodology for predicting the program threshold voltage (Vt) distribution in charge trap-based 3-D NAND flash memory, considering z-direction interference (Z-interference) induced by random grain boundaries (GB) within the polycrystalline silicon (poly-Si) channel. Most previous studies have modeled Z-interference by fixing the GB or have investigated the Vt distribution without including Z-interference arising from random GB characteristics. However, there is a lack of research analyzing Z-interference in the program Vt distribution that results from random GB characteristics. Consequently, electrical characteristics corresponding to cell variation and GB variation were trained into a machine learning model through Technology Computer-Aided Design (TCAD) simulations to comprehensively analyze Z-interference and Vt distribution formation in victim (Vic) cells influenced by additional factors determined by random program verify (PV) levels of aggressor (Agr) cells, thereby performing Monte Carlo simulations on random strings. The proposed simulator enables prediction of the Vt distribution with Z-interference under both random and specific GB conditions, suggesting that precise control of grain boundaries during the fabrication process can establish useful design guidelines for process optimization in 3-D NAND flash memory.